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Assignment Four

Convert_float

my_float *convert_my_float(float num){ struct my_float * my_num = new(my_float); if (my_num) { union converter c; c.f = num;

my_num->sign = c.i >> 31; my_num->exponent = ((c.i >> 23) & 0xff); my_num->mantissa = (((c.i & 0x7FFFFF) | 0x800000) << 3) ;

}

return my_num;}

Print Binary function

void print_binary(int num){ unsigned mask = 0x80000000; int anded;

for (int i = 0; i < 32; i ++) { if ((i > 0) && (i % 4) == 0) cout << " " ; anded = num & mask; if (anded) { cout << "1"; } else { cout << "0"; } mask = mask >> 1; }}

Add function

struct my_float * my_float_add(struct my_float *first, struct my_float *second,\ int rnd_mode){ int first_mantissa = first->mantissa; int second_mantissa = second->mantissa; int exp_diff = first->exponent - second->exponent;

my_float *my_result = new(my_float);

DBG(cout << "Starting to add" << endl); if (exp_diff > 0){

#define DBG(a) a

Processor Design

• Clocking Methodology– Defines when signals can be read and written

– Going to assume and edge triggered clocking methodology

Clock cycle

Stateelement

1Combinational logic

Stateelement

2

Control Step

• Each control step takes one clock cycle

Clock cycle

Source registers output here

Destination registers read values here

Signals propagate through system

Stateelement

Combinational logic

Datapth Design

Chapter 5 P & H

Introduction

• Deigning an implementation which contains subset of core MIPS instruction set:– Memory reference instructions (lw & sw)– Arthitmetic-logic instructions (add, sub, and, or

and slt)– Branch an d jump instructions (beq, j)

Overview of Implementation

• Consider exection of an instruction

• First two steps identical– Use PC to fetch an instruction from memory– Read 1 or 2 registers as specified in instruction– Rest of steps dependent on instruction class

• Most will use ALU

• Many write value back to register file

Overview of Implementation

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

• Will start with simple single cycle implementation• Implementation will comprise datapath plus

control

Instruction Fetch

PC

Instructionmemory

Readaddress

Instruction

4

Add

R-type Instructions

O P(6 b its )

R S(5 b its )

R T(5 b its )

R D(5 b its )

S H A M T(5 b its )

F U N C(6 b its )

Components

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

Datapath for R-Type Instructions

InstructionRegisters

Writeregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Zero

RegWrite

ALU operation3

lw and sw Instructions

• Lw $7, offset($8) or sw $7, offset($8)

• These instructions– Compute the memory address (16 bit signed offset + base register)

– If sw then value must also be loaded from reg file

– If lw the value read from memory must be stored to reg file

O P(6 b its )

R S(5 b its )

R T(5 b its )

IM M E D IA T E(1 6 b its )

Datapath for lw and sw

Instruction

16 32

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Datamemory

Writedata

Readdata

Writedata

Signextend

ALUresult

ZeroALU

Address

MemRead

MemWrite

RegWrite

ALU operation3

beq Instruction

• beq $7, $8, offset• If ($7 == $8) then pc <= pc + 4 + (offset << 2)else pc <= pc + 4

beq datapath

16 32Sign

extend

ZeroALU

Sum

Shiftleft 2

To branchcontrol logic

Branch target

PC + 4 from instruction datapath

Instruction

Add

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

RegWrite

ALU operation3

Simple Implementation Scheme

• All instructions execute in single clock cycle:– No data path resource used more than once per

clock cycle– Components of different instruction classes

may be shared if no conflicts occur• May require multiple connections to same input

• Multiplexer used to select appropriate input

Combining datapath for R-type and memory instructions

• Datapaths very similar

• Two main differences– Second input to ALU is a register (for R-type)

or signed extened lower half of instruction (lw and sw)

– Value stored in dest register comes from ALU (R-type) or memory (lw)

Combined Datapath

I n s t r u c t i o n

1 6 3 2

R e g is t e r s

W r i t e

re g i s t e r

R e a d

d a t a 1

R e a d

d a t a 2

R e a d

re g i s t e r 1

R e a d

re g i s t e r 2

D a t a

m e m o r yW r i t e

d a t a

R e a d

d a t aM

u

x

M

u

xW r i t e

d a t a

S i g n

e x t e n d

A L U

r e s u l t

Z e r o

A L U

A d d r e s s

R e g W r i t e

A L U o p e r a t i o n3

M e m R e a d

M e m W r i t e

A L U S r c

M e m t o R e g

Adding Datapath for instruction fetch

P C

I n s t r u c t io n

m e m o r y

R e a d

a d d r e s s

In s t r u c t i o n

1 6 3 2

R e g is te r s

W r ite

r e g is te r

W r ite

d a ta

R e a d

d a ta 1

R e a d

d a ta 2

R e a d

r e g is te r 1

R e a d

r e g i s t e r 2

S ig n

e x t e n d

A L Ur e s u l t

Z e r o

D a ta

m e m o r y

A d d r e s s

W r i te

d a ta

R e a d

d a taMux

4

A d d

Mux

A L U

R e g W r i t e

A L U o p e r a t io n3

M e m R e a d

M e m W r i t e

A L U S r c

M e m t o R e g

Add in beq components

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

WriteregisterWritedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

ALU Control

ALU control input

Function

000 AND

001 OR

010 ADD

110 Subtract

111 Set on less than

• For R-Type instructions need to perform operation dependent of function field

• For load instructions use ALU to compute memory address by addition

• For branch instructions ALU used for subtraction

ALUOp operation

00 Add

01 Subtract

10 Use func field

A L U C o n tro l

A L U O p fu n c

2 6

O p e ra tio n

3

Truth Table for ALU controlALUOp Funct field Operation

ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F00 0 X X X X X X 010X 1 X X X X X X 1101 X X X 0 0 0 0 0101 X X X 0 0 1 0 1101 X X X 0 1 0 0 0001 X X X 0 1 0 1 0011 X X X 1 0 1 0 111

• Note multiple levels of control– Main control unit generates ALUOp

– ALU control generates operation

Main Control Unit Design

• Opcode fiels always bits 31 – 26 (Op[5-0])• Two regs to be read are always rs and rt• Base reg for loads and stores always rs• 16 bit ofset always bits 15 – 0• Destination register is in one of two places

– Rtype instructions RD– Lw it is RT

0 R S R T R D S H A M T F U N C

3 5 o r 4 3 R S R T IM M E D IA TE

4 R S R T IM M E D IA TE

Datapath

MemtoReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

RegWrite

4

16 32Instruction [15– 0]

0Registers

WriteregisterWritedata

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address Readdata M

ux

1

0

Mux

1

0

Mux

1

0

Mux

1

Instruction [15– 11]

ALUcontrol

Shiftleft 2

PCSrc

ALU

Add ALUresult

Control Signals

Datapath with Control Unit

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31 26]

4

16 32Instruction [15 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress