Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in...

424 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 3, MARCH 2012

Test Pattern Generation for Multiple AggressorCrosstalk Effects Considering Gate Leakage Loading

in Presence of Gate DelaysAlodeep Sanyal, Member, IEEE, Kunal Ganeshpure, Member, IEEE, and Sandip Kundu, Fellow, IEEE

Abstract—Decreasing process geometries and increasing op-erating frequencies have made VLSI circuits more susceptibleto signal integrity related failures. Capacitive crosstalk on longsignal nets is of particular concern. A typical long net is capac-itively coupled with multiple aggressors and also tend to havemultiple fan-outs. Gate leakage current that originates in fan-outreceivers, terminates in the driver causing a shift in driver outputvoltage. This effect becomes more prominent as gate oxide isscaled more aggressively. Thus, in nano-scale CMOS circuits,noise margin gets eroded by both aggressor crosstalk noise as wellas gate leakage loading from fan-outs. In this paper, we present anautomatic test pattern generation solution which uses 0–1 integerlinear programming to maximize the cumulative voltage noise ata given victim net because of crosstalk and loading in conjunctionwith propagating the fault effect to an observation point. Thetarget ISCAS benchmark circuits are assumed to have unit gatedelays. Results demonstrate both the viability of a solution as wellas a need to consider both sources of noise for signal integrityanalysis. Pattern pairs generated by this technique are useful forboth manufacturing test application as well as signal integrityverification.

Index Terms—Aggressor, automatic test pattern generation(ATPG), capacitive cross-coupling, circuit transformation, integerlinear programming (ILP), leakage, loading effect, max-satisfia-bility, signal integrity, victim.

I. INTRODUCTION

I NCREASE in circuit density and switching speed has ledto an increasing number of signal integrity related failures

in VLSI circuits [1]. Capacitive crosstalk is one of the majorsources of such failures. Crosstalk fault results from parasiticcoupling between adjacent signal nets and is more common innets that have weaker drivers relative to their adjacent peers.Current trends in integrated circuit design indicate that inter-connect sidewall coupling capacitances can be significant, thusincreasing the parasitic coupling.Crosstalk effects can be categorized into two types: 1)

crosstalk induced pulses and 2) crosstalk induced delay. The

Manuscript received March 23, 2010; revised October 12, 2010 and De-cember 07, 2010; accepted December 07, 2010. Date of publication February07, 2011; date of current version February 17, 2012. This work was supportedin part by the Semiconductor Research Corporation under Contract 1420.A. Sanyal is with the Test Automation Products Research Division, Synopsys

Inc., Mountain View, CA 94043 USA (e-mail: [email protected]).K. Ganeshpure and S. Kundu are with the Electrical and Computer Engi-

neering Department, University of Massachusetts, Amherst, MA 01003 USA(e-mail: [email protected]).Digital Object Identifier 10.1109/TVLSI.2011.2106169

first manifests as a pulse on a line, called the victim, whichshould remain in a static state when one or more capacitivelycoupled neighboring lines, called the aggressors, have a tran-sition. Depending on their amplitude and width, these pulsesmay cause logic malfunction [2]. The second effect, crosstalkdelay, is observed when both the aggressor(s) and victim netshave simultaneous or near-simultaneous transitions. If bothlines undergo transition in the same direction, their transitiontimes are reduced causing a reduction in effective delay. Werefer to this phenomenon as crosstalk speedup. If, on the otherhand, the aggressor(s) and victim switch in opposite direction,then there will be an increase in delay, which is called crosstalkslowdown. These unexpected changes in signal propagationdelays may also cause faulty behaviors and adversely affect thecircuit performance [3].Signal integrity problems have been aggravated by variations

in the fabrication process [1] or usage of dynamic logic families[4]. With scaling, the problem gets exacerbated due to reducednoise threshold and increased noise arising out of sharper signaltransitions.Gate leakage current due to reduced oxide thickness has

emerged as a major concern in sub-65-nm technology nodes. Infact, gate leakage is expected to increase at least by a factor of10 for each of the future generations [5]. Recent studies [6],[7] show that different sources of leakage can affect each otherby interacting through resultant intermediate node voltages,known as the loading effect. The effect of loading is expectedto grow more prominent with further scaling of device dimen-sions. Recent introduction of high-K gate dielectric materialprovides a one time relief from gate oxide leakage, whichincreases again as dielectric thickness is scaled.Since loading effect perturbs internal node voltages, noise

margins are reduced further. Recently, through a dynamicsimulation-based study, we showed that loading effect in-duced voltage noise acts as a significant aggravating factorfor crosstalk related signal integrity problem [8]. We inferthat combination of these two noises will likely worsen withscaling as load voltage erodes noise margin further while noiselevel increases due to sharper signal transitions. Therefore, gateleakage induced loading should be considered during signalintegrity analysis for nanometer CMOS designs.If it were not for stringent area and performance require-

ments, signal integrity problems observed during validationcould be eliminated by resizing drivers, rerouting signals,shielding interconnect lines with power distribution lines andother such redesign techniques. However, redesign may be very

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SANYAL et al.: TEST PATTERN GENERATION FOR MULTIPLE AGGRESSOR CROSSTALK EFFECTS 425

expensive in terms of design effort and its effectiveness maybe offset by process variation. Thus, these problems need to betested during manufacturing [9].Crosstalk-induced faults are observed more frequently for

long nets. A long net may have multiple fan-outs and may berouted through multiple levels of interconnect metals. Thus, atypical long net is capacitively coupled with multiple aggres-sors. Due to sharing of logic, it may not be possible to excite allaggressors while simultaneously sensitizing a victim net. More-over, even if all the aggressor nets for a given victim are ex-cited, it may not be possible to do so in close temporal proximitydue to gate delays. From an automatic test pattern generation(ATPG) point of view, the next best solution is to switch a setof aggressors in close temporal proximity so as to maximize theswitching of the total coupling capacitance [10] associated witha given victim net. In this paper, we combine this objective to-gether with setting the fan-out gates of the given victim in sucha state that it contributes maximal gate leakage loading noise tothe victim.We present a novel ATPG technique that employs integer

linear programming (ILP) to perform the following two tasks:• excite an appropriate set of aggressors in temporal prox-imity to a given victim net that causes maximal couplingnoise together with setting the fan-out gates of the victim ina logic state that contributes maximal gate leakage loading;

• propagate the fault effect by sensitizing a path from thevictim net to a primary output.

The proposed solution is based on unit gate delay model, thatis capable of modeling any integer gate delays. This helps im-prove the quality of test pattern by considering temporal prox-imity effects.The rest of this paper is organized as follows. In Section II

we review the related work. Section III establishes our modelof computation for cumulative voltage noise due to capacitivecross-coupling and gate leakage loading on a given net. InSection IV, we propose an ILP-based ATPG algorithm. Wepresent experimental results for ISCAS85 benchmark circuitsin Section V. In Section VI, we provide a detailed discussionon the scalability issues involved with the proposed ILP-basedsolution. Section VII concludes with a discussion on futureresearch directions.

II. RELATED WORK

With reduced noise margin and increased noise susceptibility,signal integrity analysis becomes a metric of comparable impor-tance to area, timing and power for nano-scaled CMOS processtechnologies. Existing literature on signal integrity related prob-lems can be broadly classified into three categories.

A. Crosstalk Noise Models

Sakurai et al. [11], [12] obtained a set of analytical formulaefor peak noise of capacitively coupled bus lines by solving thetelegraph equations. However, their approaches handle onlyfully coupled bus structures, not general resistance-capacitance(RC) trees. Vittal and Marek-Sadowska [13] modeled eachaggressor and victim net by an L-type RC circuit and obtainedclosed form expression for both peak noise upper bound andnoise-over-time integral. It showed improvement on the pure

charge-sharing model, but it assumed a step input for aggressor.Extensions to [13] were made by [14]–[16] to consider a satu-rated ramp input, or a -type lumped RC circuit. These models,however, did not consider the distributed nature of an RCnetwork. Devgan [17] proposed an elegant Elmore-delay likepeak noise model for general RC trees. However, this modelmay cause more signal integrity violations due to its pessimisticnature. Kong et al. [4] proposed an improved crosstalk noisemodel which takes into consideration few parameters such asaggressor slew at the coupling location, coupling location atthe victim net (near-driver or near receiver), etc.

B. RC Extraction From Layout

There are several commercial tools available to extract inter-connect RC network from layout. Cadence SOC Encounter [18]was used in this paper to extract parasitic RC data for ISCAS-85benchmark.

C. ATPG for Crosstalk

Test generation for signal integrity problems focuses sep-arately on delay failures and logic failures. Few notablecrosstalk-induced delay failures related test generation ap-proaches include a mixed signal test generator by Chen etal. [3]; a GA-based test generator by Krstic et al. [19]; and amultiple aggressor crosstalk-induced delay problem studied byPaul and Roy [20]. Ganeshpure and Kundu recently proposed aheuristic ATPG solution for multiple aggressor crosstalk delayfailures considering zero delay [21] and unit delay models [22].These solutions are based on a heuristic combination of ILPand stuck-at-fault ATPG. In case of crosstalk-induced logicfailures, Chen et al. [9] presented a crosstalk ATPG solutionfor single aggressor-single victim scenario. Bai et al. [23]proposed a heuristic solution for multiple-aggressor crosstalkATPG problem. The ATPG techniques for crosstalk-inducedlogic failures approaches to find a pair of test vectors thatcreate the condition for logic violation in a given victim net byappropriately switching the aggressors, followed by finding asensitized path from the logic violation point to an observableoutput. Through a dynamic simulation-based study, we recentlyshowed that gate leakage loading plays an important aggra-vating factor in the context of signal integrity problems fornano-scale CMOS VLSI circuits [8]. In this paper, we proposea composite ILP-based approach that causes maximal noisedue to crosstalk and gate leakage loading on a given victim netas well as sensitize a path from the victim to a primary outputto observe the fault effect.

III. IMPACT OF LOADING EFFECT ON SIGNALINTEGRITY ANALYSIS

Before going into the detail of the models used for loadingeffect and capacitive crosstalk-induced voltage noise estimationand their collective behavior, let us first establish the problemwith the aid of an example as described in the following.Example 1: Let us consider the smallest ISCAS-85 bench-

mark C17 which involves six two-input NAND gates (see Fig. 1).The circuit has five primary inputs and twoprimary outputs . We first apply an input pattern

and perform logic simulation. The output of gate


Fig. 1. Illustration of signal integrity problem due to combined effect of capac-itive crosstalk and gate leakage loading on ISCAS-85 benchmark C17.

is in logic state 0 and both its fan-out gates and arein logic state 1. Therefore, gate leakage current flows fromthese two fan-out gates ( and ) toward the output net ofand causes a loading voltage noise (say, ).Now, let us apply a second input pattern .

Logic simulation is performed and the new logic state at theoutput of each gate is shown in the figure. The output of gateremains at logic state 0. We notice that the output net of

is capacitively coupled with the output net of gate and(coupling capacitance values being and , respectively).With the pattern pair both these aggressor nets (viz.and ) switch from logic state 0 to 1, while the victim netretains its logic state. Due to capacitive cross-coupling ef-

fect, this logic condition will draw coupling current towardthe victim net and produce a crosstalk voltage noise .If the cumulative voltage noise at the

victim net exceeds the minimum logic switching thresholdvoltage of all its fan-out gates (viz. and ), it will beflagged as a logic violation. Clearly, a logic violation will man-ifest as an error if it finds a sensitized path to an observationpoint. Incidentally, in this case as the output of both the fan-outgates and are primary outputs and a logic violation atthe input coming from causes a change at output logic stateof both and , they will also cause error at the primary out-puts.In the following sub-sections we explain in detail the models

used for loading effect and crosstalk-induced voltage noise es-timation and their collective behavior in the context of signalintegrity analysis.

A. Model for Loading Effect-Induced Noise CurrentEstimation

There have been previous studies considering the impact ofloading effect in leakage estimation [6], [7]. Mukhopadhyay etal. [6] first showed that the impact of loading effect would be-come significant as we move deeper into the nanometer regime.However, they did not consider pattern dependence on loadingeffect. Later, we proposed a pattern-dependent logic state-basedtotal leakage estimation technique [7]. We validated our modelagainst SPICE simulation results.Consider the case of leakages in C17 benchmark circuit as

shown in Fig. 1. The gate leakage currents from input of gatesand enter the output node of causing a small increase

Fig. 2. Transistor terminal states considered in Table I.

TABLE IGATE LEAKAGE FOR DIFFERENT BIAS STATES FOR 65-nm

PMOS AND NMOS DEVICE

in its output voltage (we called it in the previous example).Now the gate bias on devices in gates and is greaterthan zero. This in turn increases the sub-threshold leakage ingates and . This is known as loading effect and it dependson the number of fanout gates and input pattern applied.For a given set of logic values in source, drain and gate of

a transistor, all the three major sources of leakage (viz. gateleakage, band-to-band tunneling leakage and sub-thresholdleakage) vary almost linearly with transistor width. Therefore,we can construct lookup tables that can compute leakagecurrent for given state values.Let us consider a single transistor a three-terminal device

(source, drain and gate) that can be connected to (logic 1)or Ground (logic 0) in various ways. It leads to a possibility ofmaximum distinct states, among which six are consid-ered stable states. The basic idea behind using state-based gateleakage estimation was presented by Rao et al. [24]. We adoptthis logic state-based model for estimating the impact of loadingeffect in this paper. For each state shown in Fig. 2, values ofgate leakage current are computed using Berkeley PredictiveBSIM4 models for 65-nm technology [25], [26] and stored in a3-D array denoted by and . Table Ishows the values that were computed using these predictivemodels.The gate leakage values for each transistor in the cell are

added to obtain the loading current. Fig. 3 shows an example ofa circuit with a NOR gate connected to a number of fan-outgates. Gate leakage from each of the fan-out gatesleads to the loading current at the output node of the driver.This increases the gate voltage on the transistors in fan-out gates


Fig. 3. Effect of loading current illustrated at (left) gate level and at (right)transistor level showing the bias states in the fan-out gates.

Fig. 4. Illustration of an aggressor-victim model used for crosstalk analysis.

by , which causes a change in the sub-threshold and gateleakage current. We employed a technique conceptually similarto the one presented in [27] to compute the loading voltage .

is used to adjust sub-threshold leakage values of thedriven gates. Such adjustments will invariably lead to smallchanges at output voltages of the driven gates, which in turnwill impact the gate leakage. Newton-Raphson method has beensuccessfully used in this context [28] and we have incorporatedthis feature in our analysis. To account for Newton-Raphsonmethod, loading voltages are readjusted in an iterative fashionstarting with a baseline value till the difference in is lessthan 5% for two consecutive iterations. Here, instead of usingstate-based lookup table as mentioned earlier, we use a set ofpiecewise linear equations for gate current as a function of gatevoltage for selected values of drain voltages tuned to deliverhigher accuracy.

B. Capacitive Crosstalk-Induced Noise Current Estimation

There has been a detailed study on developing crosstalk noisemodel over the last decade as we have reported in Section II. Inthis paper, we have adopted a fairly simple model to computecrosstalk-induced noise current, which is conceptually similarto the model proposed by Devgan [17].To derive the generalized expression for crosstalk-induced

noise current, let us start with a situation where a victim nethas two aggressors ( and ) in the neighborhood (see

Fig. 4). Let the coupling capacitance between the victim andaggressor be and that with the aggressor be .Let us assume an input transition in the circuit involving these

nets such that the victim stays in the same logic state 0,

TABLE IIDEPENDENCE OF ON VARIOUS SCENARIOS OF AGGRESSOR TRANSITIONS

WHEN VICTIM REMAINS SILENT AT LOGIC STATE 0 OR 1

whereas both the aggressors ( and ) switch from logic state0 to 1 (as shown in Fig. 4). Under this condition, coupling cur-rent will flow from the aggressors to the victim net through theappropriate coupling capacitor.Coupling current ( and ) at instant can be expressed as

(1a)

(1b)

The total coupling current at the instant should be obtainedby simply adding the individual coupling current from the ag-gressors provided these aggressors undergo transition within aspecific time window

(2)Therefore, in the most general scenario, if a victim net

has aggressors and under a specific inputtransition all of these aggressor nets switch from logic state 0 to1 or from 1 to 0 keeping the victim net silent, the expression fortotal coupling current would be

(3)

When coupling effect on the aggressor itself is not consid-ered, the term can be simplified as the slew ratecorresponding to the rise time (or, fall time) of the individualaggressor net; i.e., the numerator corresponds to thechange in voltage from 0.1 to 0.9 times and the denomi-nator is the rise time or the fall time associatedwith it. Accordingly, the generalized expression for couplingcurrent can be restated as

(4)

where the term depends on the direction of transition of theaggressor relative to the victim net and the correspondingrise time or fall time associated with it as shown in Table II.The positive or negative sign on the factor represents the

case when a given aggressor acts toward contributing or com-pensating the overall noise.Moreover, the term is scaled in a manner proportional to the

time difference between the aggressor and victim transitions asshown in Table II. We consider a window size of 3 between theaggressor and the victim time slot for a particular aggressor tobe considered for the given victim. Table III summarizes scaling


TABLE IIISCALING OF THE FACTOR

of the term with respect to temporal proximity between anaggressor and a victim.Expression (4) has been used in this paper to compute cou-

pling current for a given victim net.

C. Combined Loading Effect and Crosstalk-Induced Noise

We use a simple way to find the total noise voltage in-duced by loading and capacitive cross coupling at an instant .Considering the fact that crosstalk current exhibits a transientbehavior over a pattern pair whereas gate leakage is a static ef-fect for a given pattern, we compute crosstalk current fora given pattern pair and gate leakage current for the firstpattern of the pair, followed by adding them together to find thetotal noise current at the instant after application of thesecond pattern

(5)

In this paper, we focus on creating the peak noise current. Itis shown that noise with small height and large width can beeasily filtered out using appropriate gate sizing and/or bufferinsertion methodology [29]–[31]. Therefore, higher the noiseheight, higher will be the probability of latching an incorrectlogic value.After obtaining the total noise current , we apply the same

regression-fitted piecewise linear equations we used to computeloading voltage (as described in Section III-A) to obtain the finalnoise voltage .

IV. PROPOSED SOLUTION

The problem of generating a pattern pair that results in max-imal voltage noise due to combined effect of coupling and gateleakage loading in conjunction with propagating the fault effectto an observable point primarily has the following two aspects.Goal I: Creation of maximal voltage noise due to coupling and

gate leakage loading at victim: As the victim net is cou-pled with multiple aggressors, we have to find a subsetof aggressors in temporal proximity with the victim thatcreates maximal coupling noise at the victim net. Ad-ditionally, the victim fan-outs are set to logic states tomaximize loading current at the victim net.

Goal II: Propagation of fault effect to the output: In addition tomaximal noise creation, the pattern pair must also prop-agate the fault effect at the victim net to an observationpoint.

This problem falls into the class of max-satisfiability prob-lems [32]. Max-satisfiability is a known intractable problem[32]. In this paper we present a complete solution to the problemby mapping it to an ILP formulation. Thus given enough time,

Fig. 5. C17 benchmark circuit with various switching times.

we will be able to obtain an input pattern pair that leads toabsolute worst case voltage noise due to combined effect ofcrosstalk and gate leakage loading on a given victim net.Given a set of aggressors coupled with

a victim and a set of fan-out gates drivenby the victim, we perform the following two steps.

A. Circuit Transformation

1) Time Domain Expansion to Incorporate Gate Delays: Ithas been shown previously that gate delay plays an importantrole in the context of crosstalk related signal integrity analysis[22]. In this paper, we assume unit gate delay model. We as-sume that it takes 1 unit of time between 50% transition of theinput to the 50% transition of the output for any given gate. Unitgate delay model allows arbitrary integer delays through circuittransformation that adds buffer chain. Consideration of delaysallows temporal proximity between an aggressor and a victimto be considered, improving the quality of the solution. If an ag-gressor does not switch within a finite time window with respectto the victim, it should not affect the victim under consideration.The main goal of time domain expansion is to translate a cir-

cuit structure under unit delay model to an equivalent expandedcircuit with zero delay. There is a one-to-one correspondencebetween the transitions in the original circuit and XOR outputsof the expanded circuit where the XORs are used for the samegate outputs in two consecutive time slots in the expanded cir-cuit [33]. The following example explains the step more clearly.Example 2: Let us consider the ISCAS-85 benchmark circuit

C17 as shown in Fig. 5. The numbers at the gate outputs repre-sent the possible signal arrival times corresponding to the delaysof all the possible paths in the input logic cone of the gate. It isassumed that the initial pattern of the pair is already applied tothe circuit before time and the second vector is applied attime . The expanded circuit is shown in Fig. 6. It can beseen that the gates are replicated as many times as the number ofpossible propagation times in the original circuit. For example,gate number 23 has 3 propagation times . Therefore,it is replicated three times corresponding to time slots , and. Moreover, the inputs to each of the replicas of the gate 23 are

connected to the replicas of the gates 16 and 19 in the previoustime slot.We observe that the unit delay to zero delay circuit transfor-

mation approach results in a linear increase in the number ofgates. This is illustrated with the following example.Example 3: Consider the ISCAS-85 benchmark C17 which

is shown in Fig. 7. In Fig. 7(a) all gates have unit delay. This


Fig. 6. Example showing unit to zero delay circuit transformation of the ISCAS-85 benchmark C17.

can be transformed into a functionally equivalent 0–1 delay cir-cuit where all combinational gates have 0-delay and sequentialgates with unit delay by using a transform as shown in Fig. 7(b).Circuit (b) may be redrawn as circuit (c) in the form of a classicMealy machine. When this Mealy machine is transformed intoan iterative logic array (ILA) by unrolling the feedback, we ob-tain the circuit in Fig. 7(d), where each gate has 0-delay. ThisILA has the same number of stages as the maximum path delayin Fig. 7(a). Functionally, the circuit (d) remains equivalent to(a). In the process of this transformation, the number of combi-national gates in circuits (a) to (c) remain the same, while thenumber of gates in (d) is at most maximum path length in (a)times the number of gates in (a). This completes the proof illus-trating that the unit delay to zero delay circuit expansion resultsin linear increase in the number of gates. This proof can furtherbe generalized to floating delay circuits on the basis of proce-dure in [34] that transforms floating delay circuits into unit delaycircuits.The transition of aggressors and victim nets is indicated

by XORing the corresponding outputs at two consecutive timeslots. We use a variable to evaluate the condition for anaggressor undergoing transition between time slots and

.2) Fault Effect Propagation: We perform circuit transfor-

mation in the output logic cone of the victim net in order togenerate conditions for fault effect propagation. In this step theoutput logic cone including the victim is duplicated. The orig-

inal logic cone represents the good machine while the dupli-cated logic cone represents the faulty machine. In addition, avalue is generated for each gate in the fault propagation cone byXORing the corresponding gate outputs of the two logic cones.A value represents the case where the faulty value and goodvalue are different i.e. the fault effect is being propagated. ILPformulation is done subsequently to propagate the value fromvictim net to the primary outputs. The following example helpsunderstand the step.Example 4: In Fig. 6, the output logic cone of the victim net

a11_1 (where a11 is gate number and 1 is the time slot of thegate) is represented using broken line. The duplicated gates arerenamed by replacing the prefix a with b. Inputs to the dupli-cated gates which are not a part of the output logic cone of thevictim net are supplied from the corresponding gates in originalcircuit. For example, for the gate b22_3 in the duplicated cir-cuit, the input (represented by a continuous line) which is not apart of the output logic cone of the victim comes from the gatea10_1 of the original circuit. Fault effect propagation is indi-cated by XORing the corresponding outputs of the original andthe duplicate circuits to generate value. For example, the netsa16_2 and b16_2 are XORed to obtain value of d16_2. ILPformulation is done using values for fault propagation.

B. ILP Formulation

In order to obtain the maximal noise due to combined effectof crosstalk and gate leakage loading for a given victim net in a


Fig. 7. Example showing linear increase in circuit size by time domain expan-sion of the ISCAS-85 benchmark C17: (a) original circuit C17 under unit delaymodel; (b) 0-1 delay model equivalent of circuit C17; (c) mealy machine repre-sentation of circuit C17; and (d) iterative Logic Array (ILA) representation ofthe model in (c) after unrolling the feedback.

circuit, ILP formulation is done for the circuit by writing the ILPequations for the logic gates [36], which are formed by using theclausal description of the function of the gates as developed byLarrabee [37]. For example for an AND gate with inputs , andoutput , we can describe all four input-output combinations aspresented in (6a)–(6d)

or (6a)

or (6b)

or (6c)

(6d)

For the circuit shown in Fig. 8 the complete set of ILP equationsare presented in (7a)–(7h)

(7a)

(7b)

(7c)

(7d)

(7e)

(7f)

(7g)

(7h)

Fig. 8. Example combinational logic block.

With a brief discussion on ILP formulation using clausal de-scription of the functionality of different gates, we now focus ondeveloping the constraints for: 1) switching of aggressors in away that causes maximal crosstalk noise at the output of a givenvictim net keeping the victim silent at either logic state 0 or 1; 2)set the fan-outs of the victim in such a state that it causes max-imal loading noise at the victim; and 3) assuming the cumulativevoltage noise causes a logic violation at the fan-out stage, prop-agate the fault effect to an observation point.We assume a set of aggressors coupled

with a victim and a set of fan-outs as-sociated with them. Suppose there are copies of the victimpresent in the expanded circuit starting from the time slot totime slot . The variable representing the victim at time slotis denoted . For the crosstalk pulse problem, we considerthe victim to be static either at logic state 0 or 1. This assumptionis based on the fact that the effect of usual sources of signal noisewill be insignificant in the context of worst case noise producedby the combined effect of crosstalk and gate oxide loading [35].The following constraint represents this condition.Constraint 1: Victim static at its logic state for any two con-

secutive time slots and

(8)

1) Constraints for Maximal Crosstalk Noise: We considerany aggressor which makes a transition (either or

) at time slot within a time window of 2 with respect tothe victim’s current time slot toward computing the cumulativecoupling noise and define a variable such that

(9)

where the variable representing the aggressor at time slotis denoted as . We also define a variable to

represent the condition that the final value of the aggressorat time slot and the victim at time slot are opposite

(10)

To determine whether a given aggressor transition acts towardcontributing or compensating the cumulative coupling noise, wepropose the following two constraints.Constraint 2: If a given aggressor switches at time slotsuch that the final logic value of the aggressor at time slot

and the victim at time slot are different, the aggressor is saidto contribute to the cumulative coupling noise.


Fig. 9. Illustration of gate leakage loading from fan-out nodes of a victim attime slot .

We express this constraint with the aid of the variablein the following way:

(11)

Constraint 3: If a given aggressor switches at time slotsuch that the final logic value of the aggressor at time slot

and the victim at time slot are same, the aggressor is said toact toward compensating the cumulative coupling noise.We express this constraint with the aid of the variable

in the following way:

(12)

With the aid of constraints 2 and 3 defined above, we may nowexpress the (4) describing the cumulative coupling noise causedby a set of aggressors for a given victim at the time slotin the following way:

(13)

2) Constraint for Maximal Gate Leakage Loading Noise:We now explain the formulation of ILP constraints that max-imizes gate leakage from fan-out nodes for a given victim net.After the circuit expansion step, a gate is replicated into varioustime slots. The idea here is to create appropriate input condi-tion at the fan-out nodes of a given victim to cause gate leakageloading from the fan-outs together with capacitive coupling in-duced signal noise through switching of the aggressor net(s) forthe victim net, at the same time slot. In order to maximize theeffect of gate leakage loading, the inputs of the fan-out gates ofthe victim should be set appropriately. The following exampleillustrates the point.Example 5: Let us consider a victim net at the time slotfor an example time expanded circuit shown in Fig. 9. The

instance of the two fan-out gates and for the victim copy

at time slot appear in next two time slots and , respec-tively, in the time expanded circuit. To enforce maximum gateleakage loading at the victim net at current time slot , theinputs to these two fan-out instances should be set in such a wayso as to obtain maximal gate leakage loading at the victim netat time slot . As shown in Fig. 9, the side input of fan-outinstance of at time slot appears in the previous time slot. The side input for the instance of fan-out at time slotappears in the current time slot . The ILP formulation is

done for the input and output logic cones of victim and theinput logic cone of the side input gates and .Constraint 4: In order to generate the ILP equations for

leakage current, Boolean variables indicating all the possibleinput combinations of the victim’s fan-out gates are generated.Then the total leakage is expressed as a linear combination ofthe binary variables representing individual input conditionweighted by corresponding logic states’ leakage weight. Forexample, for the circuit shown in Fig. 9, gates andwill be considered for leakage at the victim net at time slot .We define binary variables , , , and correspondingto every possible input condition for the fan-out gates and

as follows:

(14a)

(14b)

(14c)

(14d)

(14e)

(14f)

(14g)

(14h)

(14i)

(14j)

In (14e) and (14j), the variables and represent the gateleakage loading at victim at time slot coming from thefan-out gates at time slot and at time slot , re-spectively.Therefore, the general expression for total gate leakage

loading noise current over the entire set of fan-out gates for agiven victim at time slot is

(15)

where is the set of fan-out gates for the given victimnet at time slot .3) Formation of the Objective Function for the Combined

Signal Noise: The cumulative noise on a given victim netdue to capacitive cross-coupling with neighbor aggressor netsas well as gate leakage loading from its fan-out gates at a giventime slot is expressed as

(16)


Therefore, the objective function would be to maximize the cu-mulative noise over all the time slots to when thevictim is active

(17)

4) Constraints for Fault Effect Propagation: To ensure thepropagation of the fault effect from the output of the victim netto a primary output, we create a duplicate copy of the outputlogic cone of the victim , which represents the “faulty” value

for any given gate at the output logic cone of the victimat time slot . The “good” value of the gate is represented by

. The XOR of the “good” value and the “faulty” value attime slot , represented by the value will propagate thefault effect from the victim through the gate on its outputlogic cone

(18)

The following two constraints ensure that if a logic violation isobserved at the output of a victim , it will propagate to at leastone primary output.Constraint 5: Logical OR of value of all the primary out-

puts will be 1

(19)

where is the set of all primary outputs.Constraint 6: A value at a gate output implies that at least

one of the gate inputs in the output logic cone of the victim nethas a value.Therefore, for a gate at time slot with inputs at time

slot and at time slot , the following implication formallyexpresses the previous constraint:

(20)

Finally, in order to initiate fault effect generation at the victimnet, a value has to be enforced at all the copies of the victimnet starting from the first copy of the victim at time slot tofinal copy at time slot .In this paper, we primarily focus on developing the con-

straints for maximal noise generation. It is implicitly assumedthat the underlying support structures such as design-for-testa-bility (DFT) and the clocking mechanism are in place to detectthe glitch effect at an observable output.

C. ILP-Based Test Pattern Generation Algorithm

After establishing an ILP-based formulation of an objectivefunction aimed at maximizing the combined noise effect due to:1) capacitive interference between neighbor interconnects and2) gate leakage-induced loading from fanout nodes, we now for-mally present the test pattern generation algorithm MaxSig-nalNoiseATPG(), which accepts a circuit description anda list of capacitively coupled interconnect nets as input argu-ments. The objective of this algorithm is to separately generate

a pair of test patterns that maximizes:1) the capacitivecrosstalk noise and 2) combined signal noise on a given net.

Algorithm 1 MaxSignalNoiseATPG

1:2:3:4:5:6: for each member do7:8: if ( and

) then9:10:11: end if12: LogicViolation MaximizeCombinedNoise

13: if( and)

then14:15:16: end if17: end for18: return and

Algorithm 1 presents a pseudo-code description of the ATPGalgorithm. We begin with initializing sets and , whichare used to store the failing nets due to crosstalk and combinednoise effect, respectively. The sets and are used to storethe respective test pattern pairs for these failing nets. The vari-able LogicViolation is used as a flag to indicate whetherthe noise produced at a given interconnect net by a pattern paircrosses the logic switching threshold of its fan-out stage. Foreach member of the set of coupled nets , we invoke the pro-cedure MaximizeXtalkNoise() that first constructs an ILP-based model aimed at maximizing the crosstalk noise, followedby evaluating whether the crosstalk-induced signal noise ex-ceeds the logic switching threshold of the fan-out stage therebycausing a logic violation (line 7). If the variableLogicViola-tion is set to TRUE and the procedure PropagateFault-Effect() finds a sensitized path from the net to an observa-tion point (line 8), then the given net is included in the set ofcrosstalk-induced failing nets (line 9) and the corresponding testpattern pair is included in the set (line 10). Similarly, the pro-cedure MaximizeCombinedNoise() evaluates whether itis possible to cause a logic violation at a given net due tocombined noise effect (line 12). If the variable LogicViola-tion is set to TRUE and the procedure PropagateFault-Effect() finds a sensitized path from the net to an observa-tion point (line 13), then the given net is included in the set

of combined noise-induced failing nets (line 14) and the cor-responding test pattern pair is included in the set (line 15).Finally, the cardinality of the sets and are computed andreported (line 17).


TABLE IVSIGNAL INTEGRITY ATPG RESULTS FOR ISCAS-85 BENCHMARK CIRCUITS

V. EXPERIMENTAL RESULTS

A. Experimental Setup

We evaluated the effectiveness of the proposed test patterngeneration algorithm on ISCAS-85 combinational benchmarksuite. The experiments used an open source linear programsolver GNU Linear Programming Kit (GLPK) [46] with a userspecified time limit for each instance of the ILP.Computation of the loading effect requires a number of

lookup tables on a per cell basis. To keep this computationsimple, as well as fully validated, all the benchmark circuitswere initially mapped to a cell library consisting of only NOR2cell. The logic switching threshold for individual inputs of theNOR2 cell was obtained by running HSPICE [47] using 65-nmBPTM model [26]. Subsequently, a lookup table was createdto store the logic switching threshold for the two inputs of theNOR2 cell. Commercial use of this tool will require comprehen-sive leakage characterization of a wide variety of library cells.The parasitic RC data for 250-nm technology were extracted

in SPEF format using Cadence SOC Encounter tool [18] andsubsequently scaled down to 65-nm process. The SPEF fileswere parsed to list only the victim-aggressor information withassociated coupling capacitance values.The platform for these experiments was a Dell PowerEdge

2800 server [51] with 2.8 GHz dual core Intel Xeon processor,2 MB L2 cache and 2 GB RAM.In the following section, we present and analyze the experi-

mental data on ISCAS-85 benchmark circuits and compare theresults with respect to our previous dynamic simulation-basedstudy [8].

B. Results on ISCAS-85 Benchmarks

As the CMOS technology moves deeper into nanometerregime, sharper signal transitions and reduction of device noisemargin by various sources of noise start playing an importantrole in signal integrity analysis. As a first attempt to examinethe combined effect of different noise sources, very recentlywe performed a dynamic simulation based study to establishthe importance of considering gate leakage induced loadingnoise while performing signal integrity analysis for nano-scaleCMOS designs [8]. During dynamic simulation, we applied10 000 random input patterns to each circuit for identifying

the nets that cause logic violation at the fan-out stage underpattern-dependent dynamic environment. However, dynamicsimulation has the following two drawbacks: 1) it is not com-prehensive from test point of view as there could be cases ofviolating conditions that could lead to identifying a new set offailing nets, that are not exercised by the set of random patternsapplied and 2) dynamic simulation aims at identifying nets that,under the effect of noise, exceed the logic switching thresholdof their respective fan-out gates and therefore, cause logicviolations at the fan-out stage. However, dynamic simulationdoes not ensure that a logic violation, from the fan-out stage,will propagate to an observation point and get recorded as anerror.Motivated by the need for a test solution, in this paper, we

propose an ILP-based pattern generation technique for detec-tion of noise pulses caused by the combined effect of capacitivecross-coupling between neighbor nets and gate leakage inducedloading noise from fan-out nodes of a given driver net. The pro-posed algorithm retains the completeness of the solution in thesense that, given enough time and space, it will find out the pat-tern pair that causes maximal noise condition on a giveninterconnect net and evaluates the existence of a sensitized pathfrom the fault site to an observation point to propagate the faulteffect. Therefore, given a set of coupled nets for a given cir-cuit , the proposed technique identifies a subset offailing nets and their respective tests .In practice, we maintained a time limit of 1 h for every single

instance of ATPG for maximizing the crosstalk noise and a timelimit of 2 h for the corresponding instance for combined noiseeffect due to crosstalk and leakage loading. This differencein time allocation for the two separate cases of optimizationis based on the fact that the computation time needed by theILP solver is directly related to the number of constraints usedby an individual instance of the optimization problem. Sincethe problem instance for combined noise effect includes theconstraints for gate leakage loading as well, it is a prudentdecision to allocate a higher time limit for the case of com-bined noise effect. Table IV summarizes the results obtainedfor ISCAS-85 benchmark circuits. Column 2 reports the totalnumber of coupled nets in a given design. We ran ILP-basedtest generation algorithm for every single coupled net for agiven design. Columns 3 and 4 present the results on number


TABLE VWORST CASE CPU TIME REPORTED FOR AN INDIVIDUAL INSTANCE UNDER

PURE CROSSTALK AND COMBINED NOISE EFFECT

Fig. 10. Plot showing the worst CPU time taken by an individual instance ofthe ATPG for both cases of crosstalk and combined noise effect.

of logic violations reported from the dynamic simulation-basedstudy [8] on both the cases of crosstalk-induced noise aswell as the combined noise effect due to crosstalk and gateleakage-induced loading. Note that logic violation representsthe case when the noise pulse at a driver net crosses the logicswitching threshold of its fan-out stage and activates the faulteffect. It does not ensure that such a fault effect will eventuallypropagate to an observation point and get recorded as an error.For the proposed ATPG-based approach, three distinct possi-bilities exist: 1) a pattern pair is found that detects the fault atan observation point; 2) the ILP returns a no solution whichimplies that there exists no pattern pair that can simultaneouslycreate a fault effect and propagate it to an observation point; and3) the ILP solver runs out of maximum allocated time to solvea single instance of the problem. We report results for thesethree possibilities in three separate columns both for the casesof crosstalk-induced noise and the combined noise effect due tocrosstalk and loading. We observe that considering noise fromboth crosstalk and gate leakage loading can detect up to 64%more faults (column 8) as compared to the crosstalk-only case(column 5). Columns 7 and 10 reports the number of instancesthe ILP solver runs out of the maximum allocated time. InTable V and the associated plot shown in Fig. 10, we presentthe worst case CPU time reported for an individual instanceof the problem separately for the cases of pure crosstalk effectand the combined effect of crosstalk and loading. In the nextsection, we address the scalability issues involved with theproposed solution.

Fig. 11. Illustration showing the logic cones of interest for a typical instanceof the ATPG problem.

VI. DISCUSSION ON SCALABILITY OF THE

PROPOSED APPROACH

In this section, we show that the proposed solution is highlyscalable. We present the scalability of this approach in terms ofcrosstalk ATPG performance, resulting size of the test set andability to handle non-unit gate delays.

A. Performance

Scalability of the solution is related to the number of ILPequations for an individual instance of the problem. Fewer thenumber of equations, greater is the likelihood of finding an exactsolution. The number of equations in turn relate to the cone oflogic needed to formulate justification and propagation condi-tions for the crosstalk fault as shown in Fig. 11, which in turnrelates to logic depth. It has been noted that, in modern designsthe logic depth tends to be shallow: typically 6–8 levels of logicgates [48]. Also, in CMOS circuits, the number of fan-ins is lim-ited due to nonlinear increase in gate delay with transistor stackheight. Typically, the number of fan-in in CMOS gates is limitedto 4 [49]. Thus the number of gates in a logic cone in a circuitof logic depth and fan-in of is of the order of . Whenthe unit delay model is considered, worst case size of such logiccone is of the order of . In ISCAS circuits, the logic depthtends to bemuch greater. In fact for C3540, for which we had theworst case CPU time (as shown in Table V and plot presentedin Fig. 10), the logic depth is 47. The logic cone of interest iscorrespondingly much larger than expected logic cone size ofmodern designs leading to a significantly high run time. Thecircuit C6288 is a 16-bit multiplier and stands as a nemesis casefor ILP-based approach. We observe a time-out for each of the


33 capacitively coupled nets for this circuit. It may be of interestto note that in circuits where the total gate count was larger thanC3540, but the combinational logic depth was smaller (such asC5315 and C7552), the worst case CPU time reported was ac-tually lower compared to the case for C3540 (as shown in theplot in Fig. 10) for the reasons described above.

B. Test Compression

A notable benefit of the proposed approach is in test compres-sion. Test compression works best when some of the inputs in atest vector are not specified. In a multi-million gate design, thelogic cone of interest includes only a small fraction of the in-puts. Since ILP formulation does not include inputs outside thecone of interest, they remain unspecified. Thus the test cubespossess characteristics for good compression. Even for the in-puts included in the ILP formulation, which get fully specifiedduring ILP solution, some of them may be turned back to ’sthrough backward bit-relaxation process. This technique was re-cently employed by the authors [50] in the context of patterngeneration for soft error rate testing.

C. Beyond Unit Delay

If gates in a circuit have integer delays, they can easily beconverted to unit delay circuit using miter gates [34]. For ex-ample, if a NAND gate has delay of 3, we can insert two buffersbetween NAND gate output and its fan-outs. If all gates in thenew circuit have unit delay, it has the equivalent behavior of theoriginal circuit. Note that this will not increase the number ofequations in our formulation. The solution extends to circuitswith real delays that can be normalized to have equivalent in-teger delays.

VII. CONCLUSION AND FUTURE DIRECTIONS

It is well known that crosstalk noise may lead to signal in-tegrity violation. It was also shown previously that loading ef-fect from gate leakage may lead to signal integrity problems. Inthis paper, we have shown that crosstalk noise and gate leakage-induced loading noise may combine together to aggravate signalintegrity problems even further. Most signal integrity analysistools are concerned with trigger of an error signal at an interme-diate node. In reality, such errors may not propagate to an ob-servation point due to logic value constraints and may remainas observability don’t care event.In this paper, we have proposed an ATPG algorithm that

uses 0–1 ILP to attain the goals of: 1) formulating an objectivefunction for maximizing combined signal noise due to crosstalkand leakage loading and 2) finding a sensitized path from thegiven victim net to an observation point. Events triggered bythis ATPG patterns will propagate to an observation point,making them useful for both manufacturing test applicationas well as signal integrity verification. The proposed ATPG iscapable of handling logic dependencies as well as temporalproximity effects as modeled by integer delays.This paper may further be extended to study other noise ef-

fects in tandem including voltage drop and temperature effects.

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Alodeep Sanyal (M’06) received the Bachelor ofTechnology degree in electronics and telecommuni-cations engineering from the University of Kalyani,India, in 2002, the Master of Science degree incomputer science from Colorado State University,Fort Collins, in 2005, and the Doctor of Philosophydegree in computer engineering from the Universityof Massachusetts, Amherst, in 2010.He is currently employed as a research staff

member at the Test Automation Products Division,Synopsys Inc., Mountain View, CA. His research

interests primarily include the areas of computer-aided design and test fornanoscale CMOS VLSI circuits and emerging devices and systems. He haspublished over 25 papers in leading journals and conferences in the field.Dr. Sanyal is a member of the IEEE Computer Society and the ACM

Special Interest Group on Design Automation. He is a reviewer of the IEEETRANSACTIONS ON COMPUTERS, IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN AUTOMATION OF INTEGRATED CIRCUITS AND SYSTEMS, IEEETRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, andthe Journal of Electronic Testing: Theory and Applications.

Kunal Ganeshpure (M’09) received the Bachelorof Engineering degree in electronic and communica-tion engineering from The Maharaja Sayajirao Uni-versity of Barodais, Baroda, Gujarat, India. He is cur-rently pursuing the Ph.D. degree from the Electricaland Computer Engineering Department, Universityof Massachusetts, Amherst.He has worked in the area of ATPG for supply

current maximization, multiple aggressor crosstalkATPG. He has also worked in the area of thermalsimulation and thermal aware physical design.

Currently he is working in SoC synthesis and scheduling problems. He haspublished around 19 papers including those in conference and journals in theabove areas.Mr. Ganeshpure was a recipient of a Gold Medal for being on the top most

echelon of the class.

Sandip Kundu (M’86–SM’94–F’07) is a Professorof Electrical and Computer Engineering with theUniversity of Massachusetts, Amherst. Previously,he was a Principal Engineer with Intel Corporationand Research Staff Member with IBM Corporation.He has published over 150 papers, holds 12 U.S.patents, and has given more than a dozen tutorials atconferences.Dr. Kundu was the Technical Program Chair of

ICCD in 2000 and General Chair in 2001. He is theTechnical Program Chair of Asian Test Symposium

2011. He also served as a co-General Chair of VLSI 2005 conference. Heis a distinguished visitor of IEEE Computer Society. He has served as anAssociate Editor of the IEEE TRANSACTIONS ON COMPUTERS and the IEEETRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.

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