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RAM Organization

OUTPUT BUFFER

b63

.

A

A5

0

.

.

BUFFERS

a0

a5

x0

x63

b0

b0

4 K Bits64 X 64 CellsCELL ARRAY

SENSEAMPLIFIER

TRISTATE

COLUMN (Y) DECODER

s0 s0 s11 s11

11

R/W2

R/W1

CONTROL

R/W

INPUT

TRISTATE

DATA IN DATABUS

DATABUS

BU

FFERS

ROW(X

)DECODER

COLUMN ADDRESSBUFFERS

b63

CS

BITLINE PAIRSROW

ADDRESS

6A A. . .

y630

y

DATA OUT

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Faults found only in SRAM

Open-circuited pull-up deviceExcessive bit line coupling capacitance

Model

DRFCF

SRAM Fault Models

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DRAM Only Fault Models

Faults only in DRAMData retention fault (sleeping sickness)

Refresh line stuck-at fault

Bit-line voltage imbalance faultCoupling between word and bit line

Single-ended bit-line voltage shift

Precharge and decoder clock overlap

ModelDRF

SAF

PSFCF

PSF

AF

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Behavioral(black-box) Model -- State machine

modeling all memory content combinations --

Intractable Functional(gray-box) Model -- Used

Logic Gate Model -- Not used Inadequately

models transistors & capacitors

ElectricalModel -- Very expensive

GeometricalModel -- Layout ModelUsed with Inductive Fault Analysis

Fault Modeling

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Functional Model

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Simplified Functional Model

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Test Condition: For each cell, read a 0 and a 1.

< /0> (< /1>)A A

S0

S1

S0 S1

w0

State diagram of a good cell

w1w0

w1

w1

w0w1

w0

SA0 fault SA1 fault

Stuck-at Faults

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Cell fails to make a 0 1 or 1 0 transition.

Test Condition: Each cell must have an transition

and a transition, and be read each time before

making any further transitions.

,

transition fault

w0 S1S0w0 w1

w1

Transition Faults

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Coupling Fault (CF): Transition in bitj (aggressor)causes unwanted change in bit i (victim)

2-Coupling Fault: Involves 2 cells, special case ofk-Coupling Fault

Must restrict k cells for practicality

Inversion (CFin) and Idempotent (CFid) CouplingFaults -- special cases of 2-Coupling Faults

Bridging and State Coupling Faults involve any # ofcells

Dynamic Coupling Fault (CFdyn) -- Read or write onj forces i to 0 or 1

Coupling Faults

St t T iti Di f T

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w0/i

S00

S01

S11S10

w1/ j

w1/ i w1/ i

w1/ i, w0/ j

w0/ i, w0/ j

w1/i, w1/ j

w0/i, w1/ j

w0/ i

w1/ j

w0/ j

w0/ j

State Transition Diagram of Two

Good Cells, i andj

St t T iti Di f

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w0/ j

S00

S01

S11S10

w1/ i

w0/ jw0/ i, w0/ j w0/ i, w1/ j

w1/ i, w1/ jw1/ i, w0/ j

w0/ i w1/ i

w1/ j

w0/ i

w1/ j

State Transition Diagram for

CFin < ; >

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Aggressor cell or line j is in a given state y and that

forces victim cell or line i into state x

< 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >

w1/ i, w1/ j

00S

01S

11S

10S

w1/ iw1/ i

w0/ i

w1/ i, w0/ j

w0/ i, w0/ j w0/ j

w1/ j

w0/ i

w1/ j

w0/ j

State coupling fault (SCF)

w0/ i, w1/ j

State Coupling Faults (SCF)

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M0: { March element (w0)

}

for cell := 0 to n -

1 (or any other order) do

write 0 to A [cell];

M1: { March element (r0, w1)

}

for cell := 0 to n -

1 do

read A [cell]; { Expected value = 0}

write 1 to A [cell];

M2: { March element (r1, w0)

}

for cell := n

1 down to 0 do

read A [cell]; { Expected value = 1 }

write 0 to A [cell];

March Test Elements

March Tests

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AlgorithmMATS

MATS+

MATS++MARCH X

MARCH C-

MARCH A

MARCH Y

MARCH B

Description{ (w0); (r0, w1); (r1) }

{ (w0); (r0, w1); (r1, w0) }

{ (w0); (r0, w1); (r1, w0, r0) }{ (w0); (r0, w1); (r1, w0); (r0) }

{ (w0); (r0, w1); (r1, w0);

(r0, w1); (r1, w0); (r0) }{ (w0); (r0, w1, w0, w1); (r1, w0, w1);

(r1, w0, w1, w0); (r0, w1, w0) }

{ (w0); (r0, w1, r1); (r1, w0, r0); (r0) }{ (w0); (r0, w1, r1, w0, r0, w1);

(r1, w0, w1); (r1, w0, w1, w0);

(r0, w1, w0) }

March Tests

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Address decoding error assumptions:

Decoder does not become sequential

Same behavior during both read and write

Multiple ADFs

must be tested for

Decoders can have CMOS stuck-open faults

Cx

Cx

y

Multiple Cells

Fault 2

No Address to

xAccess Cell C Accessed with A

Fault 3

y

Accessed for Ax

Ay

Ax

No Cell

Ax

Fault 1

C

Fault 4

for Cell Cx

Ay

C

Multiple Addresses

x

Address Decoder Faults

Th

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A March test satisfying conditions 1 & 2 detects all

address decoder faults.

...

Means any # of read or write operations

Before condition 1, must have wx element

x can be 0 or 1, but must be consistent in test

Condition

1

2

March element

(rx, , w x )

(r x , , wx)

Theorem

M h T t F lt C

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Algorithm

MATS

MATS+

MATS++

MARCH X

MARCH C-

MARCH AMARCH Y

MARCH B

SAF

All

All

AllAll

All

AllAll

All

ADF

Some

All

AllAll

All

AllAll

All

TF

AllAll

All

AllAll

All

CFin

All

All

AllAll

All

CFid

All

CFdyn

All

SCF

All

March Test Fault Coverage

M h T t C l it

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March Test Complexity

AlgorithmMATS

MATS+

MATS++MARCH X

MARCH C-

MARCH A

MARCH YMARCH B

Complexity4n

5n

6n6n

10n

15n

8n17n

MATS+ Example

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MATS+: { M0: w0); M1: r0, w1); M2: r1, w0) }

(f) Bad machine

(a) Good machine

(d) Bad machine

after M2.

after M0.

(e) Bad machine

after M1.

(b) Good machine

0 0

0 000

000

1 1 11 1 11 1 1

0 0

0 000

000

0 0

0 000

000

1 1 11 1

1 1 10

0 0

0 000

000

after M0. after M1.(c) Good machine

after M2.

MATS+ Example Cell (2,1) SA0 Fault

MATS+ Example

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MATS+: { M0: w0); M1: r0, w1); M2: r1, w0) }

(a) Good machineafter M0.

(b) Good machineafter M1. after M2.

(d) Bad machine

after M0.

(e) Bad machine

after M1.

(f) Bad machine

0 0

0 00

000

1

0 0

0 000

0

00

1 1 1

1 1 11 1 1

0 0

0 000

0

00

0 0

0 00

000

11 1 1

1 11 1 11

(c) Good machine

after M2.

MATS+ Example Cell (2, 1) SA1 Fault

MATS+ Example

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Cell (2,1) is not addressable

Address (2,1) maps onto (3,1), and vice versa Cannot write (2,1), read (2,1) gives random data

MATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 }

(a) Good machineafter M0.

0 0

0 0

0000

0(b) Good machine

after M1.

1 1 11 1 1

1 1 1 (c) Good machineafter M2.

0 0

0 0

0000

0

(d) Bad machineafter M0.

0 0

0 00

0

00

X

(e) Bad machineafter M1 for cell (2, 1).

1 1 1

1X0 0

0 0(f) Bad machine

after M1.

1 1 1

1 11 1 1X

0 0

0 00

0

00

X

(g) Bad machineafter M2.

MATS+ Example Multiple AF: Addressed Cell Not Accessed;Data Written to Wrong Cell

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Memory BIST

LFSR and Inverse Pattern LFSR

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LFSR and Inverse Pattern LFSR

NOR gate forces LFSR into all-0 state

Get all 2n patterns

Normal LFSR: x) = x3 + x + 1

Inverse LFSR: x) = x

3+ x2

+ 1

Up / Down LFSR

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Up / Down LFSR

Preferred memory BIST pattern generator Satisfies March test conditions

X0 Q MUX

0

1

MUX0

1

MUX

0

1 Q Q

MUX

0

1

X1 X2

Up/Down

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Up / Down LFSR Pattern Sequences

Up Counting000100110111011101010001

Down Counting000001010101011111110100

Mutual Comparator

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Mutual Comparator

Test 4 or more memory arrays at same time:Apply same test commands & addresses to all 4

arrays at same time

Assess errors when one of the d i (responses)disagrees with the others

Mutual Comparator System

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Mutual Comparator System

Memory BIST with mutual comparator

Benefit: Need not have good machine response

stored or generated

SRAM BIST ith MISR

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SRAM BIST with MISR

Use MISR to compress memory outputs

Control aliasing by repeating test:

With different MISR feedback polynomial

With RAM test patterns in reverse order

March test:

{ (w Address); (r Address); (w Address);

(r Address); (r Address); (w Address);

(r Address); (r Address) }

Not proven to detect coupling or address decoder

faults

BIST System with MISR

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BIST System with MISR

LFSR and Inverse Pattern LFSR

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LFSR and Inverse Pattern LFSR

NOR gate forces LFSR into all-0 state

Get all 2n patterns

Normal LFSR: x) = x3 + x + 1

Inverse LFSR: x) = x3 + x

2+ 1

Up / Down LFSR

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Up / Down LFSR

Preferred memory BIST pattern generator Satisfies March test conditions

X0 Q MUX

0

1

MUX0

1

MUX

0

1 Q Q

MUX0

1

X1 X2

Up/Down

U / D LFSR P tt S

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Up / Down LFSR Pattern Sequences

Up Counting000100110111011101010001

Down Counting000001010101011111110100

Mutual Comparator

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Mutual Comparator

Test 4 or more memory arrays at same time:Apply same test commands & addresses to all 4

arrays at same time

Assess errors when one of the d i (responses)disagrees with the others

Mutual Comparator System

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Mutual Comparator System

Memory BIST with mutual comparator

Benefit: Need not have good machine response

stored or generated

SRAM BIST with MISR

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SRAM BIST with MISR

Use MISR to compress memory outputs

Control aliasing by repeating test:

With different MISR feedback polynomial With RAM test patterns in reverse order

March test:

{ (w Address); (r Address); (w Address);

(r Address); (r Address); (w Address);

(r Address); (r Address) }

Not proven to detect coupling or address decoder

faults

BIST System with MISR

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y

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Thank You