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Testing Mergeable Cores
Application of the DFT Disclosure
Document of the
IEEE P1500 Mergeable Core Task Force
Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh
Pradipta Ghosh, Scott Davidson, Peter Harrod
Universität Siegen, Agere Systems, Sun Microsystems,Brecis Communications, Sun Microsystems, ARM.
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Contents
n Introduction
n Economics - a good reason for this standard
n Key test cost parameters
n The structure of the DFT DisclosureDocument (DDD)
n Development methodology
n Summary
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1 Introduction
n IP based design is state of the art
n The economic pressure is increasing
n Test cost form a significant part of thedesign and manufacturing cost
n Test of IPs generates new problems
n Estimation of IP usage cost
u Purchasing cost
u Integration cost
u Test & DFT preparation cost
u Test execution cost
n The DDD describes the key test features!
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Designflown Classic
synthesis
n Test synthesisdescription forDFT integration
n DFT descriptionfor ATPG andfinal testassembly
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The IP selection process
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Current standard problems
n Merging of soft/firm cores with UDL or other coresmay introduce DFT rule violations
n Late design change in a core ->Redoing the DFT insertion process
n Merging of cores with different design styles, e.g.Latch <> FF based design
n …test
n We need a standard way of communicatingcore test features!
DFT Disclosure Document (DDD)
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2 Key issues of the DDD
n The DDD is not intended as a completeindependent test standard
n Description of key DFT Features
n May contain links to
u Other descriptive texts
u CTL files
u Vector files.
u ..
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DDD Contents summary
n General information
n Hierarchy support
u Hierarchical Ips
u Memories within IPs
n Structured contents
u Design
u Interface
u Digital Test
u Synthesis
u Memory
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DDD Contents summary
n Design
u Flipflops / Latches
u Bus properties
u Size
n Digital test
n General elements, e.g. test vector set
n Specific DFT elements
u Bist
u ATPG
u SCAN
u Iddq
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3 The structue of the DDD
n Top level information
n Component contents
n Design Information
n Interface
n Test Information
u Some details: Scan & iddq
n Clocks
n Memory
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Top level
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Component contents
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Design Information
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Interface
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Test Information
test_information
test_methodology
bist scanatpg fsim iddq
methodolgy
violation
program & scripts
test_vector_info
validated
fault typesfault_coverage
fault_information
clock_mode_ref
0.5 / Page 5 page 2, digital_component
memory
test_clock_modetest_vector_count
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Some details: Scan & iddq
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Clock Information
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Memory
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4 Development approach
n Written notes
n Graphical information model
n Dictionary
n Selection of the language:XML and XMLSchema
n Use of an effective tool: xmlspy
u Graphically supported input of entities andatributes
u Comments are supported
u Automatic generation of html documentation
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Main edit screen
File structure
Adding Element to SchemaCompo-nents
Details
Attributes
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Component definition
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Schema hierarchy
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Documentation example
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7 Future perspective
n Problems in estimating DFT costs for IPbased designs
n Overview of the DDD
n Examples of DDDs are available
n Web based tool for reading/writing DDDs isplanned
n Part of IEEE P 1500
n Is it worth the effort?We think: YES!
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The MCTF as part of P1500
n MCTF is part of P 1500
n Standard options
u Separate standard related to P 1500
u Appendix to P 15000
u Recommendation
u Integral part of P 1500F Formal documentation requirements
F P 1500 Time line
