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Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA.

Date post: 24-Dec-2015
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Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA
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Page 1: Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA.

Texas Instrument High Speed ADCs presentation summary

SALVATORE DANZECA

Page 2: Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA.

What High Speed means? High Speed means a sampling rate higher than 40 MSPS (for TI).

TI offer ADC from 40 MSPS up to 500 MSPs based on a pipelined architecture

16 bits resolution up to (370 MSPS) - 14 bit resolution (new design) (500 MSPS )

TI offer ADC from 1 GSPS up to 5 GSPS based on the folding architecture (interleaving of 2 ADCs)

The >= GSPS have a maximum resolution of 12 bits.

Page 3: Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA.

How it is possible to transfer the data?

Before there were the LVDS pairs.

Today the switch is versus a standardized communication link the JESD204B (up to 12 GSPS per lane). All the newest GSPS ADCs use the JESD204B.

Page 4: Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA.

Are they radiation hardened? The technology is 65nm. One of the fastest component qualified is a 6.4GSPS 12 bit ADCs up to 100krad (NOT YET PUBLISHED)

There are several other RAD-HARD components. The list is on the site at the link:

http://www.ti.com/lsds/ti/high-reliability/space/products.page

ADS5400-SP - 12-bit – 1GSPS

ADC12D1600QML-SP - 12-Bit, Single or Dual, 3200/1600/800 MSP

ADS5474-SP - 14 BIT 400 MSPS 

Page 5: Texas Instrument High Speed ADCs presentation summary SALVATORE DANZECA.

PSI - Status

1. Contract ready

2. Weeks available (considering the hours left from the 2014) : 13 weeks available

3. No information yet on the new facility. Follow up in these days.

4. First users: EN/STI and Prof Di Lillo SRAM memories.

5. Send me the planned request for this year.


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