Texas Instruments Hand- Free Kit Development …application-notes.digchip.com/001/1-2551.pdfinternal...

Texas Instruments Hands-Free KitDevelopment Platform

User’s Guide

Literature Number: SPRU703December 2003

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of salein accordance with TI’s standard warranty. Testing and other quality control techniques are used to theextent TI deems necessary to support this warranty. Except where mandated by governmentrequirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers areresponsible for their products and applications using TI components. To minimize the risks associatedwith customer products and applications, customers should provide adequate design and operatingsafeguards.

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Following are URLs where you can obtain information on other Texas Instruments products andapplication solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio

Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband

Interface interface.ti.com Digital Control www.ti.com/digitalcontrol

Logic logic.ti.com Military www.ti.com/military

Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork

Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video

Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright 2003, Texas Instruments Incorporated

iiiRead This First

Preface

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About This Manual

The Texas Instruments (TI) Hands-Free Kit (HFK) development platform isbased on the TI advanced C54x family of digital signal processors (DSPs).This platform was developed to enable the creation of products andapplications centered on the cellular after-market accessory and Bluetoothproduct market. The following document describes the TI HFK developmentplatform and its features.

Related Documentation From Texas Instruments

The following documents provide additional background information on someof the features and functions of the Hands-Free Kit development platform.

TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set(SPRU172)

Implementing a Software UART on the TMS320C54x with the McBSP andDMA (Literature Number: SPRA661)

DSP/BIOS Device Driver Developer’s Guide (SPRU616)

TMS320C54x Assembly Language Tools User’s Guide (SPRU102)

TMS320C54x DSP Programmer’s Guide (SPRU538)

TMS320C54x DSP/BIOS User’s Guide (SPRU326)

XDS560 Emulator Reference Guide (SPRU589)

Code Composer Studio Getting Started Guide (SPRU509)

TLV320AIC20 Data Manual (SLAS363)

TLV320AIC24 Data Manual (SLAS366).

The documentation listed above is available for download fromhttp://www.ti.com.

Trademarks

iv

Trademarks

Trademarks are the property of their respective owners.

Bluetopia is a trademark of Stonestreet One, Inc.

Bluetooth is a trademark of Bluetooth Special Interest Group (SIG).

Contents

v

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1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 DSP Subsystem 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 DSP GPIO Functions 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 DSP Clocking 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Pushbutton Interface 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 LED Interface 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 DSP Serial Ports 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.1 Soft UART 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.2 Debug Port 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.8 DSP Configuration 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 DSP JTAG Debugger 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 FLASH Memory 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.10.1 Not Ready 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11 SRAM Memory 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11.1 SRAM Timing 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Audio Codec 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Codec Clocking 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Microphone Inputs 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Line Level Outputs 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Speaker Output (Optional) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 FM Output 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Bluetooth Interface 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Bluetooth Connector 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Bluetooth Physical Requirements 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 PLD 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Logic Functions 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 Address Decoding 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 I/O Space Registers 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

vi

5.3 PLD Programming Interface 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 In-Circuit Programming via DSP 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Power Supply 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Overview 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Load Dump 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Power Input 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A PLD Equations A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Schematics B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Bill of Materials C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

viiContents

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1−1 HFK Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 HFK DSP Subsystem Components 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 C5407 HFK Program Memory Map 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 C5416 HFK Program Memory Map 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5 C5407 HFK SRAM Memory Map (32KW Page Option) 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6 C5407 HFK SRAM Memory Map (16KW Page Option) 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7 C5416 HFK SRAM Memory Map (32KW Page Option) 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 HFK Codec Subsystem 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 2.5mm Audio Input Connector 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 HFK FM Transmitter 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 HFK Bluetooth Interface (Physical) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1 I/O Space Registers 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2 cPLD JTAG Connections 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1 HFK Power Supply 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

viii

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1−1 TI TMS320C54x Derivative Feature Set 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 HFK Programmable Logic Device JTAG Pin Mapping 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 HFK Pushbutton-DSP Mapping 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 DSP Serial Port Usage 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5 HFK Resistor Stuffing Options 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6 Synchronous Serial Port Options 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7 HFK DSP Configuration Resistors 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 MICBIAS Options 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 Line Level Audio Output Connector 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 HFK Bluetooth Interfaces 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 Bluetooth Connector 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C−1 HFK Development System Bill of Materials C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

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This chapter provides an overview of the Hands-Free Development Kit (HFK)platform and the subsystems required for its implementation.

Topic Page

1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 DSP Subsystem 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 DSP GPIO Functions 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 DSP Clocking 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Pushbutton Interface 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 LED Interface 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 DSP Serial Ports 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.8 DSP Configuration 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.9 DSP JTAG Debugger 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.10 FLASH Memory 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11 SRAM Memory 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

Overview

1-2

1.1 Overview

The Hands-Free Kit (HFK) is designed around the TI TMS320C54x family ofDSPs. Specifically, the C5404, C5407, C5409, C5410, and C5416 processorsare supported, with minor limitations/variances across implementations. TheHFK design was originally targeted at the TMS320C5407 based on theamount of internal memory it provided, plus the integration of a hardwareuniversal asynchronous receiver/transmitter (UART). Other DSPimplementations are supported without this feature, however provisions aremade to include key features relative to the HFK market.

The HFK consists primarily of six discrete blocks, which are:

� digital signal processor

� audio codec

� RF (FM) transmitter

� programmable logic device (PLD)

� Bluetooth transceiver

� automotive class power supply

Depending on the system requirements, one or more of these subsystems inFigure 1−1 may be omitted. The following sections describe each subsystemin detail.

Overview

1-3Introduction

Figure 1−1. HFK Block Diagram

C5407 (1)

FLASH(128KB−

4MB)

SRAM(128−

512KB)

cPLD(4)

AIC2x(2)

BlueTooth(TI island

module) (5)

FMoutputto radio

Dual-channelcodec

Voiceprocessing

DSP

Modeminterface

BlueToothto cell phone

Microphonearray

Memoryinterface

UART McBSP

GPIO(buttons,LEDs)

TI HFK Reference Design

TI Silicon

Other Si content

TPS77733TPS76918TPS76915TL5001 (6)

Powermanagement

(3)

TPS71501

DSP Subsystem

1-4

1.2 DSP Subsystem

The DSP subsection includes a C54x-based DSP device, plus externalmemory consisting of SRAM and FLASH. The memory component of thissubsystem may not be required in production-level systems, however, fordevelopment purposes it is included in this design. Both memory elements arephysically placed on the backside of the HFK development platform’s printedcircuit board (PCB) to further illustrate this issue.

The HFK development platform ships by default with an installedTMS320C5407 device. This device includes 256 KB internal ROM, 80 KBinternal SRAM, a 16-bit memory interface, 8-bit HPI (reconfigurable as GPIO),three multichannel buffered serial ports (McBSP), and an integrated universalasynchronous receiver/transmitter (UART). Other C54x-based DSP devicesare supported by the HFK platform, including the C5404, C5409, C5410, andC5416, in the 144-pin TQFP package (TI package designator PGE). Table 1−1outlines the key features of each device.

Table 1−1. TI TMS320C54x Derivative Feature Set

DeviceMIPS(MHz)

RAM(words)

ROM(words) Timers UART

BufferedSerial

5404 120 16K 64K 2 Hardware 3 McBSP

5407 120 40K 128K 2 Hardware 3 McBSP

5409 80 32K 16K 1 Soft 3 McBSP

5410 100 64K 16K 1 Soft 3 McBSP

5410A-120 120 64K 16K 1 Soft 3 McBSP

5410A-160 160 64K 16K 1 Soft 3 McBSP

5416-120 120 128K 16K 1 Soft 3 McBSP

5416-160 160 128K 16K 1 Soft 3 McBSP

DSP GPIO Functions

1-5Introduction

1.3 DSP GPIO Functions

In the interest of supporting as many C54x devices as reasonable, severallimitations are put into place. First, all general-purpose input/output (GPIO)functions required for HFK operation have been relegated to theprogrammable logic device (PLD), as discussed in Chapter 5. The reason isthat not all C54x devices supported include enough GPIO functionality for theHFK design. Hence, the GPIO function is provided via the PLD, such that allimplementations access such functions in a consistent manner. The oneexception to this is that DSP processors that do allow the HPI to be utilized asGPIO pins will support in-circuit programming of the PLD via the DSP device.This is accomplished by tying the PLD JTAG pins to several of the HPI pins.By doing this, systems which utilize the PLD in production designs caneliminate the cost of programming the PLD by programming the JEDEC binaryfile into the C54x ROM, and programming the PLD during boot up. The PLDJTAG pin mapping is shown in Table 1−2.

Table 1−2. HFK Programmable Logic Device JTAG Pin Mapping

JTAG Signal Name C54x Pin Name C54x Pin Number (QFP144)

TCK (test clock) HD4 120

TMS (test mode select) HD2 81

TDI (test data in to cPLD) HD0 56

TDO (test data out from cPLD) HD6 135

Note that all DSP HPI pins, on a device that supports conversion to GPIOs, willpower up in the input state, and thus be pulled to a logic high level via internalpull-up resistors. To utilize the in-circuit PLD programming feature, the usermust write code to a) convert the HPI pins to GPIO, b) drive the TMS, TCK,and TDI pins of the PLD as output, and accept TDO as an input, and c)appropriately toggle these pins to correctly reset and program the PLD device.The HPIENA input of the C54x device is pulled low on the HFK design tosupport this feature. If this feature is not used, a pull-down resistor (R45) isincluded on the TCK to prevent clocking of the cPLD test logic.

DSP Clocking

1-6

1.4 DSP Clocking

The DSP subsystem is clocked from an external oscillator running at11.52 MHz. This frequency is internally (within the C54x) multiplied andphased-locked to clock the DSP at a 115.2 MHz rate. This rate was chosenbecause it results in an integer divide-down to several standard serial baudrates on the hardware UART of the C5407. This results in a design thatrequires just one external crystal.

1.5 Pushbutton Interface

The HFK development platform includes three user-interface buttons. Eachpushbutton is located on the right-hand side of the PCB, and is instanced viaa momentary-type pushbutton. Each pushbutton is tied to a DSP interrupt, andthus may be utilized either via an interrupt service routine or via polling. Ineither case, no hardware debouncing of the pushbutton inputs is provided. Thedebounce function must be provided via software running on the DSP. Thisimplementation decision was made for the purposes of reducing cost of anHFK design.

Table 1−3 defines the pushbutton-to-interrupt mapping of the HFKdevelopment platform.

Table 1−3. HFK Pushbutton-DSP Mapping

HFK Pushbutton DSP InterruptDSP Host Data Pin

(GPIO)

SW2 /INT3 HD1

SW3 /INT1 HD5

SW4 /INT2 HD3

Note that in addition to interrupting the DSP, general purpose I/O on the DSPis used to allow the developer to ascertain the amount of time that a particularpushbutton is depressed. This is useful for implementing features such asvolume controls, as well as for multiplexing multiple commands onto a singlebutton.

LED Interface

1-7Introduction

1.6 LED Interface

In addition to the user inputs (pushbuttons), the HFK development platformincludes three light-emitting diodes (LEDs), two of which may be controlled viathe DSP. The third LED, D3, is illuminated whenever power is being suppliedto the board. The other LEDs, D1 and D4, are controlled by the DSP throughan I/O space register, described in Chapter 5.

Figure 1−2. HFK DSP Subsystem Components

Top View Bottom View

push

butto

ns

USER_LED1USER_LED0

FLA

SH

SR

AM

DSP

JTAG connector

DSP Serial Ports

1-8

1.7 DSP Serial Ports

The C54x subsystem includes three serial port interfaces, referenced with0-based indexing. In the case of the C5407, all three ports are used. Table 1−4outlines the usage of each serial port using the various DSP devices supportedby the platform.

Table 1−4. DSP Serial Port Usage

DSP McBSP0 McBSP1 McBSP2 HW UART

C5404 Soft-UART debugport

Bluetooth audio datainterface

Audio data, to/fromon-board codec

Bluetooth controlinterface

C5407 Soft-UART debugport



Bluetooth controlinterface

C5409 Soft-UART Bluetoothcontrol interface



N/A




N/A




N/A

1.7.1 Soft UART

The ‘soft-UART’ functionality mentioned above refers to the usage of asynchronous serial port as a standard UART. As the name implies, such usagerequires software running on the DSP to emulate a standard UART register setand functionality. The software UART functionality is additionally supported viaseries resistors that provide/prohibit the correct/incorrect connections withinthe HFK design. The necessary connections are as shown in Table 1−5.

Table 1−5. HFK Resistor Stuffing Options

DSP Install Do Not Install Function

C5404 R42-R44, R62 R100-R104 Default (soft-UART debug port onMcBSP0)

C5407 R42-R44, R62 R100-R104 Default (soft-UART debug port onMcBSP0)

C5409 R100-R104 R42-R44 Soft-UART on McBSP2



DSP Serial Ports

1-9Introduction

For more information on the software UART functionality, please refer to TIapplication report, Implementing a Software UART on the TMS320C54x withthe McBSP and DMA (SPRA661).

1.7.2 Debug Port

Because of limited serial port availability, not all of the supported DSPs willsupport a debug UART function. The debug UART is provided in the baselinesystem as a means to obtain real-time debug information and possiblycontrol/configuration for various elements of the HFK software system. Thisinterface connects through an 8-pin header on the HFK board (JP3). Aseparate paddle board may be used to convert the TTL level TX and RXsignals of the UART to standard RS-232 levels. The JP3 header also includesan I2C (see section 5.2) interface which, when coupled with the debug portused in a more conventional, synchronous mode, provides a convenientconnection to a MOST or CAN type automotive bus controller. Such aconnection can be facilitatied as shown in Table 1−6. For other DSP devices,the debug UART function is not included, as the serial port supporting thisfunction is required for the Bluetooth interface. In systems where Bluetooth isnot required, this serial port could be reclaimed for debug purposes.

Table 1−6. Synchronous Serial Port Option

Install Do Not Install Function

R62 R63 − R65 Default (soft-UART for debug on McBSP0)

R63 − R65 R62 Synchronous serial port on McBSP0 (available at JP3interface)

DSP Configuration

1-10

1.8 DSP Configuration

The DSP subsystem includes various pullup/pulldown resistors required forconfiguration and normal operation. Table 1−7 outlines the default HFKconfiguration.

Table 1−7. HFK DSP Configuration Resistors

Configuration Input Default State To override… Function

C54x MP/MC Low (R8 pulldown) Install R6, remove R8 Low = microcontrollermode, high =microprocessor mode

AIC2x master/slavemode

High (AIC2x is master) Install R4, remove R1 Low = C54x drivesclock/frame sync, High =AIC2x drives clock/framesync

1.9 DSP JTAG Debugger

The DSP subsystem also includes a standard 2x7 TI JTAG emulationconnector (JP2). This is to provide a connection to the XDS family of emulationpods (XDS510, XDS510PP, XDS560) and development using the powerfulsuite of TI Code Composer Studio tools. For more information on this toolset,please refer to http://www.ti.com.

FLASH Memory

1-11Introduction

1.10 FLASH Memory

The FLASH memory serves as non-volatile storage for code and data acrosspower cycle events. In a production design, many systems may in fact notrequire this memory element, because the internal ROM of the C5407 or otherdevice may be sufficient. FLASH memory for which the AMD AM29LVxxxfamily of devices was selected, is included as a development platform. Thestandard HFK platform ships with an AM29LV400BT device, resulting in512KB of memory space. The HFK layout supports up to a 32Mb device(AM29LV032B), or 4MB of FLASH memory. The FLASH memory is mappedinto DSP program space (only). There may be a desire for a minimal amountof non-volatile data storage in an HFK system. To address this, the user mayutilize the FLASH memory bank using program memory store operations [seethe TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set(SPRU172)], or via a serial EEPROM which, while not implemented on theHFK development system, is addressed in Chapter 5. The FLASH memorybank is accessible at: 0x000000 – 0x3FFFFF. A nominal access time of 90nsis required for access to the FLASH bank.

The C5407 HFK Program memory map is as shown in Figure 1−3.

FLASH Memory

1-12

Figure 1−3. C5407 HFK Program Memory Map

Externalmemory(aliased)

Externalmemory

InternalDARAM

OVLY = 1

Externalmemory

24K words

32K words

0x0000

0x1000

0x2000

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xE000

0xF000

0x000000

0x008000

0x010000

0x018000

0x020000

0x1E8000

0x1F0000

0x1F8000

DSP memory map Flash

32K words

32K words

32K words

32K words

32K words

32K words

32K words

0x00000

0x08000

0x10000

0x18000

0x20000

0x68000

0x70000

0x78000

32K words

32K words

32K words

32K words

32K words

SRAM

Flash: extended program pages 0−63SRAM: extended program pages 64−79

Unused†

† Unused section in first 32K word section of Flash due to OVLY

FLASH Memory

1-13Introduction

The C5416 HFK Program memory map is as shown in Figure 1−4.

Figure 1−4. C5416 HFK Program Memory Map

Externalmemory(aliased)

Externalmemory

InternalDARAM

OVLY = 1

Externalmemory

32K words

0x0000

0x1000

0x2000

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xE000

0xF000

0x000000

0x008000

0x010000

0x018000

0x020000

0x1E8000

0x1F0000

0x1F8000

DSP memory map Flash

32K words

32K words

32K words

32K words

32K words

32K words

32K words

0x00000

0x08000

0x10000

0x18000

0x20000

0x68000

0x70000

0x78000

32K words

32K words

32K words

32K words

32K words

SRAM

Flash: extended program pages 0−63SRAM: extended program pages 64−79

32K words

FLASH Memory

1-14

1.10.1 Not Ready

The AMD FLASH device supports a ‘not-ready’ condition. This is most criticalduring programming cycles, such that the DSP does not access the memoryarray until it is correctly written. To prevent such accesses, the busy signal fromthe FLASH device is connected to the C54x READY input. This signal is pulledup via resistor R15, as the FLASH device implements an open-drain styleoutput.

SRAM Memory

1-15Introduction

1.11 SRAM Memory

The SRAM bank is based on the IDT20xx family, athough CypressSemiconductor also manufactures pin-compatible devices in their CY7C20xxfamily. In the baseline HFK, 256KB of SRAM memory is supported; however,some early HFK systems were used for development purposes with a smallermemory bank. The user should check the HFK to validate the amount ofmemory present in the SRAM bank. Similar to the FLASH memory bank, inmany HFK systems the SRAM bank may not be required, as all code/datanecessary for the application may be resident internal to the C54x device. TheHFK design natively allows support for up to 512KB of SRAM memory. Thisamount can possibly be extended to 1MB, should manufacturers choose toadd one additional address bit to the unused pin in the chosen device package.At the time of writing, a 1MB device in the x16 configuration was not availablefrom any manufacturer in the chosen package.

The SRAM bank was intended primarily to serve as program space, fromwhich the DSP would execute, after having copied program code from theFLASH memory bank (see section 1.10) to this bank during boot-up. Sincelarge data structures may be present in these systems for the purposes ofspeech recognition and/or other algorithms, the SRAM bank is additionallymapped into DSP data space. Due to a limited 64KW data space size limitationof the C54x family, additional pages of data memory within this SRAM spaceare supported through an external PLD, as described in Chapter 5. The PLDprovides two options: utilizing 16KW or 32KW page sizes within the SRAM.

Figure 1−5 and Figure 1−6 define the SRAM as viewed from the C5407 DSPdevice.

SRAM Memory

1-16

Figure 1−5. C5407 HFK SRAM Memory Map (32KW Page Option)

Internal

DARAM

External

SRAM

External

SRAM

DROM = 0

Internal

DARAM

External

SRAM

Internal

ROM

DROM = 1

24K words

Unused

24K words

Unused

24K words

Unused

24K words

Unused

24K words

Unused

24K words

Unused

24K words

Unused

0x0000

0x1000

0x2000

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xE000

0xF000

0x00000

0x08000

0x10000

0x18000

0x20000

0x68000

0x70000

0x78000

DSP memory map SRAM

SRAM Memory

1-17Introduction


Internal

DARAM

External

SRAM

(aliased)

External

SRAM

DROM = 0

Internal

DARAM

External

SRAM

(aliased)

Internal

ROM

DROM = 1

16K words0x0000

0x1000

0x2000

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xE000

0xF000

0x00000

0x08000

0x10000

0x18000

0x20000

0x68000

0x70000

0x78000

16K words

16K words

16K words

16K words

16K words

16K words

16K words

16K words

16K words

16K words

16K words

16K words

16K words

0x04000

0x0C000

0x14000

0x1C000

0x6C000

0x74000

0x7C000

DSP memory map SRAM

SRAM Memory

1-18

Figure 1−7 defines the SRAM as viewed from the C5416 DSP device.


Internal

DARAM

External

SRAM

DROM = 0

Internal

DARAM

Internal

DARAM

DROM = 1

32K words

0x0000

0x1000

0x2000

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xE000

0xF000

0x00000

0x08000

0x10000

0x18000

0x20000

0x68000

0x70000

0x78000

DSP memory map SRAM

32K words

32K words

32K words

32K words

32K words

32K words

SRAM Memory

1-19Introduction

1.11.1 SRAM Timing

All accesses to SRAM require two DSP clock cycles to complete. This is afunction primarily of the SRAM device speed (10ns access time in the baselineHFK platform). Changes to the DSP clock frequency and/or SRAM speedgrades may alter this timing.

1-20

2-1

��

This chapter discusses the TLC320AIC2x family codec, which is the audiointerface for the HFK development platform. As a codec, the AIC2x familyprovides both A/D and D/A functions for two channels of audio. The interfaceto the AIC2x is provided via one of the DSP serial ports, McBSP2.

Topic Page

2.1 Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Codec Clocking 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Microphone Inputs 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Line Level Outputs 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Speaker Output (Optional) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2

Overview

2-2

2.1 Overview

In this design, the audio interface for the HFK development platform isprovided via a TI TLC320AIC2x family codec. As a default, an AIC24 ischosen. This device is a dual-channel codec with up to a 26kHz samplingfrequency, and includes stereo microphone pre-amplifier circuits. Otherdevices in this AIC family include the AIC23 and AIC20. The HFK developmentplatform will support any of these devices; however, is chiefly targeted aroundthe AIC24 and AIC20, where the latter option provides an integrated amplifiedspeaker output for systems which require this feature.

As a codec, the AIC2x family provides both A/D and D/A functions for twochannels of audio. The interface to the AIC2x is provided via one of the DSPserial ports, McBSP2. Control of the codec can be accomplished in one of twoways − either embedded into the serial data stream or via a separate inter-IC,or I2C bus interface. Because the C54x devices do not natively include I2C asan interface, this interface is provided via the PLD (see Chapter 5). Thisinterface could be moved to C54x GPIO pins on devices that support thatfeature. The driver software provided by TI for the HFK development platformperforms control via the serial interface, thus simplifying the HW design.

Figure 2−1 identifies the key components of the codec subsystem.

Overview

2-3Audio Codec

Figure 2−1. HFK Codec Subsystem

Top View

2.5mm MIC/line in

on-boardMICs

3.5mm lineout (stereo)

SPKR−

SPKR+

AIC2Xcodec

Codec Clocking

2-4

2.2 Codec Clocking

The AIC2x is clocked by dividing down the DSP CLKOUT signal by 4, usingtwo discrete D-type flip-flops: component U16 and U10. The resulting clock isthen input to the MCLK pin of the AIC2x codec, where it is internally dividedand phase-locked using integrated DLLs. The result is an 8kHz audio sampleclock. The AIC2x is configured in master mode, that is, it drives the transmitand receive clocks back to the DSP for the audio interface. The DSP, in turn,provides frame sync outputs back to the AIC2x device to define the audiosample sequencing and alignment boundaries. The interface supports a 15-bitaudio sample, where the least significant bit, (i.e., a 16th bit), is used to selectbetween control and data on the interface. The HFK also supports the AIC2x16-bit mode once programming of the codec is complete. For more informationon these options, please refer to the TLV320AIC24 Data Manual (SLAS366).

2.3 Microphone Inputs

The AIC2x is connected to two on-board electret microphones. Thesemicrophones, M1 and M2, are physically positioned 0.5 inches apart, so thatdirectional speech and advanced signal processing algorithms can use thisparameter intelligently to filter out near-end noise. In many cases, the spacingof said microphones, in addition to their sensitivity (approximately –41dB),may not be sufficient. Hence, a 2.5-mm jack is provided which, whenconnected, will disconnect the on-board microphones from the codec andallow an external microphone or pair of microphones (mic array) to beconnected (see Figure 2−2). The 2.5-mm plug (JP4) is a 4-position plug withthe following pinout.

Figure 2−2. 2.5-mm Audio Input Connector

GND AIC2x A/D input 2

AIC2x A/D input 3

MIC bias(1.35/2.35 V,

selectable via AIC2xOR 8.0 V via stuffing options)

Microphone Inputs

2-5Audio Codec

Note that the AIC2x microphone bias is provided to the connector such thatmicrophones requiring pre-amplification may be used externally. Thishowever, is not the default configuration. By default the left-most collar inFigure 2−2 is left unconnected, allowing a more typical 3-conductor cable oradapter assembly to be used, wherein the GND collar is extended to includethe collar designated for biasing. This disconnection is achieved by no-loadingresistor R69. If a true 4-conductor cable is used and a biasing signal isrequired, R69 should be installed, and L15/R55 installed as appropriate.

In addition to the AIC2x microphone bias, the user may additionally select an8V bias, as is common to many automotive-class microphones. Themicrophone bias selection can be controlled as follows:

Table 2−1. MICBIAS Options

MICBIAS Level Install Do Not Install Suggested Components

1.35V/2.35V(AIC2x controlled)

R55 R58, R59, L15 R56, R57 = 0 Ohms(see below)

8V (fixed) L15 (R58, R59 optional) R55 R55, R56 = 1K Ohms(see below)

Note that when the 8V rail is selected as the microphone bias, the AIC2xMICBIAS output is disconnected from the JP4 port.

Regardless of the MICBIAS settings, the AIC2x inputs are designed foroperation from 0-2V, and are AC-coupled on the HFK platform. Attenuationresistors R56 and R57 are provided to aid in meeting this requirement. As adefault, these resistors are 0 Ohms for use with the on-board electretmicrophones. When using an 8v microphone, it is suggested that you replaceR56 and R57 with a 1K resistor. Further attenuation can be achieved by stallingresistors R58 and R59, though it may not be required in all circumstances. Ifthese components are installed, the user should take care to ensure that thelevel seen at the AIC2x inputs is not attenuated so much as to not bedetectable. For reference, the single-ended input impedance of the AIC2xinputs is approximately 18K Ohms.

Standard audio line-level outputs may be used to drive the JP4 inputs with theHFK in the default configuration.

Line Level Outputs

2-6

2.4 Line Level Outputs

Stereo outputs are provided on the design at near-line level. That is, theoutputs are designed to drive a 600 Ohm load with a peak voltage ofapproximately 700mV. The line-level outputs are driven from the AIC2x codecwith a DC offset of approximately 1.35V. These outputs are then AC-coupledvia 0.1 µF cap (components RC1, RC2). Both outputs are available on port J4,a 3.5mm (1/8 inch) jack, wired in the standard L/R configuration. Table 2−2defines the output channel mapping for the audio subsection.

Table 2−2. Line Level Audio Output Connector

J4.Pin AIC2x Output Channel

Tip OUT2 Left

Collar OUT3 Right

Shield GND N/A

2.5 Speaker Output (Optional)

Use of an AIC20 codec (not default) enables the developer to drive a speakeroutput. The AIC20 includes an integrated speaker driver capable of driving a16 Ohm load. To accommodate such an interface, the HFK design includes a4-pin header, JP5, which is suitable for connection to a speaker. The headeris configured for use of pins 1 and 4. Note that pins 2 and 3 are claimed for useas JTAG pins for connection to an external programmer for the on-board PLD.If a speaker is connected to this header, take care that you do not drive theJTAG pins accidentally (see Chapter 5). While the speaker output is physicallyseparate from the aforementioned line level outputs, the AIC2x is a 2-channelDAC, and thus if the speaker output is used, the line level outputs will not beavailable. This is not considered a major issue because if the speaker outputis desired, then line level outputs likely are not.

For more information regarding the operation and programming of the AIC2xdevice, refer to the TLV320AIC20 Data Manual (SLAS363) and theTLV320AIC24 Data Manual (SLAS366).

3-1

� ��

This chapter provides information about one of the simpler elements of theHFK design, the FM transmitter.

Topic Page

3.1 Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3

Overview

3-2

3.1 Overview

A final output of the AIC2x codec is provided to the FM transmitter section ofthe design. It should be noted that while this output (OUT1) is separate fromthe aforementioned line level outputs, the AIC2x is only a 2-channel codec,and thus use of the FM output will shut off one of the line level outputs. Thisis not considered a major issue because if the FM output is desired, then linelevel outputs likely are not.

For more information regarding the operation and programming of the AIC2xdevice, refer to the TLV320AIC20 Data Manual (SLAS363) and theTLV320AIC24 Data Manual (SLAS366).

The FM transmitter section of the HFK design is one of the simpler elements.This subsection is based on an extremely simplified oscillator circuit. A parallelair coil inductor (L6) and capacitor (C52) set the base carrier frequency atapproximately 90MHz. A variable capacitor (C64) is also included in parallelwhich allows adjustment of the carrier by about ±15MHz, thus covering mostof the FCC band allocated to stations. Component C64 may be changed toaccommodate a larger swing if desired, which will result in covering even moreof the band of stations that can be transmitted on. Frequency modulation isachieved by switching in a small capacitor across the collector-emitter of atransistor, as a function of the input voltage at the transistor base, which isdriven from the AIC2x codec (see Chapter 2).

The modulator transistor, Q3,is biased in the linear range when idle. In orderto avoid saturating the transistor, the input signal from the codecmust belimited to a small dynamic range, or approximatley 250mV peak-peak. Failureto do this will hav two ill side effects; distortion of the signal at the receiver, andinstability in the FM output frequency. this limited range is most easily achievedby applying attenuation of the codec DAC output through control register 5B,the D/A PGA Gain register, as described in the aforementioned TI damamanuals, SLAS363 (AIC20) and SLAS366 (AIC24). Approximately −6dB gainshould be sufficient to achieve the desired attenuation for the FM circuit. Notethat this attenuation is not required for the aforementioned line level or optionalspeaker outputs.

A switch (SW1) is provided to turn the FM transmitter off in the event it is notneeded. For reasonably short distances, say within a car, the FM transmittermay be operated without an antenna. A test point (A1) is provided forconnection to an external antenna if desired, however, it should be noted thatno buffer stage exists at the transmitter output. Thus the user should ensuretht the antenna connection does not alter the FM transmitter characteristics.Figure 3−1 identifies the key components of the FM transmitter.

Overview

3-3FM Output

Figure 3−1. HFK FM Transmitter

Bottom ViewTop View

air coil

tuning cap

switch

antenna(optional)

3-4

4-1

��

This chapter describes the Bluetooth subsystems that are able to connect tothe HFK development platform.

Topic Page

4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Bluetooth Connector 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Bluetooth Physical Requirements 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4

Overview

4-2

4.1 Overview

The HFK development platform is designed to accommodate connection to aBluetooth interface. This interface would provide connection to a cellulartelephone in systems that do not use a wired connection. The Bluetoothsubsystem may vary widely across implementations; however, the interfacefrom the DSP to the subsystem is fairly standard. It includes two electricalconnections: a PC-type UART connection for control, and a synchronousserial connection for the real-time transmit and receive audio data. Dependingon the DSP used in the system, the following interfaces are used to connectto the Bluetooth subsystem (Table 4−1).

Table 4−1. HFK Bluetooth Interfaces

DSP Bluetooth Streaming Audio Bluetooth Control

C5404/C5407 McBSP1 Integrated UART

C5409/C5410/C5416 McBSP1 Soft UART on McBSP0

For more details of the soft-UART function, refer to the application report,Implementing a Software UART on the TMS320C54x with the McBSP andDMA (SPRA661).

Bluetooth Connector

4-3Bluetooth Interface

4.2 Bluetooth Connector

The Bluetooth interface is provided via a 1x14 0.100 inch header (JP1). Thisheader includes two separate power rails, 3.3V and 1.8V, ground connection,and the UART and synchronous serial port interfaces. Table 4−2 defines theBluetooth connector, along with allocated current capacities for each of thesupply rails.

Table 4−2. Bluetooth Connector

JP1 Pin Number Signal Name Function/Comments

1 VDD3 3.3V supply, 500mA

2 AUD_CLK Synch. serial port clock

3 AUD_IN Synch. serial data to Bluetooth

4 AUD_FSYNC Synch. serial port frame sync

5 AUD_OUT Synch. serial data from Bluetooth

6 GND Supply return (same as pin 13)

7 RX_HCI Control UART receive data (FROMBluetooth controller)

8 CTS_HCI Control UART Clear-to-Send (notimplemented on HFK developmentplatform)

9 TX_HCI Control UART transmit data (to Bluetoothcontroller)

10 RTS_HCI Control UART Ready-to-Send (notimplemented on HFK developmentplatform)

11 BTINT Active-low interrupt to DSP (/INT0)

12 BTRESET Active low reset signal (SW controlledfrom DSP/cPLD)

13 GND Supply return (same as pin 6)

14 VDD2 1.8V supply, 100mA

Note: All control UART signals are standard LVTTL-type drivers. No signal conditioning (i.e.,RS-232 drivers) are implemented on the HFK development platform.

Bluetooth Physical Requirements

4-4

4.3 Bluetooth Physical Requirements

Bluetooth daughtercards may be designed for the HFK platform. To ensureproper connection, the designer should reference both the pinout of and thephysical layout of the HFK as shown in Figure 4−1. The expectedimplementation is to support Bluetooth daughtercards with at least threepoints of contact, namely the 1x14 header, and two tooling holes as shownbelow. Care should be taken not to install a Bluetooth card over the top of theJTAG connector (JP2) as this interface will likely be needed to debug ordevelop code for the Bluetooth interface. Also, you must avoid covering thepushbutton and LEDs of the HFK, as these provide the user interface for thedesign.

Figure 4−1. HFK Bluetooth Interface (Physical)

1.650″

3.70

0″

0.200″ 0.200″

0.20

0″

0.70

0″1.

300″

0.90

3″0.

100″

5-1

��

This chapter discusses the functions of the programmable logic device (PLD)as well as alternate implementation options for developers who do not wish touse a PLD in their design.

Topic Page

5.1 Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Logic Functions 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 PLD Programming Interface 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 5

Overview

5-2

5.1 Overview

The final component of the HFK development platform is a programmablelogic device, or PLD (also cPLD). A PLD was chosen over discrete logicprimarily for the purposes of board size, and the functionality implemented forthe purposes of a development platform. Many HFK developers and designerswill choose to use discrete logic, and likely implement only a subset of thefunctions of the PLD of the development kit. The complete logic equations forthe PLD are included in Appendix A. The following sections outline thefunctions of the PLD sections at a high level, and also suggest alternateimplementation options for developers who do not wish to use a PLD in theirdesign.

Logic Functions

5-3PLD

5.2 Logic Functions

The PLD provides several key interfaces, which are as follows:

� Chip select generation for the on-board FLASH and SRAM spaces

� Inter-IC, or IIC (also I2C) control bus

� User LED control

� Audio codec and Bluetooth reset (DSP controllable)

� Mapping of external SRAM into DSP data space

Depending on the subset of functions required, all of the above functions canbe implemented using GPIO functionality. Due to the limited number ofcommon GPIO pins across the many DSPs that the HFK platform supports,a PLD was the chosen implementation.

5.2.1 Address Decoding

The first and most critical function of the PLD is to provide address decodingto select between the FLASH and SRAM devices. This decoding is based onthe most significant address bit of the DSP device, A22. A22 high selects theSRAM; A22 low selects the FLASH memory.

5.2.2 I/O Space Registers

The PLD provides 3 discrete user-addressable registers. All three registersare mapped into DSP I/O space, and are defined in Figure 5−1.

Figure 5−1. I/O Space Registers

15 13 12 11 10 9 8 7 0

WIN16n32

SDAOE

SCLOE

SDA SCL

15 12 11 10 9 8 7 0

LED1(D1)

LED0(D4)

BTRST CDCRST

15 13 12 11 10 9 8 7 0

A19 A18 A17 A16 A14

Notes: 1) Grayed out bits are undefined; writing to them will have no effect; reading them will return undefined data. All definedbits are read/write, and reset to a value of 0.

2) All registers are implemented between data bits D12−D8. This was a choice made to simplify routing of the PCB;other implementations are valid. It is recommended that the HFK user utilize macros when accessing these bits topromote portability to other HFK implementations.

0x1000I2CREG

0x2000MISCREG

0x3000XDATAREG

Logic Functions

5-4

5.2.2.1 WIN16n32

This bit is set to 1 to select 16KW data memory windows in external memory;0 to select 32KW windows. Setting this bit to 1 will engage the use of bit 8 inthe XDATA_REG as fifth most-significant address bit to the external SRAM fordata space accesses only.

5.2.2.2 SDA/SCL_OE

These bits control the output enable function of the I2C bus. When set to 1, theappropriate signal is driven with the value from bits 1−0. Each bit can beindependently configured, thus allowing SDA and SCL to be configured asinputs or outputs. When set to 0, the appropriate outputs are tristated. The HFKdevelopment system includes pullup resistors on SDA and SCL to select thedefault state of high for both signals. Because all PLD registers reset to a valueof 0, care should be used to set the SDA/SCL bits (bits 1−0) to 1 beforeenabling the outputs with SDA/SCL_OE on the first access. This prevents achange in state on the pins from their tri-stated/pulled up state.

5.2.2.3 SDA/SCL

These bits are written to drive the I2C bus via “bit-banging”. When configuredas outputs, I2C signals SDA and SCL are driven directly from these registerbits. As inputs, writing to these bits will have no effect. Reads of these bitsalways return the state of the bus bits, regardless of the input/output state.

The I2C bus connects directly to the AIC2x I2C bus, and may be used forcontrolling the codec. By default, the AIC2x uses the serial data interface withembedded control; however, I2C is always available. This function could bemoved to DSP GPIO pins.

I2C can also be used in a customer system for the purposes of interfacing toa small amount of non-volatile memory, such as an EEPROM. This would beuseful for storing user configuration data across power cycle events.

5.2.2.4 LED1/0

The LED1/0 bits control the user LEDs D1 and D4 respectively. When set to1, the appropriate LED will turn off; when cleared to 0, the associated LED withthe bit will turn on (illuminate).

5.2.2.5 BTRST/CDCRST

These two bits control two general purpose outputs directly, which areconnected to the Bluetooth connector (see Table 4−2) and the AIC2x codec(see Chapter 2) reset signals. Each reset signal is intended to be active low;thus at power up, both resets will be active. The DSP must write to theMISCREG bits to remove the appropriate interfaces from the reset condition.

Logic Functions

5-5PLD

All four of the MISCREG bits function as general purpose outputs, and as such,can be moved to DSP GPIO pins. Note however, that LED drive/sink currentsmight exceed the specification for the DSP outputs in many cases. To addressthis, a small external logic gate can be used.

5.2.2.6 XDATAREG.A19-A14

The XDATAREG is probably the most complicated part of the PLD design. Thisregister should be written with the data page address bits A19-A14 that are tobe used during data accesses to external SRAM. When a data memory accessis made, as indicated by the DSP data strobe (DS) signal, the upper addressbits are internally generated from the contents of this register rather than fromthe DSP. Depending on the state of the WIN16n32 bit (see section 5.2.2.1), bitA14 may or may not be taken from this register during data accesses. WhenWIN16n32 is set to 0, address bit 14 comes directly from the DSP during datapage accesses. When cleared to 1, bit 14 is taken from the A14 bit of theXDATAREG register. Note that program accesses always have access to thecomplete external SRAM space, regardless of the setting of the XDATAREGbits.

This generation of additional address bits allows user to create up to 16x32KW(WIN16n32 = 0), or 32x16KW (WIN16n32 = 1), external data pages. The HFKnatively only supports a 512KB SRAM bank; however, address lines are runto the device pads in the event that larger SRAM devices in the same packagemay exist. The XDATAREG bits are read/write, so the bank address can beread from the PLD at any time.

The ability to map extended external SRAM into data space may not berequired for all systems, and thus, this function may be removed. Ifimplemented discretely, the function would require 4−5 general purposeoutputs to be driven with the bank address most-significant bits (DSP GPIOs),and a discrete 4 or 5 input multiplexor (MUX).

The TI SN74CBTLV3383DW is an excellent choice, as it offers very lowpropagation delay for this MUX. The MUX select signal is the DSP /DS output(data strobe), with one input of the MUX from the DSP MS address bus andthe second from the general purpose outputs making up the bank select bits.

PLD Programming Interface

5-6

5.3 PLD Programming Interface

The PLD may be programmed via one of two ways. First, a JTAG programmer,available from Xilinx (part: Parallel Cable IV, model DLC7) can be connectedto the HFK development platform. Using Xilinx’s iMPact software, theappropriate JEDEC file may be downloaded. Figure 5−2 shows the JTAGconnections to a programming pod.

Figure 5−2. cPLD JTAG Connections

Top View

TDI

TCK

TMS

TDO

PLD Programming Interface

5-7PLD

5.3.1 In-Circuit Programming via DSP

The JTAG signals are additionally connected to the DSP on the HFK, throughthe HPI port. Configured as GPIOs, this offers a second method ofprogramming under DSP control. The purpose of this connection is todemonstrate the ability to implement the PLD without incurring the high costof programming in a production environment. In order to program the PLD,code on the DSP would effectively “bit-bang” the appropriate bits to write to thePLD. The format of the stream that must be written to the PLD is exactly thesame as the JTAG programmer would use, and is described in detail athttp://www.xilinx.com.

5-8

6-1

�� !��"

This chapter features the power supply utilized by the HFK development kitplatform.

Topic Page

6.1 Overview 6-2

6.2 Load Dump 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Power Input 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 6

Overview

6-2

6.1 Overview

The HFK includes a four-rail power supply, which while seemingly large, wascreated as a compromise of cost and robustness. The four rails used in thisdesign are 1.5V (DSP core), 1.8V (codec core, also Bluetooth low voltage rail),3.3V (all digital I/O, codec analog), and a 8.0V reference from which all theother rails are generated. The 8.0V rail is additionally used to power the FMtransmitter (see Chapter 3).

6.2 Load Dump

The 8.0V rail is generated by a very robust discrete power supply design whichis architected to handle the high surge currents and voltages associated withthe automobile power bus. Since this design would typically be found in aproduct that connects to an automobile cigarette lighter, care has been takento ensure that high currents upon engine starting and jump-starting can behandled without damage to the HFK. It is recognized that not allimplementations will include this level of robustness.

6.3 Power Input

The HFK should be powered with a DC level input from 8−30V, where 12−18Vwould be considered typical. The current requirement varies depending on thefeature set and application code running on the DSP and the interfaces used.Final power numbers were not available at the time of writing, however a goodestimate would be to budget for 250mA, and add an extra 75mA if theBluetooth interface is to be added.

Power should be applied to the HFK via header J2. This header is located inlower right-hand corner of the PCB, and is detailed in Figure 6−1.

Power Input

6-3Power Supply

Figure 6−1. HFK Power Supply

Top View Bottom View

J2 PowerConnector

6-4

A-1

Appendix A

�� #$��

The following equations are used to program the HFK PLD (see Chapter 5).programming hardware is available from Xilinx. For more information, pleaserefer to http://www.xilinx.com.

library ieee ;use ieee.std_logic_1164.all ;

entity hfk is port ( RESETL : in std_logic ; −− Reset input (active−low) ADDRIN : in std_logic_vector (18 downto 14) ; −− Address ADDROUT : out std_logic_vector (18 downto 14) ; −− Address A22 : in std_logic ; −− Address SRAM_CSL : out std_logic ; −− SRAM Chip Select (active−low) FLASH_CSL : out std_logic ; −− FLASH Chip Select (active−low) RNW : in std_logic ; −− Read (1) not Write (0) OEL : out std_logic ; −− Output Enable (active−low) PSL : in std_logic ; −− Program Space Select (active−low) IOSTRBL : in std_logic ; −− IO Strobe (active−low) MSTRBL : in std_logic ; −− Memory Strobe (active−low) LED0 : out std_logic ; −− LED0 output LED1 : out std_logic ; −− LED1 output DATA : inout std_logic_vector (4 downto 0) ; −− Data RESETO0 : out std_logic ; −− RESET Output 0 RESETO1 : out std_logic ; −− RESET Output 1 RFCTRL : out std_logic ; −− RF Control CLK : in std_logic ; −− Clock SDA : inout std_logic ; −− I2C Data SCL : inout std_logic ; −− I2C Clock A0 : in std_logic ; −− Address A1 : in std_logic −− Address ) ;

attribute pin_assign : string ;end hfk ;

architecture hfk_arch of hfk is signal LADDR : std_logic_vector(18 downto 14) ; signal WIN16n32 : std_logic ; signal SDAOE : std_logic ; signal SCLOE : std_logic ; signal DATA_OE : std_logic ; signal INTADDR : std_logic_vector(2 downto 0) ; signal XDATA_CS : std_logic ; signal I2C_CS : std_logic ; signal MISC_CS : std_logic ;

Appendix A

PLD Equations

A-2

signal XDATA_REG : std_logic_vector(4 downto 0) ; signal I2C_REG : std_logic_vector(4 downto 0) ; signal MISC_REG : std_logic_vector(4 downto 0) ;

signal sREAD_DATA : std_logic_vector(4 downto 0) ;

signal sResetOut : std_logic_vector(1 downto 0) ;

constant cXDATA_ADDR : std_logic_vector(2 downto 0) := ”011” ; constant cI2C_ADDR : std_logic_vector(2 downto 0) := ”001” ; constant cMISC_ADDR : std_logic_vector(2 downto 0) := ”010” ;

begin

INTADDR(2) <= ADDRIN(14) ; INTADDR(1) <= A1 ; INTADDR(0) <= A0 ; XDATA_CS <= ’1’ when INTADDR(2 downto 0) = cXDATA_ADDR else ’0’ ; I2C_CS <= ’1’ when INTADDR(2 downto 0) = cI2C_ADDR else ’0’ ; MISC_CS <= ’1’ when INTADDR(2 downto 0) = cMISC_ADDR else ’0’ ; SRAM_CSL <= MSTRBL or not(PSL or A22) ;

FLASH_CSL <= MSTRBL or (PSL or A22) ;

OEL <= not RnW ;

ADDROUT(18 downto 15) <= LADDR(18 downto 15) when (PSL = ’1’) else ADDRIN(18 downto 15) ;

ADDROUT(14) <= LADDR(14) when (WIN16n32 = ’1’ and PSL = ’1’) else ADDRIN(14) ;

process (IOSTRBL, RESETL) begin if RESETL = ’0’ then XDATA_REG(4 downto 0) <= ”00000” ; elsif IOSTRBL’event and IOSTRBL = ’1’ then if XDATA_CS = ’1’ and RnW = ’0’ then XDATA_REG(4 downto 0) <= DATA(4 downto 0) ; end if ; end if ; end process ;

LADDR(18 downto 14) <= XDATA_REG(4 downto 0) ;

process (IOSTRBL, RESETL) begin if RESETL = ’0’ then I2C_REG(4 downto 0) <= ”00000” ; elsif IOSTRBL’event and IOSTRBL = ’1’ then if I2C_CS = ’1’ and RnW = ’0’ then I2C_REG(4 downto 0) <= DATA(4 downto 0) ; end if ; end if ; end process ;

WIN16n32 <= I2C_REG(4) ; SDAOE <= I2C_REG(3) ;

PLD Equations

A-3PLD Equations

SCLOE <= I2C_REG(2) ; SDA <= I2C_REG(1) when SDAOE = ’1’ else ’Z’ ; SCL <= I2C_REG(0) when SCLOE = ’1’ else ’Z’ ;

process (IOSTRBL, RESETL) begin if RESETL = ’0’ then MISC_REG <= ”01100” ; elsif IOSTRBL’event and IOSTRBL = ’1’ then if MISC_CS = ’1’ and RnW = ’0’ then MISC_REG <= DATA(4 downto 0) ; end if ; end if ; end process ;

RFCTRL <= MISC_REG(4) ; LED1 <= MISC_REG(3) ; LED0 <= MISC_REG(2) ;

sREAD_DATA <= XDATA_REG when XDATA_CS = ’1’ else MISC_REG when MISC_CS = ’1’ else

I2C_REG(4 downto 2) & SDA & SCL when I2C_CS = ’1’ else ”00000” ;

DATA <= sREAD_DATA when IOSTRBL = ’0’ and RnW = ’1’ else ”ZZZZZ” ;

process (CLK, RESETL) begin if RESETL = ’0’ then sResetOut <= ”00” ; elsif CLK’event and CLK = ’1’ then sResetOut <= MISC_REG(1 downto 0) ; end if ; end process ;

RESETO1 <= sResetOut(1) ; RESETO0 <= sResetOut(0) ;

end hfk_arch ;

A-4

B-1

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This document contains

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CVDD

A22

A21

A20

BC

LKR

X2

BD

R2

BF

SR

X2

TX BD

X2

RX

HPI16

A16

A17

A18

A19

R8

10K

NL

R5 10

K

Y1

11.5

2MH

z C2

30pF

C1

47pF

Schematics

B-5Schematics

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

C54xx Decoupling

Flash Decoupling

AIC24 Master

Decoupling

SRAM Decoupling

Logic and PCB Decoupling

This document contains confidential information that is the

property of Texas Instruments Incorporated and

provided under non−disclosure agreement. Reproduction and

distrubution of this information in any form is strictly


Decoupling

Capacitors

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

411

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

VD

D3_

3

VD

D1_

5

VD

D3_

3

VD

D1_

8V

DD

3_3

AV

DD

3_3

DR

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3

C9

0.01

uF

C8

0.1u

F

C7

1uF

C12

0.01

uF

C11

0.1u

F

C10

1uF

C6

0.1u

F

C5

0.1u

F

C4

0.1u

F

C3

0.1u

F

C28

0.01

uF

C27

0.01

uF

C21

0.1u

F

C22

0.1u

F

C26

0.01

uF

C25

0.01

uF

C24

0.1u

F

C23

0.1u

F

C31

0.01

uF

C32

0.01

uF

C29

0.01

uF

C30

0.01

uF

C17

0.01

uF

C16

0.1u

F

C15

0.1u

F

C19

0.01

uF

C13

0.1u

F

C14

0.1u

F

C18

0.01

uF

C20

0.01

uF

+C

3410

uFC

59

0.01

uF

C58

0.01

uF

C57

0.01

uF

Schematics

B-6

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA






Short under JP1

Misc Logic/

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

511

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

nTR

S T

(3)

EM

U1

(3)

TM

S(3

)

TD

O(3

)

AU

D_C

LK(3

,8)

AU

D_I

N(3

)A

UD

_FS

YN

C(3

,8)

AU

D_O

UT

(3)

CT

S_H

CI

TX

_HC

I(8

) nBT

RE

SE

T(6

)

RT

S_H

CI

PB

2(3

)

nUS

ER

_LE

D0

(6)

SO

FT

_TX(3

,8)

PB

1(3

)

SO

FT

_R X

(3,8

)

RX

_HC

I(8

)

nUS

ER

_LE

D1

(6)

nBT

INT

(3)

CT

S_H

CI

RT

S_H

CI

AF

E_C

LK(3

)

MC

LK(2

,6)

PB

3(3

)S

CL

(2,6

,7)

SD

A(2

,6,7

)S

OF

T_F

S(3

,8)S

OF

T_C

LK(3

)

TD

I(3

)

EM

U0

(3)

TC

K(3

)

BT

VD

D3_

3

BT

VD

D1_

8

VD

D3_

3V

DD

3_3

VD

D3_

3V

DD

3_3

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3

U10

SN

74LV

C1G

80

1 2 3

5 4

D CLK

GN

D

VC

C Q

SW

3

SW

_TA

CT

−S

PS

T/S

M1

2

SW

2

SW

_TA

CT

−S

PS

T/S

M1

2

R14

10K

R13

10K

D4 LE

D

R9

330

R52

33R

51

33

U16

SN

74LV

C1G

80

1 2 3

5 4

D CLK

GN

D

VC

C Q

R66

0

JP1

HE

AD

ER

_14

12 3 4 5 6 7 8 9 10 11 12 13 14

SW

4

SW

_TA

CT

−S

PS

T/S

M1

2

R39

10K

R61 10

KR

60 10K

R11

10K

JP2

HE

AD

ER

_7X

2

12

34

56

78

910

1112

1314

R12

330D1 LE

D

JP3

HE

AD

ER

8

1 2 3 4 5 6 7 8

Connectors

Schematics

B-7Schematics

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA






cPLD MISC LOGIC

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

611

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

nOE

(7) nS

RA

M_C

E(7

)

nMS

TR

B(3

)

nFLA

SH

_CE(7

)

LTD

I(3

)LT

DO

(3)

MC

LK(2

,5)nC

DC

RS

T(2

)S

DA

(2,5

,7)

SC

L(2

,5,7

)nB

TR

ES

E T

(5)

BA

3(7

)

nIO

ST

RB

(3)

PS

(3)

BA

1(7

)

BA

2(7

)

D9

(3,7

)D

8(3

,7)

nPO

R(3

,7,9

)

BA

4(7

)

A22

(3)

D10

(3,7

)D

12(3

,7)

D11

(3,7

)

A18

(3,7

)A

19(3

,7)

R_n

W(3

,7)

A16

(3,7

)

nUS

ER

_LE

D1 (5

)

BA

0(7

)

nUS

ER

_LE

D0(5

)

LTD

I(3

)

LT M

S(2

,3)

LTD

O(3

)

A12

(3,7

)

A17

(3,7

)

A14

(3,7

)A

13(3

,7)

LTC

K(2

,3)

VD

D3_

3

U7

XC

9536

XL−

44V

QF

P

40 41 4342 442 13 5 6 7 8 12 13 14 16 18

39 38 37

36 34 33

32 31 30 29 28 27 23 22 21 20 19 11 9 24 10

15

35

26

4

17

25

IO IO IO/G

CK

1

IO IO/G

CK

2

IO IO/G

CK

3

IOIO IO IO IO IO IO IO IO IO

IO IO IO

IO/G

TS

1IO

/GTS

2IO

/GS

R

IOIO IO IO IO IO IO IO IO IO IOT

CK

TD

IT

DO

TM

S

VCCINT

VCCINT

VCCIO

GND

GND

GND

R40

10K

JP6

HE

AD

ER

2

1 2

R45

10K

Schematics

B-8

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

This document contains confidential information that is the property

of Texas Instruments Incorporated and




Use Pin 23 for 512KB option

C54XX EXTERNAL MEMORY

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

711

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A17

A16

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A1

A3

A2

A0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A7

A6

A4

A2 A0

A1

A3

A5 A9

A8

BA

0A

13A

12A

11A10

D7

D6

D5

D4

D3

D2

D1

D0

D15

D14

D13

D12

D11

D10

D9

D8

BA

2

BA

1 BA

4B

A4

A18

A19

A20

A21

BA

3B

A3

BA

2B

A1

BA

0

A[1

9..0

](3

,6)

D[1

5..0

](3

,6)

nFLA

SH

_CE

(6)

nOE

(6)

nPO

R(3

,6,9

)R

_nW

(3,6

)

D[1

5..0

](3

,6)

A[1

9..0

](3

,6)

SD

A(2

,5,6

)

nSR

AM

_CE

(6)

R_n

W(3

,6)

nOE

(6) SC

L(2

,5,6

)

RY

_nB

Y(3

)

BA

[4..0

](6

)A[2

1..1

8](3

,6)

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3

VD

D3_

3 R35

10K

R36

10K

R15

10K

U5

AM

29LV

800B

T−7

0 E

C

25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 47 26 28 12 11 37

2746

154529 31 33 35 38 40 42 44 30 32 34 36 39 41 43 17 16 9 10

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

BY

TE

CE

OE

RE

SE

TW

E

VC

C

GNDGNDR

Y/B

Y

DQ

15/A

−1

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9D

Q10

DQ

11D

Q12

DQ

13D

Q14 A

17A

18A

19A

20

U6

IS61

5121

6−8T

54321444342272625242221201918

78910131415162930313235363738

6 17 41 40 39

2328

11 33 12 34

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CE

WE

OE

BH

EB

LE

NCNC

VD

D3_

3V

DD

3_3

VS

SV

SS

Schematics

B-9Schematics

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

This document contains confidential

information that is the property of

Texas Instruments Incorporated and

provided under non−disclosure

agreement. Reproduction and

distrubution of this information in

any form is strictly controlled by

the NDA and license agreement

conditions.

C54XX OPTIONS

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

811

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SO

FT

_R X

(3,5

)

SO

FT

_TX(3

,5)

TX

_HC

I(5

)

RX

_HC

I(5

)

TX

_HC

I(5

)

RX

_HC

I(5

)

PIN

71(3

)

PIN

38(3

)

SC

LK(2

)

SC

LK(2

)

SC

LK(2

)

PIN

73(3

)F

S(2

,3)

SC

LK(2

)

FS

(2,3

)

AU

D_C

LK(3

,5)

AU

D_F

SY

NC (

3,5)

SO

FT

_FS

(3,5

)

SO

FT

_FS

R(3)

SO

FT

_R X

(3,5

)

R10

0

0 N

LR

101

0 N

LR

640

NL

R63

0 N

L

R62

0

R65

0 N

L

R42

0

R10

30

NL

R43

0

R10

20

NL

R10

4

0 N

LR

440

Schematics

B-10

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

This document contains confidential information that is the property of Texas Instruments Incorporated and

provided under non−disclosure agreement. Reproduction and distrubution of this information in any form is strictly


POWER SUPPLY AND

RESET CIRCUITRY

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

911

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

nPO

R(3

,6,7

)

VD

D3_

3

DR

VD

D3_

3

BT

VD

D3_

3

VD

D3_

3V

DD

1_8

VD

D1_

8

AV

DD

3_3

VD

D1_

5

VD

D3_

3

BT

VD

D1_

8

VD

D3_

3

VD

D9.

5

R23

330

D3 LE

D

R22 10

K

C37

10uF

C44

4.7u

F

U8 T

PS

7773

3−P

WP

16 71314

516 15

2 3 9 10 11 12 19 20481718

GN

D

VIN

VIN

VO

UT

VO

UT

EN

RE

SE

T/P

G

FB

/NC

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

NC

NC

NC

NC

L5 FB

EA

D

L4

FB

EA

D

C50

0.01

uFC

510.

1uF

C47

0.1u

F

C49

10uF

C46

0.01

uFC

4510

uF

C43

0.1u

F

L3 FB

EA

DC

420.

01uF

C41

10uF

L9 FB

EA

D

U9

TP

S76

9 18

1 23

5 4

VIN

GN

D

EN

VO

UT

NC

/FB

C48

4.7u

F

L12 FB

EA

D

L10 FB

EA

D

L11

FB

EA

D

U12

TP

S76

9 15

1 23

5 4

VIN

GN

D

EN

VO

UT

NC

/FB

L2 FB

EA

DC

390.

01uF

C38

10uF

C40

0.1u

F

Schematics

B-11Schematics

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

POWER SUPPLY INPUT

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

1011

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofRF

_VO

UT

(11)

VD

D14

VD

D9.

5

VD

D14

VD

D14

L14

FB

EA

D

C35

22uF

D5 M

MS

Z52

57B

−7

R10

6

2K

U18

TL5

001

2

5

6 7 8

1

3 4

VC

C

SC

P

DT

C

RT

GN

D

OU

T

CO

MP

FB

R11

0

19.1

K

C66

2700

pF

C65

27pF

R11

4

1.18

K

R11

2

10K

R11

3 421

C71

1200

pF

C67

22uF

R11

1

44.2

KC

69

1uF

R10

9

232

C70

0.1u

FD

6M

MS

Z52

31B

−7

R10

8

10K

Q6

2N70

02/S

OT

R10

5

1K

U17

IRF

R90

24

J1 CO

NN

PLU

G 2

1 21 2

R10

7 10

R7

0

D7

MB

RS

360T

R

Q4

MM

BT

3904

/SO

T

L13

IND

UC

TOR

IRO

N1

Q5

MM

BT

5401

L

J2 RA

SM

712

C36

0.1u

F

C33

1.0u

F

Schematics

B-12

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

This document contains confidential information that is the property of Texas Instruments Incorporated and

provided under non−disclosure agreement. Reproduction and distrubution of this information in any form is strictly


RF OUTPUT

tuning, omit for fixed frequency

use air coil

5071

92−0

001

C

Han

dsfr

ee D

evel

opm

ent K

it B

ase

Boa

rd

A

1111

Thu

rsda

y, D

ecem

ber

11, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

RF

_VO

UT

OU

TP

1(2

)

MIC

_VO

UT

U11

TP

S71

5 011

2

345

FB

/NC

GND

NC

INO

UT

C56

1uF

L6 47nH

Q3

2N22

22

R67

44.2

K

R68

7.87

K

C64

3−20

pF

R26

4.7K

R28

2.2K

C68

1uF

C55

1nF

R29

150

C54

6.0p

F

C52

47pF

A1

CO

N1

1

SW

1

SW

SL

IDE

213

C-1

Appendix A

��

The HFK development platform was designed to use standard componentswith low tolerances wherever possible. While customers are encouraged touse the bill of material items called out, many manufacturers may substitutecomponents for purchasing, availability, and cost reasons. For the most part,such substitutions will not adversely affect the performance of the HFK design.Several key areas are noted, however, where components have been chosenfor a particular reason. Therefore, extra care should be taken if substitutionsare made. These areas are:

� Air coil

The chosen device has a minimum Q of 42 − the higher the better, as thiscomponent controls the stability of the FM transmission. Alternate FMtransmission architectures may be used, which may eliminate/change thiscomponent.

� All components in the 8.0V power supply

This design is field proven and stable. Changes to the design are notwarranted by Texas Instruments and are discouraged. The key elementhere is protection against surge currents during vehicle start (assuminginstallation into cigarette lighter or automobile power bus, as well as thoseduring accidental reversal of polarity when jump-starting said automobile).Other power supply designs are acceptable − the 8.0V rail was chosen toprovide adequate stability for the FM transmitter tank circuit. AlternativeFM transmitter topologies may allow for a reduction in this supply voltage.

� All electrolytic capacitors

Manufacturers are encouraged to validate the derated voltage rating of allsuch components when choosing a part.

� SRAM and FLASH

Chosen components are commercially available. Any changes to thesecomponents should be validated with regards to timing and voltagetolerances. Timing may be adjusted within the DSP; however slowerdevices than those specified may reduce performance of the HFKplatform.

Appendix C

C-2

Table C−1 contains the HFK Development System bill of materials. Partnumbers from DigiKey Corporation (http://www.digikey.com) have beenincluded for ease of ordering/cross reference.

Table C−1. HFK Development System Bill of Materials

Description Designator Package Quantity DigiKey Part Number

36 Macrocell cPLD U7 VQFP44 1 122-1259-ND

16-bit 26-KSPS dual channelcodec

U1 TQFP48 1 TLV320AIC24-PFB

DSP U2 PQFP144 1 TMS320VC5407-PGE

FLASH, 70nS U5 TSOP48 1 AM29LV400/SO48

SRAM, 512K x 16, 8nS U6 TSOP44 1 CY7C1041BV33

Positive-edge-triggeredD-type flip-flop

U10, U16 SOT-25 2 296-9851-1-ND

Linear regulator, 1.8V U9 SOT-25 1 296-11033-1-ND

Linear regulator, 1.5V U12 SOT-25 1 296-11032-1-ND

750mA low dropout regulator U8 PSOP20 1 296-8136-5-ND

11.52MHz Y1 XTAL_SM 1 300-6125-1-ND

Transistor, MMBT5401 Q5 SOT23 1 MMBT5401DICT-ND

Transistor, NPN, FMMT3904 Q4 SOT23 1 MMBT3904DICT-ND

Transistor, NPN Q3 TO-92 1 PN2222-ND

Transistor, Mosfet, N channel Q6 SOT-23 1 2N7002CT-ND

Transistor, Hexfet, 8.8A U17 DPAK 1 IRFR9024N-ND

Pulse-width-modulationcontrol circuit

U18 SO8 1 296-2472-5-ND

Zener, 500mW, 33V D5 SOD123 1 MMSZ5257BDICT-ND

Zener, 500mW, 5.1V D6 SOD123 1 MMSZ5231BDICT-ND

Rectifier, Schottky, 3A D7 SMC 1 MBRS360CT-ND

LED, green D1, D3, D4 1206 3 350-1345-1-ND

.047uH L6 2220 1 DN4010CT-ND

220uH L13 5022 1 DN2316CT-ND

C-3Bill of Materials

Table C−1. HFK Development System Bill of Materials (Continued)

Description DigiKey Part NumberQuantityPackageDesignator

Ferrite bead, 150 ohms L2, L3, L4, L5, L9,L10, L11, L12, L14

603 9 240-1139-1-ND

Microphone, omnidirectional M2, M1 MICELECT 2 P9949-ND

2-6pF, ceramic dielectric C64 2220 1 SG2017CT-ND

22uF,25V C35, C67 2816 2 PCE3102CT-ND

4.7uF ,16V,X5R C44, C48 1206 2 PCE3007CT-ND

10uF, 20V C34, C37, C38, C41,C45, C49

1311 6 PCE3022CT-ND

1uF, 16V, +/-20%, X7R C7, C10 1206 2 478-1567-2-ND

.1uF, 50V, +20/-20%, Z5U C56 1206 1 445-1423-1-ND

1uF, 10V, X5R, +/-10% C33, C69 805 2 PCC1807CT-ND

.1uF, 16V, +/-10%, X7R C3, C4, C5, C6, C8,C11, C13, C14, C15,C16, C21, C22, C23,C24, C36, C40, C43,C47, C51, C60, C61,C62, C63, C70, RC1,RC2

603 26 PCC1762CT-ND

.01uF, 50V, +/-10%, X7R C9, C12, C17, C18,C19, C20, C25, C26,C27, C28, C29, C30,C31, C32, C39, C42,C46, C50, C57, C58,C59, C66

603 22 PCC1763CT-ND

.001uF, 50V, +/-5%, NPO C55 603 1 PCC1772CT-ND

3300pF, 50V, +/-10%, X7R C71 603 1 311-1075-1-ND

47pF, 50V, +/-5%, NPO C52, C1 603 2 PCC470ACVCT-ND

33pF, 50V, +/-5%, NPO C2 603 1 PCC330ACVCT-ND

27pF, 50V, +/-5%, NPO C65 603 1 PCC270ACVCT-ND

6pF, 50V, +/-.5pF, NPO C54 603 1 PCC060CVCT-ND

0 ohm, 1/8 W R7 1206 1 P0.0ECT-ND

2K, 5%, 1/8 W R106 1206 1 P2.0KALCT-ND

C-4



10K ohm, 5%, 1/10 W R108 805 1 311-10KACT-ND

0 ohm, 1/16 W R42, R43, R44, R56,R57, R62, R66

603 7 P0.0GCT-ND

680 ohm, 5%, 1/16 W R37, R38 603 2 P680GCT-ND

10K ohm, 5%, 1/16 W R1, R2, R3, R5, R6,R11, R13, R14, R15,R22, R32, R35, R36,R39, R40, R45, R60,R61

603 18 P10KGCT-ND

4.7K ohm, 5%, 1/16 W R26 603 1 P4.7KGCT-ND

330 ohm, 5%, 1/16 W R9, R12, R23 603 3 P330GCT-ND

150 ohm, 5%, 1/16 W R29 603 1 P150GCT-ND

33 ohm, 5%, 1/16 W R51, R52, R55 603 3 P33GCT-ND

10 ohm, 5%, 1/16 W R107 603 1 P10GCT-ND

2.2K ohm, 5%, 1/16 W R28 603 1 P2.2KGCT-ND

44.2K ohm, 1%, 1/16 W R67, R111 603 2 P44.2KHCT-ND

6.34K ohm, 1%, 1/16 W R114 603 1 P6.34KHCT-ND

30.1K ohm, 1%, 1/16 W R110 603 1 P30.1KHCT-ND

3.01K ohm, 1%, 1/16 W R113 603 1 P3.01KHCT-ND

10.0K ohm, 1%, 1/16 W R112 603 1 P10.0KHCT-ND

7.87K ohm, 1%, 1/16 W R68 603 1 P7.87KHCT-ND

1K ohm, 1%, 1/16 W R105 603 1 P1.0KYCT-ND

232 ohm, 1%, 1/16 W R109 603 1 P232HCT-ND

Switch, SMT, slide SW1 SLIDESW_SM 1 CAS120JCT-ND

Switch, SPST right angle SW2, SW3, SW4 7260 3 CKN9008CT-ND

Audio jack, 2.5mm, 4conductor

JP4 2.5MM 1 CP-42536SJ-ND

Power jack, 2mm, male J2 CON2.5MM 1 CP-102AH-ND

Stereo jack, 3.5mm J4 3.5MM 1 CP-3533N-ND

C-5Bill of Materials



Header, 8 X 1 JP3 HDR8X1 1 S1012-36-ND

Header, 2 X 1 J1, JP6 HDR2X1 2 S1012-36-ND


Header, 7 X 2 JP2 HDR7X2 1 929710-03-36-ND


1uF, 16V, 5%, Y5V C68 603 1 478-1264-1-ND

Low dropout regulator U11 DCK 1 296-12957-1-ND

C-6

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