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JEONG AND PARK: ANALYSIS AND COMPENSATION OF DEAD-TIME EFFECTS

increas ingVANfor i 0, the shape of the output voltage follows the basedrive signal B1. On the other hand, for < 0, the voltage isshown to be a complementary shape of the signal B2. Thisobservation says that the output voltage is determined by onlyone of the two drive signals, which is called the active signal inthe following, whereas the other one is said to be inactive.Thus, in order to maintain the original pulse width of the controlsignal, the active drive signal should be made to be the same (orinversely the same) as the control signal. The inactive drivesignal needs only to be properly designed to guarantee the timedelay with respect to given switching instants of the activesignal.

Fig. 8shows the process of waveform synthesis. The signal Sis assumed to be a portion of the original PWM wave. S1 ands 2 are delayed signals of s, by Td and 2Td, respectively. Thefollowing waveforms show two sets of required drive signals B1and B2 to be synthesized for positive and negative current,respectively. Note that the active side of the drive signals ismade to be a replica (or an inverse replica) of SI. The other twosignals S and S2 are used to define the transition edges ofinactive side of drive signals. For example, under the condition

f 0 I

a) (b)Fig. 8 . Waveform synthesis for the compensation of dead-time effect: a)Tp > 2 T d ; b ) p < 2 T d .

B1

B2

* -Fig. 9. Dead -time compensation circ uit with logical combination.

< 0, the inactive signal B1 rises at the rising edge of S2 andfalls at the falling edge of S, as is shown in Fig. 8(a), but whenthe pulse width is shorter than twice the time delay, as in Fig.8 b), B1 is dropped out. The current direction determines the setof drive signals that is to be selected. Then, the output voltagewaveform will follow S1, which has the same shape as S, butwill be delayed by Td which does not matter practically.The synthesis of drive signals is achieved by logical combina-tions of the signals S, S1, and S2 in conjunction with I , whichis the signal that represents the current direction. Let I be aBoolean variable 1 when i > 0 and 0 when i < 0. A study onall possible cases for various pulse widths has shown that therelationships between the signals reduce to following simpleformulae:

Any reversal of current direction switches the drive signalsfrom one set to the other. However, in some intervals, theswitchover may result in a time delay that is unsufficient tocomplete the commutation. For example, consider the first inter-val in Fig. 8(a), where (S, S1, S2) = (1,0,0). If the currentreverses direction from negative to positive during the interval,B2 changes state from 1 to 0 instantaneously at the zero cross-

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JEONG AND PARK: ANALYSIS AND COM PENSATION OF DEAD-TIME EFFECTS 113

b)Fig. 10. a) Reference and current wave forms horizontal 2 ms/div,vertical 2 V/div, and 5 A/div) and (b) frequency spectrum of output voltagefrom 0 to 5 lcHz uncompensated).

b)Fig. 1 1 . a) Refere nce and current wave forms horizontal 2 ms/div,vertical 2 V/div, and 5 A/div) and b) frequency spectrum of output voltagefrom 0 to 5 kHz compensated by Method I).

ing, whereas B l remains 0. Soon after, B1 rises to 1 at the endof the interval before the sufficient time has elapsed, which maycause the short circuit of dc link. The upward and downwardarrows in Fig. 8 indicate that the zero crossing of the current insuch a direction should be avoided during the correspondingintervals. This can be achieved by allowing the signal tochange state only on the intervals where S , S1, S 2 ) = 0, ,O)or 1, 1, 1).Fig. 9shows a realization of (12). The D flip flop is used tolatch the current direction signal during the intervals denoted byarrows. Delayed signals S1 and S 2 are generated through a shiftregister. However, in the memory-based PWM, where the signalS is stored in a bit of the memory, two adjacent bits, instead ofthe shift register, may be used to store the delayed signals. Thecircuit in Fig. 9 is simple and can be realized with only a fewICs. Moreover, since the circuit itself guarantees the timedelay, the time delay element in Fig. 1becomes unnecessary.C. E xper imenta l R es u l t s

The compensation circuits proposed are applied to a single-phase full-bridge transistor inverter that supplies an inductiveload. In each leg of the inverter, two independent compensationcircuits are implemented while they use a common currenttransformer for current feedback. The inverter operates onsinusoidal PWM, and the carrier frequency is 40 times thefrequency of the reference M = 40). Fig. 10 (a) shows the

uncompensated reference and current waveforms. It can beobserved that the current waveform is significantly distorted.The frequency spectrum of the output voltage is shown in Fig.10 (b), which exhibits the low-order harmonics and extendedsidebands near the dominant switching harmonics of the 79thand 81st order.Fig. 11 (a) shows the reference voltage and output currentunder the compensation of Method I. The reference has beenmodified according to the current direction so that the currentovercome the reaction of the dead-time effect. When comparedwith Fig. 10 (a), the current waveform shows significant im-provement in shape, as well as the increase in magnitude. Theseimprovements are reflected in the frequency spectrum shown inFig. 11 (b), wherein undesirable harmonics have disappeared,and the fundamental component has been increased.Method I1 compensation is realized with the circuit in Fig. 9.The PWM signal S is generated through a normal sinusoidalPWM circuit for comparison with Method I. Fig. 12 showsexperimental results associated with Method 11. Although thereference wave is unchanged, the current waveform and thespectrum of the output voltage are similar to the ones in Fig. 11.However, it is observed that in Method 11, the magnitudes of thecurrent and fundamental voltage are slightly greater than those

with Method I . This is because Method I completely cancels thetime delay, and the reverse recovery time that has been ne-glected so far now affects the output voltage in an oppositemanner to the dead-time effect.

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114 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 38, NO. 2, APRIL 1991

b)Fig. 12. a) Referenc e and current waveforms horizontal 2 ms/div,vertical 2 V/div, and 5 A/div) and b) frequency spectrum of output voltagefrom 0 to 5 kHz compensatedby Method 11).

IV. CONCLUSIONThe switching time delay in a PWM inverter has a detrimentaleffect on inverter operation. It causes a decrease in the funda-mental component and an increase in low-order harmonics. Ithas been shown that the effect is closely related to the phase (notthe magnitude) of the output current. Analytical results show

that the dead-time effect can be evaluated by averaging thevoltage deviations. Simple formulae to predict the variation offundamental voltage and the magnitude of low-order harmonicsare derived and verified through simulation.In view of theoretical examinations, this paper presents two

compensation schemes -the modification of the reference waveand the logical combination of PWM signals. The former isadequate for subharmonic PWM and the latter for memory-basedPWM. Of course, the latter method works well with any othermodulation techniques including subharmonic PWM . In thisregard, the method based on logical combination seems to bemore general while it shows slight overcompensation. Neverthe-less, both are simple and easy to implement. The only supple-mentary equipment they require is the current sensor, whichneed not be a high-performance one. There are many applica-tions of the PWM inverter that inherently require current feed-back. The compensation schemes proposed would be particularlysuitable and readily applicable for such systems.Experimental results ensure the usefulness of the compensa-tion methods. Although the pulse width modulation may be of avariety of realizations, the principle of the current feedbackdiscussed in this paper will be useful for any type of modulationin compensating the dead-time effect or in improving the perfor-mance of the inverter.

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