THE ARITHMETIC-LOGIC UNIT

BINARY HALF-ADDER

BINARY HALF-ADDER condt

Half adder

Input Output

X Y S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Karnaugh Map and formulae for S

0 1

1 0

)()( YXYXSYXYXS

YXYXS

Y

X X

Y

FULL ADDER

Inputs Outputs

X Y Ci S Co

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Karnaugh Map and formulae for S

0 1 0 1

1 0 1 0

YX YXYXYX

iC

iC

)()()()( iiii

iiii

iiii

CYXCYXCYXCYXS

CYXCYXCYXCYXS

CYXCYXCYXCYXS

Karnaugh Map and formulae for carry out

0 0 1 0

0 1 1 1

YX YXYXYX

iC

iC

)()()(0

0

0

YXCYCXC

YXCYCXCYXCYXCYXCYXC

CXCYYXCYXCYXCYXCYXC

ii

iiiiii

iiiiii

FULL ADDER condt

Half adder

11

Half adder

2 S2

FULL ADDER condt

ii

iiii

iiii

iiii

iiii

iii

iiii

CYCXYX

XXCYYYCXCCYX

CYXCYXCYXCYX

CYXYXCCYXCSYXCCC

CYXCYXCYXCYX

CYXYXCYXCYX

CYXYXCYXYXCSCSSS

1210

112

FULL ADDER (IBM version)

FULL ADDER (IBM version) condt

CYXCYXCYXCYX

CYXCYXCYCXYXCYXXYCYXCYX

CYXXYCYXCYCXCYXXYCXYYCXC

))(()]())([(

)]())()([()]([

CYXCYXCYXCYX

CYXCYXCYCXYXCYXXYCYXCYX

CYXXYCYXCYCXCYXXYCXYYCXC

))(()]())([(

)]())()([()]([

CYXCYXCYXCYX

CYXCYXCYCXYX

CYXXYCYXCYX

CYXXYCYXCYCX

CYXXYCXYYCXC

))((

)]())([(

)]())()([(

)]([

PARALLEL ADDER

Applying the parallel adder for addition of natural numbers

Examples

a) b)

0111

1100

1101

00001

1010

1101

Applying the parallel adder for addition of integers in 2s complement code Examples a)

0111

1100

1101

1110010

;1011101

22

22

c

c

bb

aa

111ba

Example b)

00011

1011

1101

1101011

;1011101

22

22

c

c

bb

aa

1000ba

Skip!

Example c)

11101

0011

1101

1100100

;1011101

22

22

c

c

bb

aa

21011baSkip!

Contradiction because

Applying the parallel adder for addition of integers in 1s complement code Example a)

0001

1

11101

1011

0101

1101010

;1010101

2

2

odw

odw

bb

aa

111ba

Example b)

1110

1

01101

0011

0101

1100011

1010101

12

12

c

c

bb

aa

)!(10002 rangeofoutba

Parallel addition and subtraction

Basic logic operations

Shift operations

Generalized parallel arithmetic element

Problems encountered during multiplication

1010111

1001

1001

0000

1001

1011

1001

Multiplicand

Multiplier

Partial products

Product

Operations to be performed by ALU during multiplication:

• To sense whether a given bit is 1 or 0;

• To shift left partial products;

• To add the partial products.

Basic steps during multiplication:

• The accumulator is reset to 0, the multiplicand is load to the register Y and the multiplier is load to the register B.

Accumulator

0………….0

B register

multiplier

Y register

multiplicand

Basic steps during multiplication condt

• The following basic step is repeated n times where n is the number of bits in magnitude part of the numbers being multiplied:– 10 If the rightmost bit in the B register is a 0, the

combined accumulator and B register are shifted right one place.

– 20 If the rightmost bit in the B register is a 1, the number in Y register is added to the contents of the accumulator, and then the combined accumulator and B register are shifted right one place.

When basic steps are finished, the contents of the combined accumulator and the B register consist of the product being derived. The sign of it is set by a separate circuit.

Example 22 0110101001

01001

1010100011

01001

0101000111

01001

1010100101

01001

0101100010

01001

1011000100

01001

0110100000

543

21

Y

BX

Y

BX

Y

BX

Y

BX

Y

BX

Y

BX

StepStepStep

StepStep

Product: 00011101012

Problems encountered during division

76

396

067

583

77:0164

95

DivisorDividend

Remainder

Quotienta)

Problems encountered during division condt

2

2

22

2

101

000

1011:101

0

Remainder

b)

Dividend Divisor

Quotient

Problems encountered during division condt

1

01

11

01

11

01

01:1111

111

22

Remainder

c)

Divisor

Quotient

Dividend

Description of the division procedure:

• Before the procedure starts, the B register is reset to 0, the dividend is read into the accumulator and the divisor into the Y register. After the division, the quotient is stored in the B register, and the remainder in the accumulator. Both divisor and dividend are to be positive.

Accumulator

dividend

Y register

divisor

B register

00000

Description of the division procedure condt

• The procedure is divided into the following steps:– Step I. A „trial division” is made by subtracting

the Y register from the accumulator. The sign bit of the accumulator is examined and the dividend (accumulator) is restored by adding the divisor to the result of the subtraction. If the above sign bit is 1, the process of division is completed, if it is 0, the process is continued.

Description of the division procedure condt

– Step II. The leftmost 1 bit in the divisor is aligned with the leftmost 1 bit in the dividend by shifting the divisor left and recording the number of shifts required to make this alignment. That number of shifts plus 1 is the value of the parameter p applied in the next step.

– Step III. The contents of the Y register is subtracted from the accumulator (operation performed in 2s complement code, the result replaces the contents of the accumulator). There are two possible cases.

a) A new contents of the accumulator represents a negative number i.e. its sign bit is 1. Therefore the previous contents of the accumulator is restored by adding to it the contents of the Y register and the long register X+B is shifted left one place putting 0 is as the rightmost bit of X+B.

b) A new contents of the accumulator represents a non negative number i.e. its sign bit is 0. In that case the long register X+B is shifted left one place putting 1 as the rightmost bit of X+B.

The step III is repeated p times.– Step IV. The contents of the accumulator is shifted right p times.

Examples

0011

11:01101

a)

0110

1011:0110

c)

10111

0010

0101:11010

101

b)

Example a) 22 11:110

00110

0001000000

00110

0001000000

00110

0000111010

00110

0000100000

00110

0000000000

00110

2

0000000110

00011

0000000110

00011

0000000011

00011

0000000110

2/

1/

Y

BX

Y

BX

Y

BX

Y

BX

Y

BX

pY

BX

Y

BX

Y

BX

Y

BX

IVStepIIIStep

IIIStepIIStep

IStep

quotient: 102 ; remainder: 02 .

Example b) 22 1101:110

01101

0000000110

01101

0000011001

01101

0000000110

Y

BX

Y

BX

Y

BXIStep

quotient: 02 ; remainder: 1102

.

Example c) 22 10:1011

01000

0010100001

01000

0010101000

01000

0001000100

01000

0001001100

01000

0000111110

01000

0000100110

01000

0000000011

01000

3

0000001011

00010

0000001011

00010

0000001001

00010

0000001011

3/

2/1/

Y

BX

Y

BX

Y

BX

Y

BX

Y

BX

Y

BX

Y

BX

pY

BX

Y

BX

Y

BX

Y

BX

IVStepIIIStep

IIIStepIIIStep

IIStepIStep

quotient: 1012 ; remainder: 12 .