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The Automatic Generation of Merged-Mode Design Constraints
Subrangshu K. Das, Texas InstrumentsAjay J. Daga, FishTail Design AutomationAishwarya Singh, Texas InstrumentsVikas Sachdeva, FishTail Design Automation
Constraints Development Challenges
Number of operating modes supported in a design today has increased tremendously (>20)
Each operating mode could be unique in terms of its timing requirements
Constraints designer needs to understand all these “unique” timing
requirements and capture them in the constraints
Prior Solutions1. Single-mode implementation flow
Using most timing-critical “operating” mode E.g., if freq. clkb > freq. clka,
SDC-1: set_case_analysis 1 sel Single timing-critical mode is extremely rare
2. Multi-mode implementation flow Separate constraint files for each
“operating” mode SDC-1: set_case_analysis 0 sel SDC-2: set_case_analysis 1 sel
Easy to create but tool run-times become prohibitive beyond 2-3 modes (on complex IPs)
3. Merged-mode implementation flow Created by collapsing constraints for
multiple “operating” modes into one No case-analysis SDC-1: set_clock_groups –
logically_exclusive –group clka –group clkb Effort intensive and error-prone No easy way to review
clka
clkb
sel
0
1
FF1 FF2
Ideal Solution: Designer creates individual mode SDC files and a tool automatically collapses them and also generates the clock-exceptions!
Key Components for “automation”
clka
clkb
sel
0
1
FF1 FF2
1. Ability to define boolean condition required to propagate a clock signal from one node to another
2. Ability to calculate dot-product between two sets of boolean expressions to see if 2 clocks can interact or not False-path if dot-product == 0
TI and Fishtail collaborated to enhance Focus (formal tool) to handle above and generate exceptions automatically during merging
1. Mode-table2. Case-analysis to block clock propagation3. Clock-propagation false-path4. Logically-exclusive5. Partially-exclusive
Enhancements in Focus
Automated Constraints Generation Flow
Design Statistics Complex IP with ~1.6 Million instances Multiple clocks (~25) with highest clock frequency being 266 MHz ~30 operational modes including test modes
Merged-mode
# of set_clock_sens
e (stop propagation)
# of generated
clocks (partially-exclusive)
# of clock exceptions
# of case-analysis
generatedRun time
Memory Usage
Capture 17 30 133 2 4 hr 9.2 GB
Func-PBIST 56 0 1 3 3 hr 6 min 9.37 GB
Shift 1 12 8 107 3 hr 16 min 9.21 GB
P1500 2 61 248 0 4hr 40 min 9.34 GB
Focus Results
No missing / erroneous exceptions Constraints un-touched in the course of the entire P&R and STA
flow
Focus helped catch design bugs! DFT clock implementation is complex and is custom-built for
every IP Verifying DFT clock implementation is difficult using
conventional techniques for scenarios like: Ensure ATPG shift and ATPG capture clocks do not interact in any of the
operating modes No timing paths in the design between 2 ATPG capture clocks
(programmed for simultaneous capture) in TFT However constraint designer assumes above when writing
constraints Design implementation bug can easily get un-detected till late in the
design or worse after Si! Focus formally proves if 2 clocks are mutually-exclusive and
then generates clock-exception in merged SDC Absence of clock-exceptions (clock-crossing report) with help of clock-
propagation/interaction reports helped catch implementation bugs (>5)
Conclusions Described how Focus was used to
1. Automatically generate merged-mode constraints from mode-table spreadsheet
2. Automatically generate clock-exceptions to remove pessimism
Helped reduce constraint development cycle-time by a factor of 2-3X No last-minute heart-aches due to constraint bugs!!
Described how Focus helped in catching implementation bugs that could have been missed in conventional verification
Thank You
Configuration registers
Configuration ports
Operating Modes
Back
Mode-table spreadsheet
CLKA
CLKB
SEL1
SEL2
MODE1 MODE2
SEL1 0 1
SEL2 1 0
Modes being MergedMODE1MODE2
set_case_analysis 1 mux1/s
0
1
1
0
1
Case-Analysis to Block Clock Propagation
Back
mux1
FF1 FF2
0
1
Clock Propagation False-path
TESTMODE
CLKA
CLKB
TCLK
0
0
01
1
1
set_clock_sense –stop_propagation –clocks {TCLK} [get_pins mux3/b]
mux1
Back
mux3
mux2
FF1 FF2
SEL
AUXCLK0
PICLK0 0
1
AUXCLK0
PICLK0 – functional clock AUXCLK0 – shift clock SE – scan enable
set_clock_groups –logically_exclusive –group AUXCLK0 -group PICLK0
SE
ICG
SE = 0
SE = 1
Logically-Exclusive Clocks
FF1 FF2
mux1
Back
CLKA
CLKB
create_generated_clock mux1/Z –name clka_1 –master_clock CLKA create_generated_clock mux1/Z –name clkb_1 –master_clock CLKB
set_clock_groups –physically_exclusive –group CLKA –group CLKB
Partially-Exclusive Clocks
Back
FF1 FF2
FF3 FF4
mux1
0
1