The Changing Model For Testing Complex SOC Mobility Devices20 Teradyne Proprietary Information...

The Changing Model For Testing Complex SOC Mobility Devices

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“The Human Brain” The Most Complex SOC Device?


Part Of a Bigger System – The Human Body

Source: VICTOR DE SCHWANBERG/SCIENCE PHOTO LIBRARY


A Test Model For Complex SOC Devices?


Functional Components (Senses) Are Major Test Ports


How Would We Test Each of these Primary Functions?

• Sight Port

• Hearing Port

• Taste Port

• Touch Port

• Smell Port


Traditional Testing Of The Sight Port


Traditional Testing Of The Hearing Port


Traditional Testing The Taste Port


Traditional Testing The Touch Port


Traditional Testing The Smell Port


The Problem with These Traditional Testing Methods

• Does not test all the complex interactions between the functions of the brain

• Does not simulate real word “mission mode” conditions (eating a meal, having a conversation, listening to music, watching a movie, etc)

• Does not capture complex responses from individual tests and non-determinist events such as emotions (fear, anger, happiness, sadness, anxiety, love, etc)

• Does not test the real quality of the brain functions

AND to fully test brain function this way takes too long

…………………………..A lifetime!


The Same is True for Testing Complex SOC Mobile Devices

We could test each block though its traditional “test“ port” but that wouldn’t test it in real world “mission mode” conditions

Integrated Mobile Device

CPU

DRAM

I/F

Flash

I/F

JTAG

I/F

USB

I/F

DSP BB

Proc

Power Mgmt

Functions Audio / BB

Functions GPS

3G

WiFi

FM/TV


But What if?:

• We could simulate real world “mission mode” conditions to test the brain and do multiple of them concurrently and in parallel?

• That would

Simplify the testing process

Shorten the time to test

Improve the quality of test

Capture complex “real world” responses

Accurately detect non-deterministic response


Examples of Real World Simulations

• Consider these “Sense Testing Protocols”


Results of “Protocol” Testing of Senses

• Simulates real word “mission mode” conditions

• Stimulates complex interactions and responses between the senses

• Improves the quality of test of the brain functions

• Faster Test Time by testing multiple ports in parallel


Now lets Turn to Complex SOC Devices, Specifically for Mobility

Mobile Devices are Rapidly Outpacing PC’s


Mobility Apps Drive ASSP Chips

Figure 4. Annual Revenue of Application-Specific Chips, 2009-2016 (Millions of Dollars)

Millions of Dollars

140,000

120,000

100,000

80,000

60,000

40,000

20,000

0

2009 2010 2011 2012 2013 2014 2015 2016

Application-Specific Chips for Mobile Phones and Tablets Other Application-Specific Chips

Source: Gartner (May 2012)


Continued Cost Pressure

$0

$5

$10

$15

$20

$25

$30

$35

$40

$45

$50

2009 2010 2011 2012 2013 2014 2015 2016

IC $

Digital Cellular, Basic Digital Cellular, Enhanced Digital Cellular, Smartphone

IC $ per End Application


Market Window Transitions Becoming Extremely Narrow – One Quarter!

22

20M

The world changes over 1 quarter

• iPhone3GS goes from 8M to 3M

• iPhone 4 goes from 0 to 12M

Each phone generation contains updated

devices with different test programs and

required configurations

iPhone4

iPhone3GS


Functional Integration, 3D IC and Wafer Scale Packaging Continues to Increase Test Complexity

Source: Gartner

Functional Test Requirements:

• Multiple Interface standards

• Complex data flows

• Multiple, simultaneous active interfaces

• RF to Bits testing

• “Industry Standard” Interfaces

Device Architecture Trends:

• Re-use of complex and 3rd party IP

• Asynchronous core interfaces

• NoC – Network on Chip technologies

• Independent PLLs within IP cores

• Redundant cores and repair during test

• 3D and WLP


So Our Industry Dynamics Confirm that Traditional Approaches to Test Won’t Work

Must test:

• Faster (Time to Market and Test Time)

• Cheaper

• Higher quality and increased complexity

“Zero dppm”

Will it work in real world “mission mode”?


What Happens With Traditional Test Approaches

• Test development time is longer because ATPG can’t predict real-world behavior of all the different interfaces

And it all changes with Process, Voltage and Temperature

• Yield is reduced because good devices don’t match simulation

• Test times are long because multiple pattern executions are required looking for a pass or the test must capture and post-process large data sets

• Device quality is inadequate because the DUT is not tested in “Mission Mode”

“Stored Response” ATE Complex SOC Device Architecture


CPU

DRAM

I/F

Flash

I/F

JTAG

I/F

USB

I/F

DSPBB

Proc

Power Mgmt

FunctionsAudio / BB

Functions GPS

3G

WiFi

FM/TV

Tries

to

Test


Impact of Silicon Integration on Device and ATE Complexity

In each decade semiconductor device complexity increases by >10x and

requires a new tester architecture

Time

Chip Complexity (Transistor Count)

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

10,000,000,000 -New complex devices have more IP Blocks, more gates,

-more clock domains.

- IP re-use makes devices easier and faster to

design but more difficult and slower to test.

1990’s

Logic, Memory & Analog

Analog non-determinism

1980’s Multiple Digital functions

Complex Timing

2010’s IP re-use & DUT Master

Digital non-determinism

Per Pin Timing

Mixed Signal &

Memory Test

Protocol Aware

2000’s

Integrated RF

And SERDES

RF & SERDES

High speeds


What is Protocol Aware (PA) Test?

• PA = Tester Hardware & Software communicates with the DUT port in its native “Protocol”:

Handling physical issues like unknown data timing and content on-the-fly

Enabling programming in “Design” terms, bypassing ATPG processes

• Examples

Control Busses; JTAG, SPI, I2C, etc.

DDR ports (with memory emulation in the tester)

PCI-Express, including Clock/Data Recovery


CPU

DRAM

I/F

Flash

I/F

JTAG

I/F

USB

I/F

DSPBB

Proc

Power Mgmt

FunctionsAudio / BB

Functions GPS

3G

WiFi

FM/TV

DRAM Emulation Engine

DRAM Emulation Engine

JTAG Protocol Engine

DC Test

Resources

AC Test

Resources

Modulation Domain RF




Protocol Synchronization & Communication

USB Protocol Engine

Protocol Aware Powered

ATE


How is PA ATE Different From Traditional ATE?

• Difficult to debug

• Difficult to modify

• Difficult to communicate to

design engineers

• Can’t deal with device behavior

JTAG

Protocol DUT

DDR

Memory

Emulation

Protocol

“Go” Memory

Writes

Memory

Reads “Pass!”

Protocol Aware Powered Tester

Traditional ATE uses bits

and ATE vectors

PA Testing talks to the

device in its native language


A Customer Proof - PA Successes

• 50 to 1 improvement in pattern iterations

Old method required up to 50 pattern executions to find one pass

PA allows this to be done in one shot

Improvement is magnified when using multi-site

• Mission Mode Testing

Impossible to validate without PA

Greatly improves test quality

• Fast Test Bring Up

Days turned into hours

Portability across devices

• Debug greatly enhanced

Design marginalities discovered and debugged quicker

Characterization capabilities created by PA did not exist before

T T

Timing

Host

Computer

FPGA Based

Protocol Engines

“stored

response”

digital

DSSC

Logic

Patgen

Transaction

Memory

Pin

Electronics

UP1600


A Customer Proof - PA Successes

• Using System Level Test (PA) methods enabled 100% correlation with system results on a small number of samples

• System Level Test (PA) Test Time Improved by factor of 4X

• PA Improved Yield – Non PA methods over rejected some parts while missing other marginal parts

“With PA we are able to closely replicate the system environment and

test conditions and quickly bring up and correlate with system results,

at a fraction of the test time, compared to non PA methods”


Conclusions

• A simple hearing and vision test doesn’t come close to testing the full capability of the human brain

• Traditional testing also falls short of testing the “brains” of Complex SOC Mobility devices

• Some really smart “brains” have developed a new model for testing using Protocol Aware Enabled ATE

The Test Model for the Future


감사합니다

http://www.omniglot.com/soundfiles/korean/thanks1_kr.mp3

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The Changing Model For Testing Complex SOC Mobility Devices20 Teradyne Proprietary Information...

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