© Fraunhofer IIS/EAS | COSIDE® - DESIGN ENVIROMENT FOR HETEROGENEOUS SYSTEMS
THE DESIGN ENVIRONMENT FOR HETEROGENEOUS SYSTEMS
COSIDE® Use Cases & Applications
© Fraunhofer IIS/EAS | COSIDE® - DESIGN ENVIROMENT FOR HETEROGENEOUS SYSTEMS
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Consumer
Wired & Wireless Communication Security
Automotive & Safety
Avionics
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Mixed Signal Architecture and System Level Design
Co-Simulation Model Exchange
Regression Testing
Verification Collaboration
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SystemC / SystemC AMS
RCP/HiL Verilog
VHDL
TLM
UVM-SystemC C/C++
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– Creates Virtual prototype
• Easy model definition via XML editor frontend
• SC/SCA Syntax highlighting • Code completion with
suggestions
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– Creates Create model database
• Easy model definition via XML editor frontend
• SC/SCA Syntax highlighting • Code completion with
suggestions
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– Creates Model database – SystemC code generation
DB
Primitive
SC/SCA
Test bench
Doc TB
Documentation
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– Creates Plain SystemC AMS – Simple DC/DC buck converter
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– Creates Plain SystemC AMS – Simple DC/DC buck converter (top-level)
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– Verifies Test bench infrastructure
DB
Simple Generic UVM Interactive workbench
COSIDE® Regression test framework
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– Verifies Simple test bench
Simple test bench
DUT (SystemC)
Stim SystemC
• Apply simple stimulus to a design under test (e.g. sub-system)
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– Verifies Generic test bench
Generic test bench
DUT (SystemC)
Multiple Stim.
(SystemC)
• Apply multiple test cases to a design under test (e.g. top-level)
• Add measurement, connection, injection utilities for each TC
TC-n TC-3 TC-2
TC-1
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– Verifies UVM test bench
UVM harness
DUT (SystemC)
Test (UVM-SystemC)
• Apply UVM structure to a design under test (e.g. top-level)
• Using Scoreboard, Virtual Sequencer, Driver, Monitor, Agents etc.
UV
C2
Ag
ent
Mo
nit
or
VIF
UV
C1
Ag
ent
Dri
ver
VIF
V-Sequencer …
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– Verifies Interactive workbench
Design/Adapt
Control Visualize
Compile & select Traces
Run & Trace
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– Verifies Plain SystemC AMS – Simulation results
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– Verifies Regression test framework
Kill the Bug!
Flexible and user adaptable regression infrastructure.
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– Connects Model database – Co-Simulation interface gen.
DB
Primitive
SC/SCA
Test bench* Coupling
IF Doc TB
Documentation Schematic
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Customer Model Generation
with ensured IP-Protection
Model Exchange with reproducible analogue simulation behavior
Hardware in the Loop (HiL) Simulation with dSPACE, ZedBoard (ARM®)
Tool Couplings for model exchange and implementation level verification
– Connects Co-Simulation framework & Model export
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Tool Couplings for implementation level verification Mentor Questa
Easy to achieve by RMB to entity xml and let COSIDE® do the work
Coupling menu
Questa coupling
Create co-simulation interface
Create VHDL test bench
– Connects Co-Simulation framework – Refinement and implementation
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– Connects Co-Simulation framework – Refinement and implementation (2)
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Tool Couplings for implementation level verification with Cadence AMS Designer
Easy to achieve by RMB to entity xml and let COSIDE® do the work
Coupling menu
AMS Designer (NCSim) coupling
Create co-simulation interface
Create VHDL/Verilog test bench
– Connects Co-Simulation framework – Refinement and implementation (3)
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– Connects Co-Simulation framework – Refinement and implementation (4)
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– Connects Co-Simulation framework – Seamless testing
Concept phase – SystemC virtual prototype
(plain SystemC)
Implementation phase – Reuse of SystemC tests for RTL model regression testing
(Co-Simulation)
Hardware validation phase – Reuse of SystemC tests for FPGA/ASIC regression testing
(COSIDE® @ Lab. – dSPACE, ZedBoard)
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– Connects Co-Simulation framework – Bridge the missing link
DB
Generate initial schematic – contains specified entity
Implementation designer provide module entity
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– Connects Co-Simulation framework – Bridge the missing link (2)
DB
Adding predefined interface modules to match the entity and establish the link between system-level and implementation.
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Tool Couplings for model exchange with Matlab Simulink
Easy to achieve by RMB to entity xml and let COSIDE® do the work
Coupling menu
Simulink coupling
Create co-simulation interface
and a Simulink symbol
– Connects Co-Simulation framework – Customer model
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– Connects Co-Simulation framework – Customer model (2)
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COSIDE® Collaborates
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OEM
tight cooperation
tight cooperation
e.g. automotive value chain
TIER-2
TIER-2
TIER-2
TIER-2
TIER-1
TIER-1
IP protected
– Collaborates IP protected model exchange
source code
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Subversion CVS
Clear Case
Mercurial Design Sync
– Versioned Integrated version management support
GiT
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COSIDE® thanks for your attention!
Questions
Suggestions
Feature requests
Discussions
© Fraunhofer IIS/EAS | COSIDE® - DESIGN ENVIROMENT FOR HETEROGENEOUS SYSTEMS
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Thomas Arndt Application Engineer COSIDE® [email protected] +49-351-4640-743
Fraunhofer Institute for Integrated Circuits IIS Design Automation Division EAS Zeunerstraße 38 01069 Dresden, Germany www.coside.de
THANK YOU FOR YOUR ATTENTION YOUR CONTACT