The Design of the Coincidence The Design of the Coincidence Matrix ASIC of the ATLAS Barrel Matrix ASIC of the ATLAS Barrel
LevelLevel--1 Muon Trigger1 Muon Trigger
LECC 2002 ColmarLECC 2002 Colmar
R. VariR. VariINFN RomaINFN Roma
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Level 1 Barrel Muon Trigger AlgorithmLevel 1 Barrel Muon Trigger AlgorithmSystem based on three System based on three Resistive Plate Chamber Resistive Plate Chamber detector layersdetector layersEach RPC detector is Each RPC detector is composed by a doublet of composed by a doublet of ηη and and φφ stripsstripsA coincidence of two (low A coincidence of two (low ppTT) or three (high ) or three (high ppTT) hits ) hits in different detector layers in different detector layers is required for a valid is required for a valid triggertrigger
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Coincidence Matrix ASIC FunctionalityCoincidence Matrix ASIC FunctionalityThe Coincidence Matrix ASIC performs most of the The Coincidence Matrix ASIC performs most of the functions needed for the lowfunctions needed for the low--ppTT and highand high--ppTT triggers and triggers and for the readfor the read--out of the ATLAS Barrel Level1 Muon out of the ATLAS Barrel Level1 Muon TriggerTriggerTrigger and readout of 192 RPC FE signalsTrigger and readout of 192 RPC FE signalsTiming and digital shaping of the signals coming from the Timing and digital shaping of the signals coming from the RPC doubletsRPC doubletsExecution of the trigger algorithm, local muon track Execution of the trigger algorithm, local muon track candidates identification and candidates identification and ppTT classificationclassificationROI overlap flaggingROI overlap flaggingData storage during Level1 latencyData storage during Level1 latencyStorage of readout data in derandomizing memoryStorage of readout data in derandomizing memoryRPC hit time measurement with 3.125 LSB (1/8 BC)RPC hit time measurement with 3.125 LSB (1/8 BC)Readout data serializerReadout data serializer
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Level 1 Barrel Muon Trigger SchemeLevel 1 Barrel Muon Trigger Scheme
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PAD BoardPAD Board
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PAD BoxPAD Box
CMA eta
CMA phi
PAD logic
Programmable Delay ASICs
ELMB
TTCrx Optical link tx
Colmar, 10/9/2002Colmar, 10/9/2002 R.Vari R.Vari -- INFN RomaINFN Roma 77
Radiation EnvironmentRadiation Environment
SIMULATED RADIATION LEVEL
SRLtid [Gy·10y-1] SRLniel[1 MeV n·cm-2·10y-1]
SRLsee[> 20 MeV h·cm-2·10y-1]
BMF 3.02 2.49·1010 4.69·109
BML 3.04 2.82·1010 5.65·109
BMS 3.03 2.50·1010 4.73·109
BOF 1.19 2.14·1010 4.08·109
BOL 1.33 2.20·1010 4.21·109
BOS 1.26 2.10·1010 4.10·109
RTCRTCtidtid = = SRLSRLtidtid ·· SFSFsimsim ·· SFSFldrldr ·· SFSFlotlot ·· 10y10y ~ 1 ~ 1 kRadkRad (SF=3.5x1x1)(SF=3.5x1x1)SEUSEUff = (soft = (soft SEUSEUmm / ARL) / ARL) ·· ((SRLSRLseesee / 10y) / 10y) ·· SfSfsimsim (SF=5)(SF=5)
SEUSEUmm = the number of measured soft SEU during test.= the number of measured soft SEU during test.ARL = integrated hadrons flux received by the tested component.ARL = integrated hadrons flux received by the tested component.
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CMA ArchitectureCMA Architecture
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CMA LayoutCMA LayoutUMC 0.18 UMC 0.18 µµm, 6 metal m, 6 metal layers, 1.8 V core power layers, 1.8 V core power supply, 3.3 V I/O padssupply, 3.3 V I/O pads430 kgates430 kgatesChip area: 4.5Chip area: 4.5××4.5 mm4.5 mm22
Virtual Silicon standard Virtual Silicon standard cell librarycell library320 MHz PLL (x8) macro320 MHz PLL (x8) macro24 double24 double--port RAMsport RAMs352 pins BGA package352 pins BGA package
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I/O signalsI/O signals
I0[31:0] positive pivot plane 0 / low pt k-pattern XOFF Transmit off input I1[31:0] pivot plane 1 BUSY ASIC busy signal J0[63:0] non-pivot plane 0 SCL I2C clock line J1[63:0] non-pivot plane 1 SDA I2C data line L1ACCEPT L1 Accept signal DEVID[7:0] Device identification input L1CNTRES L1 counter reset TCK TAP SCAN clock BCNTRES BCID counter reset TMS TAP SCAN MODE CLK 40 Mhz TRST TAP SCAN RESET TCLK 10 MHz TDI TAP SCAN IN K[31:0] k-pattern output TDO Tristate TAP SCAN OUT BCID[11:0] Bunch crossing ID counter SE Scan enable signal THR[1:0] Threshold value TST Test enable signal OVL[1:0] Overlap value CLKOUT pll_clk tree output SER_D DS-link Data line CLK160OUT clk_160 tree output SER_S DS-link Strobe line CLR_N Asynchronous clear
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Timing BlockTiming BlockCMA has 3 clock domains, 2 working modesCMA has 3 clock domains, 2 working modesInitialization mode:Initialization mode:
all blocks are driven by the external 40 MHz clockall blocks are driven by the external 40 MHz clockthe PLL is bypassed and the 160 MHz clock divider is the PLL is bypassed and the 160 MHz clock divider is excludedexcludedall registers are accessible as shift registers, driven all registers are accessible as shift registers, driven by the I2C interface.by the I2C interface.
Run mode.Run mode.the PLL is in lock mode, provides the 320 MHz clock, the PLL is in lock mode, provides the 320 MHz clock, and drives the 160 MHz clock generator.and drives the 160 MHz clock generator.
Colmar, 10/9/2002Colmar, 10/9/2002 R.Vari R.Vari -- INFN RomaINFN Roma 1212
Input Pipeline BlockInput Pipeline Block
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
32
32
64
64
INSYNC MASK0 EDGE IPB1-8 deep
PIPELINESHAPE MASK0
MASK0
IPB1-8 deep
IPB1-8 deep
I0_READOUT
I1_READOUT
J0_READOUT
J1_READOUT
32
32
64
64
I0_TRIGGER
I1_TRIGGER
J0_TRIGGER
J1_TRIGGER
I0
I1
J0
J1
FrontFront--end signal digital shaping is programmable in the end signal digital shaping is programmable in the range 1/8range 1/8÷÷1 BC.1 BC.Pipeline delay is programmable in the range 3/8Pipeline delay is programmable in the range 3/8÷÷3 3 BCsBCsFE signal dead time is programmable in the range 0FE signal dead time is programmable in the range 0÷÷4 4 BCsBCs, in steps of 1/8 BC, in steps of 1/8 BC
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Trigger BlockTrigger Block
DE
-CLU
STE
RIN
G
COINCIDENCELOGIC
I0 32
I1
J0 64
J1 64
PR
E-P
RO
CE
SS
ING
32
32
64
64
32
32
64
64
32
I_GE1
I_EQ2
J_GE1
J_EQ2
32
32
32 EDGE
PATTERN 0
PATTERN 1
PATTERN 2
SH
AP
ER
OV
ER
LAP
K_PATTERN_TRIGGER
OVL
EN
CO
DE
R
THRESH32
32
32
READOUTMUX
2 32 K_PATTERN_READOUT
SYNCHRONIZER12
BCID
OVL_READOUT
THRESH_READOUT
2 THRESH_TRIGGER
2 OVL_TRIGGER
12 BCID
2
2
32
2
2
32
32
32
Coincidence logic works at 320 MHzCoincidence logic works at 320 MHzNumber of matrices/thresholds is 3, logic is repeated Number of matrices/thresholds is 3, logic is repeated three times in parallel, one per threshold settingthree times in parallel, one per threshold settingMajority logic is 1/4, 2/4 (one hit per doublet), 3/4, 4/4Majority logic is 1/4, 2/4 (one hit per doublet), 3/4, 4/4The highest threshold kThe highest threshold k--pattern which has a nonpattern which has a non--zero zero trigger information is shaped in time and then sent to the trigger information is shaped in time and then sent to the chip output padschip output pads
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DeDe--clustering + preprocessingclustering + preprocessing
RPC average cluster size is ~1.4RPC average cluster size is ~1.4..DeDe--clustering logic type can be clustering logic type can be selected at CMA initialization.selected at CMA initialization.Max processed cluster size is Max processed cluster size is programmable (up to programmable (up to ±±3).3).
Correlates hits from two Correlates hits from two detector layersdetector layers2/2 hits favoured over 1/2.2/2 hits favoured over 1/2.programmable programmable ηη<0, <0, ηη=0, =0, ηη>0 >0 modes can be selected at modes can be selected at CMA initialization.CMA initialization.
Colmar, 10/9/2002Colmar, 10/9/2002 R.Vari R.Vari -- INFN RomaINFN Roma 1515
Readout BlockReadout Block
LATENCY BUFFER DERANDOMIZER
SE
RIA
LIZ
ER
FIFO1BCC
L1C
CLK40
CLK160 BC
BC160EDGE
L1ID
CLK320
CLK160
L1A
BCR
L1CR
CLK160FIFO1_FLAGS
FIFO1_L1ID
FIFO1_BCID
L1EXECL1DONE
BC160
L1ID
FIFO2
CLK160 FIFO2_FLAGS
FIFO2_L1ID
FIFO2_BCID
FIFO1_BCID
FIFO1_L1ID
FIFO2_WEN
FIFO2_WEN
FIFO2_REN
L1C_WEN
SER_FLAGS
DATA
BC160
TSLICE160
XOFF
SER_WEN
D
S
EMPTY_DER
REN
DATA
FIFO2_BCID
FIFO2_L1ID
SER_WEN
CMID
FIFO2_REN
I0
I1
J0
J1
K
I0_BCID, I1_BCID, J0_BCID, J1_BCID, K_BCID
K_THRESH
K_OVL
L1DONE
L1EXEC
BC
BC160
TSLICE
THRESH
OVL
FIFO1_BCID
FIFO1_L1ID
REN
CLK40
CLK160
CLK320
BUSY
CLK160
BCID
CLK160
I0_L1ID, I1_L1ID, J0_L1ID, J1_L1ID, K_L1ID
I0, I1, J0, J1, K_O
I0_TIN, I1_TIN, J0_TIN, J1_TIN, K_TIN
L1C_WEN
BUSY
CMID
TSLICE160
XOFF
32
32
32
64
64
3
2
2
12
12
12
3
12
9
2
9
3
32
3
2
2
12
9
16
9
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Readout blockReadout blockThe latency buffer stores hit patterns coming from the input FIFThe latency buffer stores hit patterns coming from the input FIFO O until they get olduntil they get oldThe input FIFO buffer is written at 320 MHz and contains the hitThe input FIFO buffer is written at 320 MHz and contains the hitpattern, BCID and time interpolator value. The readout part of tpattern, BCID and time interpolator value. The readout part of this his buffer, together with the rest of the readout logic works at 160buffer, together with the rest of the readout logic works at 160 MHzMHzIn the derandomizer buffer, hits belonging to the same L1ID are In the derandomizer buffer, hits belonging to the same L1ID are assembled in data frameassembled in data frameAll buffer memories are implemented with All buffer memories are implemented with FIFOsFIFOsFIFO1 and FIFO2 contain a list of L1IDs and relative FIFO1 and FIFO2 contain a list of L1IDs and relative BCIDsBCIDsrespectively to be processed by the derandomizer and ready to berespectively to be processed by the derandomizer and ready to besent via the serializersent via the serializerThe serializer block attaches CRC codes to event fragments and The serializer block attaches CRC codes to event fragments and ships the data out, following the DSships the data out, following the DS--link protocol, at a programmable link protocol, at a programmable frequency of 10frequency of 10--80 MHz80 MHz
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SEU detectionSEU detectionOne parity bit is stored when One parity bit is stored when register is initializedregister is initializedRegister parity is checked Register parity is checked against stored parity every against stored parity every clock cycleclock cycleSEU output signal active when SEU output signal active when parity check failsparity check failsSingle Event Upset detection Single Event Upset detection has been implemented for has been implemented for almost all CMA registersalmost all CMA registersFor the fundamental chip For the fundamental chip control registers (Main Control control registers (Main Control Register, Latency Registers, Register, Latency Registers, DSlinkDSlink Register), triple Register), triple redundancy, 2/3 majority, has redundancy, 2/3 majority, has been implemented for error been implemented for error correction.correction.
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TestabilityTestability32+5 serial scan chains, JTAG boundary scan, I2C register access32+5 serial scan chains, JTAG boundary scan, I2C register accessScan chains (including RAM chains) used during ASIC acceptance Scan chains (including RAM chains) used during ASIC acceptance tests:tests:
All core registers and all All core registers and all RAMsRAMs are accessible via scan chainsare accessible via scan chainsDedicated scan chains have been designed for RAM data, addressesDedicated scan chains have been designed for RAM data, addressesand control signals, in order to be able to test the RAM coresand control signals, in order to be able to test the RAM cores
JTAG for tests during board assembly testJTAG for tests during board assembly testI2C is used for register accessibility and test pattern generatiI2C is used for register accessibility and test pattern generation on during trigger operationduring trigger operationInput pipelines can be preloaded with hit patterns and chip can Input pipelines can be preloaded with hit patterns and chip can be be run for a fixed programmed number of cyclesrun for a fixed programmed number of cycles
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Design flowDesign flowVHDL RTL codeVHDL RTL codeVHDL VHDL testbenchestestbenches for all blocks and full chipfor all blocks and full chipDesign exploration synthesisDesign exploration synthesisTopTop--down compile core and timing blocksdown compile core and timing blocksScan chains, JTAG and IO pads insertionScan chains, JTAG and IO pads insertionPlace & routingPlace & routingClock treeClock treeParasitic capacitance extractionParasitic capacitance extractionFinal layoutFinal layout
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CMA LAB TestCMA LAB TestLoadboardLoadboard developed developed for industry Teradyne for industry Teradyne testertesterThe board has been The board has been designed with designed with additional connectors additional connectors for PLL test and lab for PLL test and lab tests in Rometests in Rome
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Test PatternsTest PatternsScan and functional tests were performed on Teradyne Scan and functional tests were performed on Teradyne machine at 1 Mhz, 40 MHz, at room and at 125°C machine at 1 Mhz, 40 MHz, at room and at 125°C temperatures. PLL lock was also tested.temperatures. PLL lock was also tested.
SCAN test: 32 scan chains, maximum of 900 cells (generated SCAN test: 32 scan chains, maximum of 900 cells (generated with Synopsys Test Compiler)with Synopsys Test Compiler)RAM test: using single dedicated scan chain (23,743,440 RAM test: using single dedicated scan chain (23,743,440 cycles), generated from RTL modelcycles), generated from RTL modelFunctional test: 105576 vectors, to test I2C interface and startFunctional test: 105576 vectors, to test I2C interface and startPLL, generated from full netlist+timing simulationPLL, generated from full netlist+timing simulation
86 packages tested by industry:86 packages tested by industry:7 GND fails7 GND fails5 RAM fails5 RAM fails4 SCAN fails4 SCAN fails70 good (70 good (~81%)~81%)No logic fail on functional test!No logic fail on functional test!
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LAB setupLAB setup36x64K T=6.125nsPattern generator
Clock jitter
WaveformAnalyser T=10ns
GeneratorPODs
GPIBLAN
loadboard
I2C on RJ45
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PLL TestPLL Test160 MHz derived clock 160 MHz derived clock output has been used to output has been used to check PLL stability (320 check PLL stability (320 MHz)MHz)PLL has been characterized PLL has been characterized vs V and vs input frequencyvs V and vs input frequencyMeasured jitter: 25 ps rms, Measured jitter: 25 ps rms, 150 ps pk150 ps pk--pkpkPLL works according to PLL works according to specificationsspecifications
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Trigger testTrigger testTrigger test on a limited Trigger test on a limited number of input channels, number of input channels, due to limitations on the due to limitations on the laboratory setuplaboratory setupMinimum pulse width Minimum pulse width measurement:measurement:
TTwminwmin > 6.126 ns (12 ns in > 6.126 ns (12 ns in specs)specs)Dead timer, pulse shaping Dead timer, pulse shaping and pipeline delay working and pipeline delay working according to specs.according to specs.
Trigger output latency:Trigger output latency:Input to KInput to K--pattern delaypattern delay
TTlatkpatlatkpat = (59 = (59 ±± 1) ns1) ns
Input to THR/OVL delayInput to THR/OVL delayTTlatthr latthr = (63= (63÷÷88 88 ±± 1) ns1) ns
Skew between THR and Skew between THR and OVL signals OVL signals
TToutskewoutskew = (2 = (2 ±± 0.5) ns0.5) ns
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Readout testReadout test
CMID L1ID
… BCID + 16-bit hits …
8-bitCRC
Readout tests done at 40 Mbit/s using:Readout tests done at 40 Mbit/s using:10ns period sampling with waveform analyser10ns period sampling with waveform analyserGPIB LAN box connected to waveform analyserGPIB LAN box connected to waveform analyser
VISAVISA--GPIB library (linux) in deserializer program has GPIB library (linux) in deserializer program has been used to convert waveform vectors to readout data been used to convert waveform vectors to readout data fragmentsfragments
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Readout latencyReadout latency
0.00
100.00
200.00
300.00
400.00
500.00
600.00
700.00
800.00
0 2 4 6 8 10 12 14 16 18hits
max
LVL
1 fre
quen
cy (k
Hz) LVl1 max f (kHz) 40Mbit/s
LVl1 max f (kHz) 80Mbit/s
1% RPC occupancy1-BC window
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Power consumptionPower consumptionNominal power Nominal power consumption during consumption during normal run mode normal run mode operation is operation is ~1.2 W
Power consumption vs. voltage
550
600
650
700
750
1.50 1.60 1.70 1.80 1.90
Vdd [V]
I [m
A]
~1.2 W
Power consumption vs. clock frequency
0
100
200
300
400
500
600
700
800
900
2.5 12.5 22.5 32.5 42.5
freq. [MHz]
I [m
A]
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Plans & ConclusionsPlans & Conclusions
Radiation Test:Radiation Test:60 MeV proton SEE test60 MeV proton SEE testGamma TID testGamma TID test
Slice Test:Slice Test:all slice components are now availableall slice components are now available
Test Beam with RPC detectorTest Beam with RPC detectormuon beam with background photon sourcemuon beam with background photon source
No problems or bugs founded up to nowNo problems or bugs founded up to nowNo second ASIC version previewed!No second ASIC version previewed!