Shimote et al.: Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin (1/7)
1. IntroductionFCBGA packages are mainly used in fields where chips
require multiple functions and high-technology, such as
high-end server and network systems. Along with the
strong requirements in these fields for packages to have
high performance and reliability, strong demands for
reduced costs and further miniaturization are also present.
[1–4] To meet the above demands we developed an
FCBGA on which the bumps are Cu pillars. We then
worked to improve its reliability to the high level we
require.
To obtain high-reliability from a package having Cu-pil-
lar bumps, the package design is clearly important. In
order to develop a high-reliability package, we started by
defining the concepts to be considered in the package
design. We then designed the flip-chip bonding (FCB) pro-
cess and the structure of the package.
2. Designing the Package2.1 Concepts for consideration
Difficulties with conventional flip-chip bonding on
organic substrates have arisen in the development of
FCBGA packages for commercial products. The following
items are points that must be considered in designing a
package.
(1) As chip components shrink with evolution through
wafer process generations, the functionality of chips
becomes broader and the number of terminals
increases.
(2) An inexpensive package is generally required for a
product to be competitive.
(3) To simplify the design of an flip-chip (FC) package,
the design of the bump layout should be simpler
and more closely match the IO layout in compari-
son with a typical wire bonding (WB) package.
(4) In terms of electrical performance, assigning the
ground pads to the central area of the chip is helpful
for the integrity of the power system.
We evaluated the FC process design as well as package
design to realize an FCBGA package optimized in terms of
the above four points.
In designing the structure of the package, we (1)
[Technical Paper]
The Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing
NCP Resin, Achieving the High Quality and ReliabilityYoshikazu Shimote*, Toshihiro Iwasaki**, Masaki Watanabe**, Shinji Baba***, and Michitaka Kimura***
*Renesas Semiconductor Package & Test Solutions Co., Ltd., 111, Nishiyokote-cho, Takasaki-shi, Gunma 370-0021, Japan
Transactions of The Japan Institute of Electronics Packaging Vol. 7, No. 1, 2014
selected bumps at a staggered pitch of 30 μm, since this
pitch is sufficiently fine for high density IO signals, (2)
adopted a substrate having a low metal layer to reduce the
number of layers and increase the number of wires, (3)
simplified lines to re-distribute signals from IO pads to
bumps, (4) placed the IO (WB pads) more peripherally
and power and ground bumps in and around the center.
In designing the FCB process, the key points are to
obtain stable connections despite the fine pitch and to
achieve a void-free under-fill. When the conventional form
of connection by solder bumps is applied at a pitch of the
order of 30 μm, solder bridges are often formed between
adjacent bumps, which is obviously a problem for mass
production. However, raising the bump pitch to, for exam-
ple, 150 μm to avoid this problem creates the need to
arrange the bumps in an area array that requires rewiring,
which increases the number of substrate layers and raises
costs. Pitches of the order of 30 μm can be handled by
switching to Au studs as the bumps, but this raises produc-
tion costs. A further problem is that a void-free under-fill is
not easily obtained with the conventional capillary under-
fill technique because some bumps of the area-array will
be placed with narrow gaps away from the periphery.
Therefore, we adopted Cu pillars for the bumps to main-
tain a high quality of bonding in terms of preventing solder
short-circuits and simplifying the design of wiring in the
substrate and of re-distribution lines on the chip. We
applied NCP resin to achieve void-free quality in spite of
the peripheral-and-central layout of bumps and the narrow
gap between the chip’s surface and substrate.
2.2 Package specificationFigure 1 shows external views of the package used in
our experiments, and Table 1 lists the specifications.
The chip has 707 bumps in a peripheral-and-central lay-
out. Each Cu-pillar bump consists of a Cu post topped by
Sn/Ag solder, and is formed by electroplating. The sub-
strate has four metal layers (1-2-1) and electroplated solder
on the pads for connection to the bumps on the chip.
2.3 The flip chip bonding processIn the experiment, we applied a local reflow process
(shown as Fig. 2)[5] for FCB.
Fig. 1 Photograph of the package.
Fig. 2 Local reflow FCB process with NCP.
(A) Pre-heating and alignment (B) Pressing the chip
(D) Cooling(C) Heating(for connecting the bumps and curing the NCP)
BumpChip
SubstrateStage
Bonding head
NCP
Table 1 Specification of the Package.
Chip
Size 7 × 7 mm
Thickness 0.28 mm
Bump pitch Min. 30 μm staggered
Number of bumps 707
Bump specificationCu pillar
+ solder
Bump layoutPeripheral
+ central
Organic Substrate
Size 21 × 21 mm
Thickness 0.60 mm
Number of balls 472
FC pads Solder
Ball pitch 0.80 mm
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Shimote et al.: Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin (3/7)
The sequence of the process is as follows:
(A) Applying NCP to the substrate, heating it and the
chip to a temperature below both the melting point
of the solder and the curing point of the NCP, and
aligning the chip and substrate to be ready for bond-
ing.
(B) Pressing the chip under an appropriate load until
the bumps make contact with the solder on the sub-
strate.
(C) Controlling the height of the bonding head and
heating of the bonding head to a temperature above
the solder melting point.
(D) Final cooling down.
3. Results and Discussions3.1 Evaluating the shape of the solder after FCB
In order to optimize the shape of solder joints after FCB,
we evaluated the shapes under several conditions for the
speed of heating of the bonding heads as shown in Fig. 3.
Table 2 shows the shapes of solder joints produced
under several conditions for the speed of heating the bond-
ing head.
Whereas the solder joints in samples 1 and 2 are smooth
and spheroidal, they are shaped somewhat like snowmen
in samples 3 and 4. This is because the relative timing of
melting the solder and of hardening of the NCP have quite
a strong effect on the shape of the final solder joint. The
condition for smooth spheroidal shapes like sample 1 and
2 is that the solder starts melting before the NCP hardens
and thus relies on the surface tension of the solder, so this
shape is similar to that produced by a local reflow process
in the absence of NCP. On the other hand, when the NCP
hardens before the solder starts melting, the bump shapes
become like those of samples 3 and 4, which are similar to
the characteristic solder shape (Fig. 4) produced when
NCP hardens at a temperature below the solder melting
point with the bonding head being kept in the pre-heated
state instead of being heated up to the melting point or
higher in process (C) in Fig. 2.
Fig. 3 Evaluated bonding head heating speeds.
A
B
Bonding head temperature curve
Bonding head heating speed = BA
320 °C
Time
Bon
ding
hea
d te
mpe
ratu
re
Table 2 Relative values for speed of heating the bonding head and shapes of resulting solder joints.
Sample No.
Speed of heating (relative value)
Solder joint shape
Cross-sectional view
1 1Smooth
spheroidal
Sample No.
Speed of heating
(relative value)
Solder joint shape Cross-sectional view
1 1 Smooth spheroidal
Cu-pillar
NiIntermetallic
compoundSolder
joint
10μm
2 7x10-2 Smooth spheroidal
3 4 x10-2 Snowman
4 2 x10-2 Snowman
2 7 × 10-2 Smooth spheroidal
Sample No.
Speed of heating
(relative value)
Solder joint shape Cross-sectional view
1 1 Smooth spheroidal
Cu-pillar
NiIntermetallic
compoundSolder
joint
10μm
2 7x10-2 Smooth spheroidal
3 4 x10-2 Snowman
4 2 x10-2 Snowman
3 4 × 10-2 Snowman
Sample No.
Speed of heating
(relative value)
Solder joint shape Cross-sectional view
1 1 Smooth spheroidal
Cu-pillar
NiIntermetallic
compoundSolder
joint
10μm
2 7x10-2 Smooth spheroidal
3 4 x10-2 Snowman
4 2 x10-2 Snowman
4 2 × 10-2 Snowman
Sample No.
Speed of heating
(relative value)
Solder joint shape Cross-sectional view
1 1 Smooth spheroidal
Cu-pillar
NiIntermetallic
compoundSolder
joint
10μm
2 7x10-2 Smooth spheroidal
3 4 x10-2 Snowman
4 2 x10-2 Snowman
90
Transactions of The Japan Institute of Electronics Packaging Vol. 7, No. 1, 2014
From the above results, Fig. 5 shows the mechanism
which determines the shapes of the solder joints.
(A) Enlarged view of a Cu-pillar bump prior to contact
between the solder on the chip and on the sub-
strate. The solder is immersed in NCP, which is liq-
uid while the solder is solid.
(B) The solder on the chip comes into contact with that
on the substrate. As in (A), the NCP is liquid but the
solder is solid.
(C_fast) The bonding head is heated to start formation
of the solder connection. In this case, the bonding
head is heated quickly, so the solder melts before
the NCP is cured. At this time, both the solder and
NCP are liquid.
(D_fast) Heating continues at the same level, and the
NCP is cured. At this time, the solder is liquid, but
the NCP is solid.
(E_fast) Finally, the package is cooled, and the solder
also solidifies. The surface tension of the molten
solder determines the final shape, which is smooth
and spheroidal.
(C_slow - E_slow) In contrast, when the rate of heating
speed is low, the NCP is cured before the solder is
melted. The result is a snowman shape for the final
connection.
The smooth spheroidal shape for the solder connections
is more desirable since the wider area of the connection
provides greater reliability and stability for the bonds. We
then proceeded to optimize the height of the joints to fur-
ther improve their reliability.
3.2 Evaluation of solder bump heightTo optimize the height of the solder gap (joint height),
we simulated the effects of the solder gap on reliability
through finite element analysis (FEA).[6–8] Figure 6
shows the model we used in simulation and the target
point of the simulation (point A), which was the location of
the greatest stress in the results of simulation.
In the analysis, we simulated an increase in one cycle of
plastic strain energy (ΔW) of Cu on an Al pad during tem-
perature cycling (-55/125°C) under three conditions for
the height of the solder gap (relative heights: 1.2, 1.9, 3.0).
The results are shown in Table 3: ΔW decreases as the
solder gap forming the connection becomes higher. It is
assumed that the solder affects the relaxation of stress due
to the substrate shrinking with lower temperature, so that
the interconnection model with a higher volume of solder
shows lower strain energy. The results in general indicated
that the height of the solder gaps has a strong effect on
reliability, and specifically that a higher solder gap leads to
a higher reliability for the bump connection.
Our next step was to evaluate the conditions of the FCB
process in terms of productivity in mass-production. We
performed experiments with the FCB process through the Fig. 4 Solder shape when NCP hardens below the solder melting point.
10µm
Fig. 5 The mechanism which determines the shapes of the solder joints.
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Shimote et al.: Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin (5/7)
process flow shown in Fig. 7.
We started by preparing samples for several solder
heights (1). The total solder height in Fig. 7 is the sum of
the height of the solder on the chip that on the substrate.
Next, (2) we proceeded with FCB of the samples. The key
parameter for FCB is the height of the bonding head, since
this affects the solder gap. The peak bonding-head tem-
perature is 320°C, and this temperature is applied for sev-
eral seconds. Finally, (3) we confirmed the states of the
connections made in step (2) in terms of open- and short-
circuit failures by taking cross-sections of the solder joints
and X-ray observation. In this evaluation, we observed
about 160 bumps per sample. The results are shown in
Fig. 8.
The horizontal axis shows the total height of solder
between the chip and substrate, and the vertical axis
shows the height of the bonding head. “O” means that the
connections looked good, while “X” means that they did
not.
The vertical-line area is the region where the solder
Fig. 6 Outline of simulation model.
Fig. 7 Flow of evaluation.
(1). Prepare samples for several solder heights(total solder height = Hc + Hs)
(2). FCB< Parameters >Peak bonding-head temperature: 320Height of bonding head (solder gap)
(3). Check for open- and short-circuit failures in the connections
Cross-sectionalX-ray observation
°C
Table 3 Results of simulating plastic strain energy (ΔW).
Simulation modelSimulation model
Solder gap (relative value) 2.1 9.1 0.3
ΔW (relative value) 50.1+ 30.1+ 00.1+
Simulation model
Solder gap (relative value) 2.1 9.1 0.3
ΔW (relative value) 50.1+ 30.1+ 00.1+
Simulation model
Solder gap (relative value) 2.1 9.1 0.3
ΔW (relative value) 50.1+ 30.1+ 00.1+
Solder gap (relative value)
1.2 1.9 3.0
ΔW (relative value) +1.05 +1.03 +1.00
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Transactions of The Japan Institute of Electronics Packaging Vol. 7, No. 1, 2014
joints are too close to each other or bridges are formed
between them. The horizontal-line area is the region
where open-circuit failures appear in the connections.
From the results shown in Fig. 8, solder height of
around 5.0 (relative value) corresponds to the widest
range of the bonding height condition that should maxi-
mize the margin of the process against open- and short-cir-
cuit failures.
3.3 Checking quality and testing reliabilityWe confirmed the quality of the package, especially at
the points of connections, by X-ray, scanning acoustic
microscope (SAM), and cross-sectional checking before
and after the reliability tests. Figure 9 shows the result of
an X-ray check, and no abnormalities can be seen.
Figure 10 shows the result of SAM observation, indicat-
ing an absence of voids.
Figure 11 is a cross-sectional view of two connections.
The bumps have the desired smooth spheroidal shape.
We tested reliability by running the following four tests,
with pre-treatment of 192 h at 30°C and 70% RH plus three
rounds of reflow processing with a maximum peak tem-
perature of 267°C: a high-temperature storage life test
(HTSL, 1,000 h at 150°C), a temperature cycling test (TC,
1,000 cycles between -55 and 125°C), a temperature
humidity-bias test (THB, 1,000 h at 85°C and 85% RH), and
an unbiased highly accelerated stress test (UHAST, 100 h
at 130°C and 85% RH). The results are shown in Table 4.
All tested devices passed the corresponding tests.
4. ConclusionWe have developed a high-reliability package with Cu-
pillar bumps and a local reflow process utilizing NCP resin
which testing showed to be a robust design. The package
and process are now in use in actual mass production. In
Fig. 8 FCB results dependence on the total height of solder and height of bonding head.
X: Bad bond
Partly open connection
O: Good bondBonds are too close
7.06.05.04.03.02.01.00
7.0
6.0
5.0
4.0
3.0
2.0
1.0Open area
Widest range
Short area
OK
Total height of solder (relative value)
Hei
ght o
f bon
ding
hea
d (re
lativ
e va
lue)
60µm
Fig. 9 Photograph of X-ray (four corners of the chip).
500 µm
Fig. 10 Photograph by SAM (four corners of the chip).
500µm
Fig. 11 Photograph of cross-section.
10µm
Table 4 Results for package reliability.
Item Result
HTSL (1,000 h at 150°C)
22 pcs tested, 22 pcs passed
TC (1,000 cycles between -55 and 125°C)
45 pcs tested, 45 pcs passed
THB (1,000 h at 85°C and 85% RH)
22 pcs tested, 22 pcs passed
UHAST (100 h at 130°C and 85% RH)
22 pcs tested, 22 pcs passed
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Shimote et al.: Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin (7/7)
the development process we defined the concept of the
package as a whole, corresponding to the structural
design of the package and the design of the FCB process.
In obtaining the conditions for the FCB process to produce
solder bumps having a shape appropriate for high quality,
we considered the timing in the FCB process of both the
solder melting and the NCP hardening, and the dimen-
sions in making the connections, the latter through the
results of FEA simulation and precise experiments.
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Yoshikazu Shimote received the degree of M.S. in applied chemistry from Kyushu Institute of Technology in 2008. He has been engaged in the development of flip-chip-bonding technologies and under-fill technologies for FC-BGA packages.
Toshihiro Iwasaki received the degree of M.E. in manufacturing science and engineer-ing from Osaka University, Osaka, Japan, in 1993. He joined the Mitsubishi Electric Cor-poration in 1993 and since then he has been engaged in the development of LSI packag-ing and IC assembly technologies. He trans-
ferred to Renesas Technology Corporation and Renesas Electron-ics Corporation in 2003 and 2010, respectively. In 2014, he joined J-Devices Semiconductor Corporation and is presently in the Advanced Technology Group of Package Development Depart-ment at J-Devices Corporation.
Masaki Watanabe received the degree of M. S. in electrical engineering from Kyushu University, Fukuoka, Japan, in 1993. He joined the Mitsubishi Electric Corporation in 1993 and since then he has been engaged in design of LSI package. He transferred to Renesas Technology Corporation and then
Renesas Electronics Corporation. In 2014, he joined J-Devices Semiconductor Corporation and is currently in the Design Department at J-Devices Corporation.
Shinji Baba received the degree of M.E. in precision machine engineering from Osaka University, Osaka, Japan, in 1989. He joined the Mitsubishi Electric Corpora-tion in 1989, where his work included research and development related to pack-age design and technology of Flip-chip
assembly. He is presently the Section Manager of the System Assembly Solution Department at Renesas Electronics Corporation.
Michitaka Kimura received the degree of M. E. in mechanical engineering from Okayama University, Okayama, Japan, in 1984. He joined the Mitsubishi Electric Cor-poration in 1984 and since then he had been engaged in the development of LSI package and of assembly process, especially for
Stacked CSP and Flipchip technologies. He transferred to Rene-sas Technology Corporation and then Renesas Electronics Corpo-ration.
