742 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 3, MARCH 1992

.05 .075 .1 .125 .15 ,175 .2 225 .25 ,275 .3 ,325 ChanrwlknOlh(mlcronr)

Fig. 1. A comparison of the overshoot factor F,, of the new analytical model with experimental data at T = 300 K.

channel length estimates given in [8] were used. The fit shown in Fig. 1 is for y = 4 X lo-’’ cm2/V. Good agreement is observed between the data derived from the results of [8] and the analytical calculations. The fitted value of the overshoot parameter is similar to values suggested by the physically based results for silicon cal- culated previously [SI, [6].

IV. DISCUSSION AND CONCLUSIONS

The new theory inherits the limitations of charge control analysis and the generalized augmented drift-diffusion charge transport model. However, the comparisons with experimental data suggest that the theory captures the main features of the influence of ve- locity overshoot on drain currents for silicon transistors over a use- ful range of feature sizes.

The qualitative insights obtained from the new theory are useful in their own right. For practical parameter values, the fractional increase in drain current due to velocity overshoot is directly pro- portional to the overshoot parameter y and the drain voltage Vd, and inversely proportional to the square of the channel length. These dependencies can serve as useful rules of thumb for predict- ing the consequences of scaling or the use of alternative materials.

The theory provides a simple way of adding velocity overshoot effects into semi-empirical circuit models. Improved device models of submicrometer field-effect transistors can be developed for use in circuit simulators such as SPICE. First-order design and opti- mization of transistors for operation at microwave and millimeter- wave frequencies may also be performed, taking into account the beneficial effect of overshoot on transconductance, and the dele- terious effect of overshoot on output conductance. Work is under way to improve silicon and SiGe bipolar transistor models, by ac- counting for the velocity overshoot of minority camers in base re- gions with built-in fields and velocity overshoot in the collector region.

In conclusion, an analytic theory of the impact of velocity overshoot on the drain current characteristics of field-effect tran- sistors has been developed. The utility of the new theory has been demonstrated in a comparison with measured data for MOS tran- sistors with a range of submicrometer gate lengths. Important ap- plications of the new theory are improved device models for use in circuit simulation, and first-order design and optimization of mi- crowave and millimeter-wave transistors.

ACKNOWLEDGMENT

The authors wish to acknowledge useful discussions with Prof. C. Maziar and X.-L. Wang of the Microelectronics Research Cen- ter of the University of Texas at Austin, and with T. Hamilton and Dr. M. Orlowski of Motorola APRDL.

REFERENCES

[l] R. K. Cook and J . Frey, “Two-dimensional numerical simulation of energy transport effects in Si and GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. ED-29, pp. 970-977, 1982.

[2] A. Forghieri, R. Guerrieri, P. Ciampolini, A. Gnudi, M. Rudan, and G. Baccarani, “A new discretization strategy of the semiconductor equations comprising momentum and energy balance.” IEEE Trans. Computer-Aided Des. , vol. 7, pp. 231-242, 1988.

[3] S. E. Laux, M. V. Fischetti, and D. J . Frank, “Monte Carlo analysis of semiconductor devices: The DAMOCLES program,” IBM J. Res. Devel., vol. 34, pp. 466-494, 1990.

[4] E. Sangiorgi, B. Riccb, and F. Venturi, “MOS2: An efficient Monte Carlo simulator for MOS devices,” IEEE Trans. Computer-Aided Des. , vol. 7, pp. 259-271, 1988.

[5 ] P. A. Blakey, X.-L. Wang, C. M. Maziar, and P. A. Sandborn, “A new technique for including overshoot phenomena in conventional drift- diffusion simulators,’’ in Computational Elecrronics: Semiconductor Transport and Device Simulation, K. Hess, J. P. Leburton, and U. Ravaioli, Eds.

[6] P. A. Blakey, C. M. Maziar, and X.-L. Wang, “A generalized for- mulation of augmented drift-diffusion for use in semiconductor device modeling,” to be submitted for publication.

[7] B. T. Murphy, “Unified field-effect transistor theory including veloc- ity saturation,” IEEE J. Solid-Stare Circuits, vol. SC-15, pp. 325- 327, 1980.

[8] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. A. Rishton, E. Ganin, T. H. P. Chang, and R. H. Dennard, “Experimental technol- ogy and performance of 0.1 pm gate-length FETs operated at liquid nitrogen temperature,’’ IBM J. ResmDevel., vol. 34, pp. 452-464, 1990.

Boston, MA: Kluwer, 1991, pp. 51-54.

The Off set Voltage of Heterojunction Bipolar Transistors Using Two-Dimensional Numerical Simulation with Current Boundary Condition

L. L. Liou, J. Ebel, and C. I. Huang

Akfracf-The offset voltage of an emitter-mesa AIGaAs/GaAs het- erojunction bipolar transistor was obtained from the transistor’s cur- rent-voltage Characteristics calculated using a two-dimensional nu- merical simulation with a current boundary condition at the base contact. The results show that the offset voltage strongly depends on the position of the emitter-base p-n junction and on the width of the emitter mesa.

I. INTRODUCTION

Heterojunction bipolar transistors (HBT’s) have been proven to be significant devices for high-power, high-frequency microwave

Manuscript received April 23, 1991; revised July 29, 1991. The review

The authors are with the Solid State Electronics Directorate, Wright Lab-

IEEE Log Number 9105361.

of this brief was arranged by Associate Editor S. E. Laux.

oratory, Wright-Patterson Air Force Base, OH 45433-6543.

U.S. Government work not protected by U.S. copyright

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 3, MARCH 1992

and high-speed digital applications. However, the asymmetry of the emitter-base and collector-base junctions introduces an offset voltage. Below this voltage in the current-voltage (I-V ) relation of the HBT, the collector current flows in the opposite direction of the saturation current. The offset voltage is an undesirable feature since it causes extra power consumption and reduced logic swing under active transistor operation. The origin of the offset voltage has been investigated in several studies [1]-[6]. Most of these stud- ies use the Ebers-Moll equivalent circuit model. With the circuit emphasis of this model, the offset voltage is explained by the dif- ference in tum-on voltages between the emitter-base and collector- base junctions together with extrinsic effects such as emitter/col- lector area ratio and parasitic resistance.

There has been little study of the offset voltage using numerical simulation. The reason may be that the commonly used voltage boundary condition is not suitable for obtaining I-V transistor char- acteristics. Using a current boundary condition at the base contact, the I-V characteristics can be calculated with base current as a pa- rameter [ 7 ] , [8], and the offset voltage can be directly obtained.

To demonstrate this calculation, emitter-mesa AlGaAs /GaAs n-p-n HBT’s with different emitter width and different p-n junction position between the emitter and base were simulated. The transis- tor characteristics and the dependence of the offset voltage on the emitter width and the position of the emitter-base p-n junction were shown. These offset voltage dependence results were similar to those obtained using equivalent circuit models.

11. CALCULATION

Our calculations were derived from numerical solutions of the coupled Poisson’s and electron and hole continuity equations. Tak- ing advantage of the spatial symmetry, only half of the emitter- mesa HBT structure, as shown in Fig. 1, was simulated, using a fixed-current boundary condition on the base contact and fixed- voltage boundary conditions on the emitter and collector contacts. A finite difference numerical scheme was used in spatial discreti- zation. The electron and hole current densities between two adja- cent points were calculated based on the Scharfetter-Gummel expressions [9] where the electrostatic potential, electron affinity, and equivalent densities of state in the conduction and valence bands are functions of position. The Shockley-Read-Hall model with electron and hole lifetimes of 1 ns was used for the bulk gen- eration-recombination mechanism and a surface current at the GaAs free surface due to a recombination velocity of lo6 cm/s was also implemented. Fermi-Dirac statistics were used to calculate elec- tron and hole densities.

111. RESULTS A N D DISCUSSIONS

For the simulated HBT structures, a half-Gaussian profile of the p-type dopant from the base toward the emitter with a variance of U was assumed. The p-n junction is thus a distance A x = a(2 In Nb/NC)”’ away from the base edge of the HBT toward the emitter, where N b and Ne are the base and emitter doping densities. The structural parameters of the HBT with U = 0 are listed in Fig. 1. The calculated results of the collector and base current densities as functioas of VbC are shown in Fig. 2 for HBT’s with a = 0, 100, y d 200 A and an emitter width of 1 pm. The HBT with U = 100 A , which corresponds to the p-n junction being in the grading layer ( A x = 245 A) , has a larger current gain than the HBT with U = 0. Similar results were obtained and discussed in [lo]. The HBT with U = 200 A , which corresponds to the p-n

0.25 urn w/2 . .

AlAs Composition Em’tter ‘Ontact (Mole Fraction)

’ - 0 - 0

Doping (/cm3)

5 X 10” 5 x 1017

1 x 10’9

- - -

n Collector 1 x 1017

1 - O n + Subcollector 5 x 1018 I- O

743

Thic5ness

1700 300 50

1000

3000

(A)

5000

Collector Contact Fig. 1, The structural parameters of one half of the device simulated.

Base - Emitter Voltage, Vbe (Volts) Fig. 2. The base and collector currents as a function of base-emitter volt- age with a collector-emitter voltage of 2.0 V for the HBT structures with a variance o = 0 ( 0 ) . 100 (A), and 200 A (m) of the half-Gaussian p-type base doping profile at emitter-base junction.

junction being in the wide-bandgap emitter ( A x = 490 A) , re- quires an increase in v),, of 200 mV to haye the same operating current levels as the HBT with U = 100 A . This result agrees qualitatively with the 1 mV increase of Vb, per 1 A p-n junction movement (presumably due to the base dopant outdiffusion) ob- tained in a reliability study for a similar structure with beryllium base doping [ 1 11.

The calculated transistor I-V curves for the HBT with a = 200 A and an emitter width of 1 pm are shown in Fig. 3. Since the base doping density is much higher than that of the collector, a small base modulation is expected. An expanded view of the offset region is also shown. The offset voltage decreases slightly as the base current increases, which is an intrinsic property determined by the I-V characteristics of both the emitter-base and collector- base junctions. This trend may be reversed in experimental data by the correction term of &Ib, where R, is the parasitic resistance in the emitter which is not included in this calculation.

The variation of the offset voltage at I), = 20 A / m as a function of U is shown in Fig. 4 for the HBT’s with three different emitter widths, W = 0.2, 1.0, and 5.0 Fm, and the other dimensions re- maining the same. The offset voltage stays low until the p-n junc- tion position is beyond the mid-grading layer, and saturates at a high value when the p-n junction position is in the wide-bandgap emitter region. The analytical study [6] shows that the most im- portant intrinsic contribution for the offset voltage in single het- erojunction bipolar transistor is the effective conduction band spike

- 900

$ 700 - s 600 -

- E 800 - -

fl

“ “ “ “ -

Collector - Emitter Voltage, Vce (Volts)

Fig. 3. Calculated collector current versus collector-emitter voltage for the HBT with W = 1 pm and U = 200 A as the base current varies from I O to 50 A/m with I O A/m per step.

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39, NO. 3, MARCH 1992

400

300 - 0

- 3 2 200 6

-

100

50 100 150 200 250 300 d50 400

Variance in Half - Gaussian Prokle (A)

Fig. 4. The offset voltage as a function of the Gaussian variance U for the HBT structures with emitter width W = 0.2 (A), 1.0 ( O ) , 5.0 pm (U).

at the heterojunction. The low offset voltage (less than 0.13 V for the HBT’s with U < 100 A ) shown in Fig. 4 is mainly caused by the reduction of the effective spike due to the grading and the spacer layers at the emitter-base heterojunction.

Recent experimental data [12] of a Be-doped base HBT with a slightly different structure (base doping density is 4 x lOI9/cm3) having operated in an ambient temperature of 360°C for 2 h show a significant increase of the offset voltage from 0.25 to 0.53 V at room temperature. Depending on the power input and the thermal resistance of the measured device, the emitter-base junction may be at a significantly higher temperature than the ambient. Although the reason for the initial high offset voltage is not known, the 0.28 V increase of the offset voltage may be explained by the emitter- base p-n junction shift toward the emitter due to the Be outdiffu- sion.

Q.2 d.4 d.6 d.8 1’ 1’.2 1:4 1.6 1:s 2 2.2 2.4 Y (microns)

Fig. 5 . The calculated current distribution for the HBT with W = 1 pm, U = 200 A , and I,, = 20 A/m operated at the offset voltage of the collec- tor-emitter voltage. The magnitude is indicated by the gray tone.

The simylation result of the current distribution for the HBT with U = 200 A , W = 1 pm, and Zb = 20 A / m operating at the offset voltage is shown in Fig. 5. A normal transistor current flows from the collector to the emitter beneath the emitter mesa. This current is balanced by the forward current flowing from the base to the collector, and results in zero net collector current. An HBT with a smaller W requires a smaller forward bias applied at the base-col- lector junction to compensate for the normal transistor current un- der the emitter mesa, and as a result, the offset voltage increases as W decreases. The dependence of the offset voltage on W indi- cates a collector-to-emitter area ratio contribution, which is very close to ( k T / q ) In(A,/A,), where k T / q is the thermal voltage, A, and A, are the collector and emitter area, respectively. This quan- tity is also suggested by the equivalent circuit model [ 2 ] , [6].

In conclusion, we have obtained the offset voltage from the dc characteristics of HBT using two-dimensional numerical simula- tion with a current boundary condition. The offset voltage is shown to depend on the position of the emitter-base p-n junction and the emitter width. These results agree with those using analytical ap- proach.

REF ER EN c E s

[ I ] T. Won, S . Iyer, S . Agarwala, and H. Morkos, “Collector offset voltage of heterojunction bipolar transistor grown by molecular beam epitaxy,” IEEE Electron Device Lett., vol. IO , pp. 274-216, 1989.

[2] N. Chand, R. Fischer, and H. Morkos,, “Collector-emitter offset voltage in AIGaAs/GaAs heterojunction bipolar transistor,” Appl. Phys. Left., vol. 47, pp. 313-315, 1985.

[3] S.X. Lee, J.-N. Kau, and H.-H. Lin, “Origin of high offset voltage in an AlGaAs/GaAs heterojunction bipolar transistor,” Appl. Phys Lett.,vol.45,pp. 1114-1116, 1984.

[4] J . R. Hayes, F. Capasso, R . J . Malik, A. C. Gossard, and W. Wieg- mann, “Optimum emitter grading for heterojunction bipolar transis- tors,” Appl. Phys. Lett., vol. 43, pp. 949-951, 1983.

[ 5 ] M. E. Hafizi, C. R. Crowell, and M. E. Grupen, “The dc character- istics of GaAs IAIGaAs heterojunction bipolar transistors with appli- cation to de\ IC. modeling,” IEEE Trans. Electron Devices, vol. 37,

[6] B. Mazhari, G. B. Gao, and H. Morkos, “Collector-emitteroffset volt- pp. 2121-2129, 1990.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 3, MARCH 1992 745

age in heterojunction bipolar transistors,’’ Solid-State Electron., vol.

[7] L. L. Liou and C. I . Huang, “Using constant base current as a bound- ary condition for one-dimensional AIGaAs/GaAs heterojunction bi- polar transistor simulation,” Electron. Lett., vol. 26, pp. 1501-1503, 1990.

[8] L. L. Liou, J. Ebel, and C. I . Huang, “DC transistor characteristics of mesa-etched-emitter heterojunction bipolar transistor using two di- mensional simulation with current boundary condition,” in Proc. NA- SECODE VII . Boulder, CO: Front Range Press, 1991, pp. 241-242.

[9] S . Selberherr, Analysis and Simularion of Semiconductor Devices. Wien, New York: Springer-Verlag. 1984.

[IO] M. E. Hafizi, C. R. Crowell, L. M . Pawlowicz, and M . E. Kim, “Improved current gain and fT through doping profile selection in lin- ear graded heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 37, pp. 1779-1788, 1990.

[ I 11 M. F. Chang, private communication, 1991. [I21 M . E. Cheney, private communication, 1991.

34, pp. 315-321, 1991.

Digital GaAs FET versus Si FET Gate Delay as Predicted from the Electron Velocity

David E. Fulkerson

Abstract-This brief constructs a FET model that takes into account the effective saturation velocity (including the effect of velocity over- shoot), fringing capacitance, and source resistance. The model is ap- plied to identical differential source-coupled FET logic gates in both GaAs and Si. The simulated gate delay of the Si logic gate is about 2.6 times that of the GaAs gate, thus refuting the common hypothesis that GaAs and Si delays should be about equal because their equilibrium saturated electron velocities are about equal.

I. INTRODUCTION

Fig. 1 shows the electron velocity versus electric field curves for pure GaAs and Si [ l , p. 461. If we apply 1 V across a channel with a length of 0.6 pm, the average electric field is 1 V/0.6 pm = 16.7 kV/cm. From Fig. 1, the GaAs and Si electron velocities at this field are nearly equal, so it is tempting to conclude that the switching speeds of GaAs and Si FET’s should be nearly equal [2]. The main purpose of this brief is to show why this conclusion is not valid and to derive a more accurate comparison of the speed of GaAs versus Si.

The fallacy in the above argument for equal speeds is the as- sumption that the only significant electron transport mechanism in a GaAs FET is the electron drift velocity, i.e., diffusion current and electron velocity overshoot are negligible. However, GaAs FET’s form an electron dipole layer that sustains the current by an accumulation of electrons and by the diffusion current due to the gradient of electrons [ l , pp. 338-3401. The effect of electron ve- locity overshoot increases GaAs speed even further [l], [3]-[6]. A GaAs transistor behaves as if the velocity followed the constant mobility curve up to an effective elective velocity that is higher than the peak velocity of Fig. 1, and then remains constant [5], [61.

Manuscript received January 4, 1991; revised October 23, 1991. The review of this brief was arranged by Associate Editor M . Shur.

The author is with Honeywell Systems and Research Center, M/S MN09/ A I 10, Bloomington, MN 55420.

IEEE Log Number 9105362.

z X lo7

0 10 - 20 30 40

Electric Field (kV/Cm)

Fig. 1. Electron velocity versus electric field in pure bulk GaAs and Si.

11. THE EFFECTIVE SATURATION VELOCITY OF GaAs VERSUS

Si

By modeling of GaAs FET’s and comparing the results to actual devices, this brief and others (51-[7] show that the effective satu- rated electron velocity vs is about 2.2 X IO’ cm/s for a 0.6-pm gate length. Because of velocity overshoot, this velocity is even higher than the peak velocity of pure GaAs in Fig. 1. On the other hand, the saturation velocity for Si is about 0.8 X IO7 cm/s [8]. The ratio of the effective saturation velocities for GaAs and Si with 0.6-pm gate lengths is therefore

tlJGaAs 2.2 x io7 0.8 x 10’

2.8. -=-=

111. A LARGE-SIGNAL FET MODEL

A simple large-signal saturated transistor model for a 5 pm X

0.6 pm Heterostructure Insulated Gate FET (HIGFET) is shown in Fig. 2 . A 5-pm gate width was chosen because this transistor size is required in a logic gate that will be described later in this brief. This logic gate has all of its transistors biased in the active (“sat- urated”) region of operation, so the drain resistance has virtually no effect on the gate delay; therefore, the drain resistance is left out of Fig. 2 .

The gate capacitance is broken up into two parts in Fig. 2 . Cc, is the intrinsic gate capacitance as, for example, would be calcu- lated from CG, = d / d , where E is the average gate dielectric con- stant, d is the gate dielectric thickness, and A is the area of the channel. In addition to C,, we also must have a “fringing capaci- tance” C, for both gate-to-source and gate-to-drain [9 ] , [IO]. This fringing capacitance is comprised of metal-to-metal capacitance and metal-to-implant capacitance. Our measurements show that, since the transistor is pinched off near the drain, nearly all of the intrinsic gate capacitance can be lumped into the gate-to-source capaci- tance.

The value of CG, in Fig. 2 corresponds to a total dielectric thick- ness of 40 nm and an average relative dielectric constant of 12. In addition to the intrinsic gate capacitance, the model includes gate- to-source and gate-to-drain fringing capacitance of 0.2 fF /pm. The capacitances were experimentally determined by s-parameter mea-

-

0018-9383/92$03.00 0 1992 IEEE