FEE 2016
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The Readout ASIC for the DSSC Detector
for the European XFEL
Florian Erdinger, Heidelberg University
for the DSSC ASIC design groups
C. Fiorini3, P. Fischer1, A.Grande3, K. Hansen2, P. Kalavakuru2, M. Kirchgessner1,M. Manghisoni4, M. Porro5, C. Reckleben2, J. Soldat1, J. Szymanski2
(Heidelberg Univ.1, DESY2, Politecnico di Milano3,
Univ. de Bergamo4, European XFEL GmbH 5)
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Novel Detectors for the European XFEL
● European XFEL in Hamburg
will provide X-ray bursts
● Photon Energy: 0.25 … 15 keV
● → XFEL has initiated 3
development projects: LPD,
AGIPD, DSSC
Key Requirements for DSSC:
• Detect single low energy photons ( 0.25 keV → 70 e-h+ pairs in Si)
• Detect up to 104 photons with resolution better than Poisson limit
• 4.5 MHz … 1 MHz bunch rate
• Possibility to process 500 pulses in each burst
Novel 2D detectors required!
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System Overview
● Focal Plane Composition:
1024 x 1024 pixels
4 equal quadrants
32 monolithic sensors
(256 x 128 pixels)
8 readout ASICs per sensor
● The system can be mounted with
two sensor types:
Mini SDD
Full camera by end of 2017
DEPFET with signal
compression
Full camera will to follow
M. Porro et al. “Development of the DEPFET Sensor with
Signal Compression: a Large Format X-ray Imager with
Mega-Frame Readout Capability for the European
XFEL”, IEEE TNS, vol. 59-6, Dec. 2012
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Mini SDD Motivation
● DSSC – DEPFET Sensor with Signal Compression
Ultimate goal is a DEPFET APS based system
● However: a sufficient number of DEPFET sensors will not be
available for “day 0” operation @ XFEL
● The sensor production has a long turn around time and a second run
is needed, an industrial process is currently being established
parallel track with a passive Mini SDD
(Silicon Drift Detector)
no amplification, no compression on sensor level
an additional front-end is needed in the ASIC
● This situation evolved when the F1 ASIC (first full format prototype)
was basically finished
Only a very simple front-end was added in F1
● The Mini SDD system
● will have reduced performance wrt the DEPFET
● allows to develop the full system in advance
● also covers a large range of experiments @ EuEXFEL
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The ASIC Design Team
Collaborating Institutes:
● Politecnico di Milano:
● Front End Design
● Filter Design
● Universita di Bergamo:
● Pixel Injection Circuit
● LVDS Pads
● DESY Hamburg:
● ADC Design
● Heidelberg University
● Front End Design
● In-pixel Memory
● Chip Control
● Pixel & Chip Integration
● Process: IBM (now GF) 130nm, C4
15mm
4096 Pixels
IO and Control
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The DSSC Pixel Processing Chain
ASICPixel
Sensor Pixel
Two sensor variants:
● DEPFET achieves lower noise and comprises
signal compression but available later
● Mini-SDD type sensor for Day 0 operation
Front End● Mini-SDD sensor requires on-chip
amplification & compression
Filter● Flip Capacitor Filter for low noise, trapezoidal
weighting function, gain setting
ADC● 4.5MHz frame rate in-pixel single slope ADC
(8-9bit depending on frame rate)
Digital Memory
● Digital storage (800 words), readout in ~99ms
XFEL gaps
● XFEL Clock & Control sends VETO signals, on-chip
implementation of fixed latency VETO mechanism
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● 1mW per ASIC pixel ~4W per chip during BURST
● low duty cycle (~1/100ms)
power cycling
Only VDDD stays on permanently
(needed for readout during in XFEL gaps)
ASIC Operation & Power Cycling
Pipelined operation
Maximum time for
filtering and digitization
Memory has virtually
no timing constraints
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Peripheral Circuits
64x64 pixels
13mm long pixel columnsVoltage drop
Row wise referencestrack column voltage drop
● Per column Gray counters &
TX for the in-pixel ADC
● 14 bit DAC for ADC calibration
● Front end injection DACs
● Temperature measurement
circuit
● On-chip digital control block
● 58 total power pads
● 4 LVDS pads
● 5 CMOS pads
● Monitor Pad
● IO & Power can only be placed at the bottom due to sensor geometry
(2x8 ASICs per sensor)
● We have under estimated the (static) horizontal voltage drops in F1
For the next chip generation, a simpler reference will be put in each
pixel
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ASIC Interface & On-Chip Control
● The ASIC has very few control signals (all signals are shown!):
700MHz clock (LVDS)(needed by ADC)
Telegramclk/data (LVDS)
JTAG(slow control)
Monitor
Serial Data(350 Mbps)
Global ChipControl
4096 Pixels
Clock Divider
Dimensions not to scale
Telegram Decoder
Main FSM
Memory Controller
Front End Control
Readout Control& Serializer
Main FSM
controlled
by telegrams
Programmable
Sequencer
(700MHz)
Veto Mechanism
Reset
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Pixel Architecture
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Readout Modes: DEPFET
DEPFET with intrinsic
signal compression
FE Filter ADC RAM
● Photons are collected in the
internal gate (IG) of the DEPFET
● Low Cin (60fF) for first photons
● Cin enlarges for larger signals
● Very well shielded
● Input signal to the ASIC is a current
● Cascode to improve virtual ground imp.
● Linear signal processing in the ASIC
● Prelim ENC estimate: 26el. rms
@ 1keV and 4.5MHz
G. Lutz et al. “DEPFET sensor with intrinsic
signal compression developed for use at the
XFEL free electron laser radiation source”,
NIM, vol. 624, pp. 528-532, 2010
IG
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Bias Current Cancellation
IProg: bias current cancellation
is fine tuned through closed
loop configuration
FE Filter ADC RAM
Coarse setting
Analog fine tuning,
digitized and stored in the pixel
memory for each for burst
20us
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Readout Modes: Mini SDD
DEPFET branch
Switched off
FE Filter ADC RAM
On chip amplification
and “Triode Compression”
Global reset voltage for bias,
Buffer & switch to clear signal
● On chip transistor for direct UI
● Large gm required (>1mS) to overcome
larger Cin of 300f-500f
● Prelim ENC estimate: 72el. rms
@ 1keV and 4.5MHz
● Same bias cancellation
mechanism as for the DEPFET readout is used
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Triode Compression
optimum bias point
largest gm
(for single
photon
detection)
region of operation
Basic principle:
● Signal increases the current and hence the voltage across the resistor
Gain transistor is pushed into the triode region and loses gm
FE Filter ADC RAM
C. Fiorini et al. “A simple technique for
signal compression in high dynamic range,
high speed X-ray pixel detectors”, IEEE
TNS, vol. 61-5, Oct. 2014
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Pixel Circuits: Front End & Filter FE Filter ADC RAM
DEPFET / SDD Clear Signal SettlingBaseline + Signal
Integration
BaselineIntegration
XFEL Pulse / Flip of Cf
Sensor Readout Cycle
Flip Capacitor Filter
● Trapezoidal WTF
optimum for series white noise @
target speed, 1/f minimized by CDS
● implemented with only one amplifier
by flip of Cf
saves area & power
● 4 different Cf are implemented to
cope with different X-ray energies
15 gain settings
(1pF..14pF)
● Integration time can be tuned with
700MHz granularity (globally for the
whole chip)
Negatesbaselineintegration
L. Bombelli et al. “A fast current readout
strategy for the XFEL DEPFET detector”,
NIM, vol. 624, pp. 360-366, 2010
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Pixel Circutis: Single Slope ADC
● Vref of Comp = Vref of Filter!
● Local ramp allows pixel wise gain setting via I-Source (6bits)
allows local offset through in-pixel delay of ramp (5bits)
allows comparator to switch @ same voltage and slope
is voltage drop insensitive
FE Filter ADC RAM
13mm Coplanar
Waveguide
C. Reckleben et al. “8-bit 5-MS / s per-
pixel ADC for the DSSC ASIC”,
FEE 2014
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In-Pixel SRAM Architecture Bias Filter ADC RAM
Block replicated 9 times
to store full ADC words
Serial Readout● Core: IBM Dense SRAM Cell
● Requirement:
Compactness, not speed!
● Custom periphery
● No sense amplifiers
● Global address decoder
● Control signals shared among 4
pixels to save routing
● Serial readout by connecting
word bits and pixel columns in
series
● Capacity: 800 x 9bit words
● Area: 74µm x 229µm
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Pixel Layout: Circuits, M1-3
229µm
204µm
ADC
SRAM
Filter
Injection
Bias Subtract
Co
ntr
ol
SDD Front End
47 slow
control bits
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Pixel Layout: M4-8
M4-5
● ADC Time Stamps
● SRAM & FE Cntrl
● Local Routing
M6
● Caps
● (weak) horizontal
power busses
M7-8
● Caps
● Vertical power
busses, maximum
density exploited
33pF Decoupling
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Latest Experimental Results
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8 x 8 ASIC Prototype + DEPFET
• DEPFET prototype bump-bonded to
ASIC mini-matrix (8x8)
• Complete readout chain:
• DEPFET sensor
• Trapezoidal filter
• 8-bit internal ADC
• SRAM
• All pixels operated in parallel
• ENC ~ 18 el. rms
• Equivalent operating speed 1.2 MHz
• Non-optimal DEPFET (low gain
device)noise peak
~20 el rms
Mn-k
Mn-k
(by J. Soldat,
Heidelberg)
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8 x 8 ASIC with Mini SDD
• MiniSDD prototype bump-bonded
to an ASIC mini-matrix (8x8)
• no DEPFET mode in this variant
est. Cin = 400f
• Complete readout chain:
• MiniSDD Front-end
• Trapezoidal Filter
• 8-bit internal ADC
• SRAM
• All pixels operated in parallel
• ENC ~ 42 el. rms
• Equivalent operating speed 2.2
MHz
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Full Matrix (F1) ADC Gain Trimming
Before trim After trimNom. gain 320 LSB/V
Automated
trimming
procedure
(software)
using on-chip
DAC
DESY FEC
(K. Hansen, C.
Reckleben et al)
4096 ADCs in operation
simultaneously
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Full Matrix (F1) ADC Noise
● Evaluated after gain trimming
for first incoming photons
Energy (keV)
ADC ENC (el.)
0.5 11
1 22
3 66
DESY FEC
(K. Hansen, C.
Reckleben et al)
● In order to have single photon
detection capability we tune the
front end gain to 1 ph / ADC bin
● Noise for small photon counts
● Mean all pixels: 250 µV rms
● Mean left half: 270 µV rms
● Mean right half: 200 µV rms
● Bin size (8 bits): 3.125 mV
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Comissionig of F1 with 64 x 64 Mini-SDD Sensor
Sensor
F1 ASIC(backside)
BondsSensor->PCB
Sensor backside
(metalized)
optical
photons
Imaging in full acceptance by
light pulsing through Al-mask
(4.5MHz, average ADUs over burst, colour axis is roughly set to 1 keV / ADU)
(by J. Soldat,
Heidelberg)
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Summary
● The DSSC ASIC (F1) pixel processing chain contains:
● Two selectable front ends (Mini-SDD OR DEPFET)
● An analog filter (trapezoidal WTF)
● An 8bit ADC (single slope architecture)
● An 800 words SRAM
● The ASIC has a minimal digital interface and comprises an on-
chip digital control block
● The ASIC runs with power cycling to cope with the load current
● The first full format 14x15mm² 4k pixel prototype ASIC has
been fabricated (F1)
the chip is completely functional
characterization with a mini SDD has just begun
● Measured noise performances of mini matrix systems (8x8):
● ENC = 18e- with a DEPFET sensor
● ENC = 42e- with a mini SDD
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Thank You!
