The 8155...The 8155 Block Diagram: 8155 features: 1. Two programmable 8 bit i/o ports (port A and...

Abhishek Dey Assistant Professor Department of Computer Science Bethune College, Kolkata

The 8155

Block Diagram:

8155 features:

1. Two programmable 8 bit i/o ports (port A and port B) 2. One programmable 6 bit i/o port (port C)

3. One programmable 14 bit binary counter and timer

4. 2 kbits static RAM 256x8 5. Address bus AD0- AD7

6. Internal address latch to demultiplex AD0- AD7, using ALE line

7. It contains an internal select logic for memory and i/o using a command register and two I/O

ports 8. It can be easily interfaced with 8085 microprocessor

Control Signals in 8155:

The functions of the above signals can be seen as follows:

1. STB (Strobe Input): This is an input handshake signal. This is connected from a peripheral to the 8155. The low on this signal informs the 8155 that data are strobed into the input port.

2. BF (Buffer Full): This is an active high signal, which basically indicates the presence of a data byte in the port.

3. INTR (Interrupt Request): As clear from the name itself, the rising edge of the STB signal generates this signal. This


happens whenever the interrupt flip-flop (INTE) is enabled. This can be used to interrupt the

MPU.

4. INTE (Interrupt Enable): This is an internal flip-flop which is used to enable or disable the interrupt capability of the 8155.

The interrupts of port A and port B are controlled by bits D4 and D5, respectively, in the control

register.

An example of Interfacing:

The interfacing of 8155 with 8085 is done using I/O mapped I/O.

8155 has on chip de-multiplexing circuit, therefore AD0-AD7 pins of 8085 are directly connected

to AD0-AD7 pins of 8155.

8155 also contains separate (internal) Control signal generator circuit, therefore the IO/M(bar),

RD(bar) and WR(bar) control signals are directly connected to 8155.

Reset out pin of 8085 is connected to reset pin of 8155.

Chip enable is active low signal which is obtained by decoding high order address lines as shown

in the diagram.

Interfacing Diagram:


The chip select logic and port address are shown as:


INTEL 8259A Programmable Interrupt Controller

Block Diagram:

Descripton of signals:

1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).

2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave in a system

with multiple 8259As

3. WR - the write input connects to write strobe signal of microprocessor.

4. RD - the read input connects to the IORC signal

5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master, and is

connected to a master IR pin on a slave.

6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system. In a

system with a master and slaves, only the master INTA signal is connected.

7. A0 - this address input selects different command words within the 8259A.

8. CS - chip select enables the 8259A for programming and control.

9. SP/EN - Slave Program/Enable Buffer is a dual-function pin. When the 8259A is in buffered mode, this

pin is an output that controls the data bus transceivers in a large microprocessor-based system. When the 8259A is not in buffered mode, this pin programs the device as a master (1) or a slave (0).

10. CAS2-CAS0, the cascade lines are used as outputs from the master to the slaves for cascading multiple 8259As in a system.


Interrupt Request Register (IRR):

This block accepts and stores the actual interrupt requests from external interrupting devices on IR0 –IR7

lines. Interrupt request register (IRR) stores all the incoming interrupt inputs that are requesting service. It

is an 8-bit register – one bit for each interrupt request. Basically, it keeps track of which interrupt inputs are asking for service and also stores the pending interrupt requests. If an interrupt input is unmasked, and

has an interrupt signal on it, then the corresponding bit in the IRR will be set.

Interrupt Mask Register (IMR):

This logic block masks interrupt lines based on programming by the processor and prevents masked

interrupt lines from interrupting the processor. The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-bit register. Each bit in this register corresponds to

the interrupt input with the same number. The IMR operates on the IRR. Masking of higher priority input

will not affect the interrupt request lines of lower priority.To unmask any interrupt the corresponding bit is set ‘0’.

In-service Register (ISR):

The in-service register keeps track of which interrupt inputs are currently being serviced. For each input

that is currently being serviced the corresponding bit of in-service register (ISR) will be set. In 8259A,

during the service of an interrupt request, if another higher priority interrupt becomes active, it will be acknowledged and the control will be transferred from lower priority interrupt service subroutine (ISS) to

higher priority ISS. Thus, more than one bit of ISR will be set indicating the number of interrupts being

serviced. Each of these 3-registers can be read as status register.

Priority Resolver:

This logic block determines the priorities of the incoming interrupts set in the IRR. It takes the

information from IRR, IMR and ISR to determine whether the new interrupt request is having highest

priority or not. If the new interrupt request is having the highest priority, it is selected and processed. The

corresponding bit of ISR will be set during interrupt acknowledge machine cycle.

8259A Interrupt Operation:

To implement interrupt, the interrupt enable flip-flop in the microprocessor should be enabled by writing

the EI instruction and the 8259A should be initialized by writing control words in the control register. The

8259A requires two types of control words: Initialization Command Words (ICWS), Operational CommandWords (OCWs). ICWs are used to set up the proper conditions and specify RST vector address.

The OCWs are used to perform functions such as masking interrupts, setting up status-read operations etc.

Step-1: The IRR of 8259A stores the request.

Step-2: The priority resolver checks 3 registers- The IRR for interrupt requests, IMR for masking bits and

the ISR for interrupt request being served It resolves the priority and sets the INT high when appropriate.

Step-3: The MPU acknowledges the interrupt by sending signals in INTA.


Step-4: After the INTA is received, the appropriate bit in the ISR is set to indicate which interrupt level is

being served and the corresponding bit in the IRR is reset to indicate that the request for the CALL instruction is placed on the data bus.

Step-5: When MPU decodes the CALL instruction, it places two more INTA signals on the data bus.

Step-6: When the 8259A receives the second INTA, it places the low-order byte of the CALL address on

the data bus. At the 3rd INTA, it places the high order byte on the data bus. The CALL address is the

vector memory location for the interrupt; this address is placed in the control register during the initialization.

Step-7: During the 3rd INTA pulse, the ISR bit is reset either automatically (Automatic-End-of Interrupt-AEOI) or by a command word that must be issued at the end of the service routine (End of Interrupt-

EOI).This option is determined by the initialization command word (ICW).

Step-8: The program sequence is transferred to the memory location specified by the CALL instruction.

8257 DMA Controller

Block Diagram:

The 8257 provides four separate DMA channels (labeled CH-0 to CH-3). Each channel includes two

sixteen-bit registers:

(1) DMA address register, and


(2) Terminal count register

Both registers must be initialized before channel is enabled. The DMA address register is loaded with the

address of the first memory location to be accessed. The value loaded into the low-order 14-bits of the

terminal count register specifies the number of DMA cycles minus one before the Terminal Count (TC) output is activated. In general, if the number of desired DMA cycles, load the value N-1 into the low-

order 14-bits of the terminal count register.

Interfacing of 8257 with 8085:

DRQ0−DRQ3: These are the four individual asynchronous channel DMA request inputs, which are used by the peripheral devices to obtain DMA services. When the rotating priority mode is selected, then

DRQ0 will get the highest priority and DRQ3 will get the lowest priority among them.

DACKo − DACK3 : These are the active-low DMA acknowledge lines, which updates the peripheral

requesting device service about the status of their request by the CPU. These lines can also act as strobe

lines for the requesting devices.

Do − D7 : These are bidirectional, data lines which help to interface the system bus with the internal data

bus of DMA controller In the Slave mode, command words are carried to 8257 and status words from


8257. In the master mode, the lines which are used to send higher byte of the generated address are sent to

the latch. This address is further latched using ADSTB signal.

Ao - A3 : These are the four least significant address lines. In the slave mode, they perform as an input,

which selects one of the registers to be read or written. In the master mode, they are the outputs which contain four least significant memory address output lines produced by 8257.

A4 - A7: These are the higher nibble of the lower byte address generated by DMA in the master mode.

READY: It is an active-high asynchronous input signal, which helps DMA to make ready by inserting

wait states.

HRQ : This signal helps to receive the hold request signal sent from the output device. In the slave mode,

it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the

CPU.

HLDA : It is the hold acknowledgement signal which indicates the DMA controller that the bus has been

granted to the requesting peripheral by the CPU when it is set to 1.

MEMR: It is the low memory read signal, which is used to read the data from the addressed memory

locations during DMA read cycles.

MEMW: It is the active-low three state signal which is used to write the data to the addressed memory

location during DMA write operation.

ADST: This signal is used to convert the higher byte of the memory address generated by the DMA

controller into the latches.

AEN: This signal is used to disable the address bus/data bus.

TC: It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral

devices.

MARK: The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It

indicates the current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral device.

Vcc: It is the power signal which is required for the operation of the circuit.


Programmable peripheral interface 8255A

Pins and Signals of 8255:


Block Diagram:

The INTEL 8255 is a device used to parallel data transfer between processor and slow peripheral

devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.

The 8255 has three ports: Port-A, Port-B and Port-C.

Port-A can be programmed to work in any one of the three operating modes mode-0, mode-1 and

mode-2 as input or output port.

Port-B can be programmed to work either in mode-0 or mode-1 as input or output port.

Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.

If port-A and B are programmed in mode-0, then the port-C can perform any one of the following

functions:

o As 8-bit parallel port in mode-0 for input or output. o As two numbers of 4-bit parallel ports in mode-0 for input or output.

o The individual pins of port-C can be set or reset for various control applications.

If port-A is programmed in mode- 1 or mode-2 and port-B is programmed in mode-1 then some

of the pins of port-C are used for handshake signals and the remaining pins can be used as input

or output lines or individually set/reset for control applications.

The read/write control logic requires six control signals. These signals are given below.


1. RD (low): This control signal enables the read operation. When this signal is low, the

microprocessor reads data from a selected I/O port of the 8255A.

2. WR (low): This control signal enables the write operation. When this signal goes low, the

microprocessor writes into a selected I/O port or the control register.

3. RESET: This is an active high signal. It clears the control register and set all ports in the input

mode.

4. CS (low), A0 and A1: These are device select signals. They are,

Operating modes –

1. Bit set reset (BSR) mode – If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are used

for set or reset.

2. Input-Outpt mode – If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into

three modes:


Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function or

simple output function. In this mode there is no interrupt handling capacity. Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or port B can

work as simple input port or simple output port, and port C bits are used for handshake signals

before actual data transmission. It has interrupt handling capacity and input and output are

latched.

Example: A CPU wants to transfer data to a printer. In this case since speed of processor is very fast as compared to relatively slow printer, so before actual data transfer it will send handshake

signals to the printer for synchronization of the speed of the CPU and the peripherals.

Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can work

either in mode 0 or mode 1. 6 bits port C are used as handshake signals. It also has interrupt

handling capacity.

A simple schematic for interfacing the 8255 with 8085 microprocessor:

[ RD bar and WR bar should not be directly connected, check book and next diagram]


The 8255 can be either memory mapped or I/O mapped in the system. In the schematic shown in

above is I/O mapped in the system.

Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to

IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.

The address line A7 and the control signal IO/M (low) are used as enable for the decoder.

The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to A1 of 8255

to provide the internal addresses.

The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data transfer.

The I/O addresses allotted to the internal devices of 8255 are listed in table.

Another example:

Step 1: Lower order of 8-bit address A0-A7 is separated from AD0-AD7 using address latch/buffer (Ex: IC

74373) and ALE signal. The separated address lines A0-A1 are connected to A0-A1 input pins of 8255 and

the separated data bus D0-D7 are connected to D0-D7 pins of 8255. Reset out of 8085 is connected to reset pin of 8255.

Step 2: 8255 does not have internal (separate) control logic generator, hence the IO/M(bar), RD(bar) and

WR(bar) control signals are not connected directly to 8255. These pins are 1st given to decoder and

decoded using 3:8 decoder (Ex: IC 74138). The generated control signals IOR(bar) and IOW(bar) are

connected to RD(bar) and WR(bar) input of 8155.

Step 3: An active low signal of chip select logic is obtained decoding remaining address lines of lower

order addresses A2-A7.


.

[Replace A8 – A15 with AD0 – AD7 in the above diagram, Check the decoder output]

Chip select logic and IO port address for this interfacing circuit are as:


Interface 8255 with 8085 microprocessor for addition

Problem – Interface 8255 with 8085 microprocessor and write an assembly program which determines

the addition of contents of port A and port B and store the result in port C.

Example –

Algorithm –

1. Construct the control word register

2. Input the data from port A and port B 3. Add the contents of port A and port B

4. Display the result in port C

Program –

Mnemonics Comments

MVI A, 92H A ← 92H

OUT 83H Control Register ← A

IN 80H A ← Port A;

MOV B, A B ← A;

IN 81H A ← Port B;

ADD B A ← A+B;

OUT 82H Port C ← A

HALT Stop

Reference books and website links:

1. Microprocessor Architecture, Programming and Applications with the 8085 by Ramesh Gaonkar

2. Microprocessor 8085 and Its Interfacing by Sunil Mathur

3. https://www.zseries.in/

4. https://www.geeksforgeeks.org/

Date post:	06-Sep-2020
Category:	Documents
Upload:	others
View:	112 times
Download:	6 times

The 8155...The 8155 Block Diagram: 8155 features: 1. Two programmable 8 bit i/o ports (port A and...

Documents