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1. Theory (why & how it works)

2. Error Sources

3. Advanced DDS Capabilities

4. Applications Examples

Direct Digital Synthesis Theory & Applications

paul.smith@analog.com

2

Phase Time

360360t*Fout

TIME

Fout

TIME0

PHASE

3

Discrete Phase Discrete Time

PHASE

TIME

TIME

2n-1

0

nclk

out 2

FF

Fout

clkF

1

4

How do you build this?

PHASE

TIME

2n-1

0

nclk

out 2

FF

nPHASE REGISTER

CLOCK

n

PHASE ACCUMULATOR

n

1

n = 24 - 48 BITS

Fclk

5

Changing Frequency

PHASE

TIME

2n-1

0

nclk

out 2

FMF

nPHASE REGISTER

CLOCK

n

PHASE ACCUMULATOR

nn = 24 - 48 BITS

M

FREQUENCY CONTROL M = TUNING WORD

DELTA PHASE

REGISTER M

n

M

Fclk

6

Getting a Sinewave Output

AMPLITUDE

TIME0

nclk

out 2

FMF

nPHASE REGISTER

CLOCK

n

PHASE ACCUMULATOR

nn = 24 - 48 BITS

FREQUENCY CONTROL M = TUNING WORD

DELTA PHASE

REGISTER M

n

M

Fclk

PHASE-TOAMPLITUDECONVERTER

p

7

Signal Flow Through the DDS Architecture

2n=fo

M • fc

M = JUMP SIZE

REFERENCECLOCK

PHASEACCUMULATOR

(n-BITS)

PHASE-TO-AMPLITUDECONVERTER

DACM

TUNING WORD SPECIFIESOUTPUT FREQUENCY AS AFRACTION OF REFERENCECLOCK FREQUENCY

DIGITAL DOMAIN ANALOG

N

DDS CIRCUITRY (NCO)TO

FILTER

2n=Fo M

Fclk

Fclk

n

8

Another Way to Look at DDS

6-bitphasewheel

01

234

63

…

…

024

3129…

… 5-bitamplituderesolution

vector dataraw DDS-DAC outputfiltered outputcompared output

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3. Advanced DDS Capabilities

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Direct Digital Synthesis Theory & Applications

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10

Errors in a DDS SystemPHASE ACCUMULATOR

Fclk

nn

FREQUENCY CONTROL M = TUNING WORD

PHASE REGISTER

DELTA PHASE

REGISTER M

CLOCK

n n

n

PHASE TRUNCATION 12-19 BITS N-BITS

(10-14)

n = 24 - 48 BITS

PHASE-TOAMPLITUDECONVERTER

SYSTEM CLOCK

Fout

AMPLITUDE QUANTIZATION

pM

nclk

out 2

FMF

DAC ERRORS

DAC

11

Amplitude Errors

Quantized waveform ≠ Sinewave Therefore there will be spectral components 6.02N + 1.76 quantization noise is only valid when clock

and data are uncorrelated. NOT THE CASE for a DDS! DAC non-linearities

INL and DNL spurs will alias Harmonics from the analog output stage will NOT alias

12

Aliased Distortion Terms

Freq

Distortion in an analog system

FreqFs 2Fs

Distortion in an sampled system

All the distortion terms show up in the passband

13

Effects of Choosing an Odd Value For M

PHASE

TIME

2n-1

0

M=4

PHASE

TIME

2n-1

0

M=5

30 3128 29

2730

14

Effect Sampling Clock / Output FrequencyRatio on SFDR for Ideal 12-bit DAC

(A) FOUT = 2.0000 MHz, fS = 80.0000 MHz

FFT SIZE = 8192THEORETICAL 12-BIT SNR = 74dBFFT PROCESS GAIN = 36dB = 10log(8192/2)FFT NOISE FLOOR = 110dBFS

SFDR = 77dBc SFDR = 94dBc

Ratio = 80/2 = 40 Ratio = 80/2.0117 = 103/4096

(B) FOUT = 2.0117 MHz, fS = 80.0000 MHz

15

Phase Truncation Errors

Green points (outer circle) show n=8 phase accumulator 256 phase steps M=6 in this illustration

Red points (inner circle) show p=5 32 steps passed on the phase-

amplitude converter 3 points get truncated, but the 1st and

4th do not As the phase moves around the

circle, the error becomes periodic Phase error = Amplitude error

Due to phase-amplitude converter Periodic phase error = periodic

amplitude error = spectral component

16

Phase Truncation Error (Time Domain)

Not only is the error periodic, but it also has a ramp shape Therefore we expect the spectral components fall at a 1/m

rate (m = harmonic number)

17

Phase Truncation Error (Frequency Domain)

However, since this is a phenomenon in the digital domain, these spurs will alias.

The largest spur is approximately -6.02p dBc (e.g., -72 dBc for p=12)

The World Leader in High-Performance Signal Processing Solutions

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Direct Digital Synthesis Theory & Applications

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19

Additional DDS Capabilities

Add Frequency Register Sweep Chirp RAM profiles

Amplitude control IQ modulation Multi-DDS

For arrays Phase offset/compensation Spurkiller

20

Frequency Control

nPHASE REGISTER

CLOCK

n

PHASE ACCUMULATOR

nn = 24 - 48 BITS

FREQUENCY CONTROL M = TUNING WORD

DELTA PHASE

REGISTER M

n

Fclk

PHASE-TOAMPLITUDECONVERTER

pM

PRE-PROGRAMMED

FREQUENCY CONTROL

or RAM

TIME

FREQUENCY

21

Amplitude Control

nPHASE REGISTER

CLOCK

n

PHASE ACCUMULATOR

n

Fclk

PHASE-TOAMPLITUDECONVERTER

pM DAC

AMPLITUDEREGISTER

22

IQ Modulation

The DDS is the LO for the Quadrature Modulator Everything is in the Digital Domain and can be made as perfect as necessary

by adding more bits Upsampling gives the DDS room to move the signal around

23

Multiple DDS

Precise phase control allows use in beam forming systems Each DDS starts up in its own phase Phase offsets compensate for phase mismatch in analog reconstruction filters

24

COS(X)

FTW

FrequencyAccumulator

PhaseOffset

143216 10

DAC

DDS Channelfor spur reduction

DDS Channelfor amplitudemodulation

DDS Channelfor phase

modulationRegister Register Register

SpurKiller Technology

Use an auxiliary DDS channel to add in a signal at the same frequency and amplitude as the spur, but 180° out of phase with the highest spur…

AD9911 DDS core

25

AD9911 SpurKiller 500 MHz DDS

It’s all in the Digital Domain!

26

The Results of Using SpurKiller Technologyon a DDS Output Spur

OUTPUT FREQUENCY = 166 MHzFclk = 500 MSPS

500 kHz / DIVISION 500 kHz / DIVISION

BEFORE AFTER

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1. Theory (why & how it works)

2. Error Sources

3. Advanced DDS Capabilities

4. Applications Examples

Direct Digital Synthesis Theory & Applications

paul.smith@analog.com

28

Output Circuits

ROUT

ROUT

IFS – I

I

IOUT

IOUT

RSET

IFS 2 - 20mA typical

ROUT > 100k

Output compliance voltage < ±1V for best performanceThat is, the output can go below ground!

29

Single Transformer Coupling

LCFILTER

MINI-CIRCUITSADT1-1WT

1:1

RLOAD

= 50

VLOAD = ± 0.333V

IOUT

IOUT

0 TO 20mA

20 TO 0mA

± 6.67mACMOSDAC

50

50

+0.45dBm

Note: The 100 differential primary driving impedancerepresents the best compromise between the effects of transformer impedance mismatch and DAC SNR performance.

30

Dual Transformer Coupling

Transmission Line Transformer in series with outputs to help cancel HD2 Dual Transformer design helps minimize imbalance caused by mis-

matched signal coupling from primary to secondary windings. RF Transformer from Coilcraft (TTWB-1-B) shows better performance for

IFs at 200-300 MHz

CMOSDAC

50

50 Mini-CircuitsADTL1-12

CoilcraftTTWB-1-B

TO50

LOAD

20-1200MHz 0.13-425MHz

VLOAD = ± 0.333V

+0.45dBm0 TO 20mA

20 TO 0mA

31

Differential DC Coupling Using a Dual-Supply Op Amp

IOUT

IOUT

0 TO 20mA

20 TO 0mA

CMOSDAC

AD8055

+

–

+5V

–5V

25

25

0V TO +0.5V

+0.5V TO 0V

CFILTER

500

500

1000

1000

± 1V

f3dB = 1

2 • 50 • CFILTER

OR AD8021

32

Differential DC Coupling Usinga Single-Supply Op Amp

IOUT

IOUT

0 TO 20mA

20 TO 0mA

CMOSDAC

AD8061

+

–

+5V

25

25

0V TO +0.5V

+0.5V TO 0V

CFILTER

500

500

2k

1k

± 1V+2.5V

+5V2k

f3dB = 1

2 • 50 • CFILTER

33

High-Speed Buffered Differential DAC Outputs

IOUT

IOUT

CMOSDAC

+

–

AD813xADA493x

VOCM

2.49k

2.49k

5V p-pDIFFERENTIALOUTPUT

0 TO 20mA

20 TO 0mA

0V TO +0.5V

+0.5V TO 0V

25

25

f3dB = 1

2 • 50 • CFILTER

CFILTER

500

500

34

Generating a Clock With a DDSLimiter

ReconstructionFilter

Fsysclock(fc) DAC out Filter out

Clock out

Ideal TimeDomain

Response

IdealFrequency

DomainResponse

"Real World"FrequencyResponse

t

0

1 1 3 5 7

Odd harmonic series

1 3 5 7

t t

f ff

ffffc

fc 2fc

2fc

DDS

External filtering removes unwanted images A squaring circuit converts the signal back to a digital clock

35

Why You Need a Reconstruction Filter

Fout = 56 MHz, Fclk = 175 MHz The MSB does not have a consistent pulse width Jitter shows up when unfiltered output is fed directly to a comparator

36

AN-823 Discusses DDS-based Clocks With Very Low Phase Noise

AD9959 Residual Phase Noise - REF CLK = 500 MSPS

-170

-160

-150

-140

-130

-120

-110

-100

10 100 1000 10000 100000 1000000 10000000

Frequency Offset (Hz)

Pha

se N

oise

(dB

c/H

z)

15.1 MHz

40.1 MHz

75.1 MHz

100.3 MHz

Phase noise floor below –150dBc/Hz

Power dissipation <200mW per channel

15.1 MHz40.1 MHz75.1 MHz100.3 MHz

REF CLOCK = 500MHz, MULTIPLIER DISABLED

100.3 MHz75.1 MHz40.1 MHz15.1 MHz

37

AD9858 1GSPS DDSwith Phase Detector and RF Mixer

38

PLL General Architecture

RF

÷N

Loop Filter

VCO

Phase/ Frequency Detector

Fref

refRF FNF

39

DDS Used as PLL Reference

RF

÷N

Loop Filter

VCO

Phase/ Frequency Detector

Fref DDS

nref

RF2

FNMF

M

40

DDS Used in Fractional-N Loop

RF

Loop Filter

VCO

Phase/ Frequency Detector

Fref

DDS

refRF

n2F

MF

M

41

DDS Used in Translation Loop

RF

Loop Filter

VCO

Phase/ Frequency Detector

Fref

DDS

÷N

n2clkF

MrefRF FNF

Fclk

42

RF Upconversion Using Analog IQ Mixing

DSP CHANNELFILTER

TxDAC

BPFPA

RF

LO

I

Q

I

Q

0°90°

TxDAC

BPF

BPF

AD977x

ADL537x

300MHz – 3.8GHz

43

RF Upconversion Using Digital IQ Mixing

DSP CHANNELFILTER

DACBPF

PA

RF

I

Q

I

Q

0°90°

N

N

BPFNCO

QDUC = QUADRATURE

DIGITAL UPCONVERTER

AD9857AD9957

IF TO 400MHz(AD9957)

LO

44

RF Upconversion Using Dual DDS for LO

DSP CHANNELFILTER

TxDAC

BPFPA

RF

I

Q

I

Q

0°

90°

TxDAC

BPF

BPF

AD977x

ADL5385

50MHz - 2.2GHz

DUALDDS

45

On-Line DDS Tools

ADIsimDDS

46

DDS Design Tool Main Screen

47

DDS Design Tool: Tabular Display of Spurs

48

DDS Design Tool: Display Options and Filter Selection

49

http://www.analog.com/dds

Click ‘More …’ to find the cool technical papers

50

Summary

DDS can be used to obtain a variety of precision waveforms Compared to other frequency generating techniques, a DDS has the

following advantages: Precise phase control without affecting frequency Precise frequency control without affecting phase Fast arbitrary phase changes Fast arbitrary frequency changes Precision modulation

DDS has well known error characteristics Care must be taken designing the output analog circuitry Applications abound!

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