Thermal-aware DC IR-drop co-analysis using non-conformal domain decomposition methods

by Yang Shao, Zhen Peng, and Jin-Fa Lee

Proceedings AVolume 468(2142):1652-1675

June 8, 2012

©2012 by The Royal Society

The geometry of the computational model.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Electrical–thermal coupling.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Notations for decomposing the original problem domain into two sub-domains.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Partitioning of the sub-domain unknowns into interior and boundary unknowns.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Views of the simulated IBM package geometry: (a) top view and (b) side view.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

PDN geometry that could cause the Swiss cheese effect.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Convergence study using DDM to compute voltage distribution of a product-level three-dimensional IC package.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

IBM package PDN with boundary conditions and voltage distribution on the top plane (unit: V).

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Voltage distribution on the power planes of layer 1 and layer 7 (unit: V).

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Voltage distribution on the ground planes of layers 3, 4, 5, 6 and 8 (unit: V).

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Notations for partitioning the problem domain into two sub-domains for steady-state thermal analysis.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Convergence study to compute voltage and temperature distribution of the chip-package-PCB model.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Chip, memory and thermal TSVs of chip and memory layers: (a) top view and (b) side view.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Volumetric power densities in chip and memory layers: (a) CPU1, (b) CPU2 and (c) RAM1 and RAM2.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Non-conformal partitioning and mesh of the PDN of the chip-package-PCB model.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Boundary conditions and voltage distribution of the PDN. (a) Boundary conditions and (b) computed initial voltage distribution at room temperature (unit: V).

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Boundary conditions and temperature distribution of the chip-package-PCB.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Detailed thermal-aware voltage distributions on the chip modules (unit: V).

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society

Maximum thermal-aware IR-drop results with iterations.

Yang Shao et al. Proc. R. Soc. A 2012;468:1652-1675

©2012 by The Royal Society