Enabling a Microelectronic
World®
Jesse Galloway Ph.D. Applied Engineering & Characterization February 16, 2005
Thermal Design Considerations For System in Package
MicroElectronic Packaging & Test Engineering Council
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
What is a System in Package?
A fully integrated system or sub-system • One or more semiconductor chips plus:
• Passive components otherwise integrated on the mother board. — Surface mount discrete passives. — Embedded or patterned into substrate. — Integrated passive components.
• Other subsystem components – EMI shield, SAW/BAW filters, packaged ICs, connectors,
antennas, mechanical housings, etc.
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
Product Using SiPs
MicroProcessors
Telecom
Digital Cameras
Graphic Cards Cell Phones
PDAs http://xcski.com/gallery/cooling/dscn1015
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Why Consider System in Package?
• System integration
• Reduce manufacturing steps at OEM
• Increased electrical performance
• Increased packaging/system density
• Reduce overall cost
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Package Options
Array Lead
Frame
Cavity-up Cavity Down
Wire Through
ePad Standard
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Lead Frame
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Plastic Ball Grid Array (MCM)
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Package Stacking
• Higher final test yield because each package in stack is tested before final assembly.
• Easier to integrate die from multiple suppliers.
• FA is simplified.
• Ideal for logic plus memory integration.
CABGA, S-CSP family low cost
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PoP Thermal Analysis
Logic
SRAM FLASH
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Stack CSP
DRAM
DRAM
BASEBAND
BASEBAND
FLASH
FLASH
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CSP Thermal Analysis
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Flip Chip Ball Grid Array System Integration
http://services.e21corp.com/ase_newsletter/tech_focus.htm
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
Why Is Controlling Temperature Important?
R.K. Kirschman, “Cold electronics: an overview”, Low Temperature Electronics, Ed. R.K. Kirschman, pp. 9, 10 1986.
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
Reference: Influence of temperature on microelectronics and system reliability, by Lall, Pecht and Hakim
Reliability decreases with temperature Electrical performance changes with temperature
Why Is Controlling Temperature Important?
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Heat Paths
ePad
To Application Board
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Heat Paths
Die
Vias
Traces
Planes
Solder Balls
(Array Style Packages)
Top of Package
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Heat Paths Top of Package
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Heat Flow Paths
θbrd
θba
θca Package
System
θjb
θjc
System
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System Vs. Package
7.7mm die Still Air
QFN 2LPBGA TT-01-11
FCBGA + External Heat Sink
TT-00-07
Body Size (mm) 12 35 35
Die Size (mm) 8 10.2 9
IO 100 388 680
θ jc 7.5 5.5 0.40
θ jb 6.8 14.0 4.4
θ ja 14.2 25.8 12.0
θ ca 580 68 7.0
θ ba (1s2p JEDEC Board) 13 9 9
Top Heat Flow 2 26 75
Bottom Heat Flow 98 74 25
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
Theta JC Enhancements Plastic Package Designs Heat Spreader Designs
w
L
w L
• Wire sweep • Wire shorting • Die contamination • Die stress • Wire bond stress • Adhesion • MRT performance • Mold flow • Warpage control • Cost
Manufacturing Concerns
• Die stress • Pump out • Filler size control • Long term stability • Slump • Cost
Manufacturing Concerns
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Theta JB Enhancements
Substrate Style Packages Lead Frame Style Packages
• Die delamination • Warpage control • Manufacturability • Cost
Manufacturing Concerns
• Enhanced die attach • Die flag • Open solder mask • Filled vias • Thermal balls
• Enhanced die attach • MRT • Die cracking • Thermal vias on app. Board • Cost
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
System In Package Thermal Concept
Hot Cold
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MLF SIP Design Example
Hot
Mem
ory
X
• Location of die? • Number of thermal Vias?
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JEDEC Thermal Characterization (Current Methods For One Die Only)
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MCM / Stack Models
Methodology for thermal evaluation of multichip modules By Balwant Lall, Bruce Guenin. IEEE Transactions on components, Packaging and Manufacturing Technology-Part A, Vol. 18, No. 4 1995.
(Multiple Die and Resistances)
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Presented by Li Zhang
MCM / Stack Models (Multiple Die and Resistances)
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MCM / Stack Models (Multiple Die and Resistances)
Generation of Subassembly Compact Half Models Through Experiment Modeling for Hard Drive Thermal Characterization By Jeff Weiss, Ebyson Thomas and Adesoji Airo
20th ITHERM, March 9 – 11, 2004, San Jose, California
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http://www.icepak.com/prod/icepak/solutions/packages/icepak06.htm
ICEPAK “ACE” Method (FEA Model Reduction)
© 2005 Amkor Technology, Inc. February 16, 2005, JESSG
Conclusions
• SiP will see greater adoption for 2005 – 2006 in wireless, PC and game console markets
• Cooling limitations are challenging many higher performance designs
• Thermal enhancement options are available through improved design and material selection
• MCM style packages require improved thermal characterization methods beyond current JEDEC theta ja methods