Thesis

Design and implementation of FPGA based high speed data acquisition

systems for embedded applications

Chandrajit PalUniversity of Calcutta

MONSOON 2010

University of Calcutta 1

Abstract

• In present day technology there is an immense need of developing suitable data communication interfaces for real time data acquisition embedded systems.

• Field Programmable Gate Array (FPGA) offers various

resources which can be programmed for building up an efficient embedded system.

• This thesis paper proposes various resources and implementation methodology for development of Real Time Data Communication interfaces like RS232 serial , SPI controller for A/D and D/A conversion , audio data processing using pmod A/D D/A converters and last but not the least high speed Ethernet communication(100 Mbps, 1Gbps ).

04/08/23 University Of Calcutta 2

Activities

• Introduction to FPGA and embedded systems.

• Implementation of SPI controlled DAC and ADC converters.

• Audio signal processing .

• Embedded system design and checking of system via UART(RS232).

• Implementation of GIGABIT ethernet connectivity.


Introduction to FPGA and embedded systems:

• Electronic Design and Automation (EDA) paradigms allow portions of design problems to move from physical hardware domain to the software domain.

• Today, the availability of high-capacity, high-performance programmable devices(such as Field Programmable Gate Arrays - FPGAs) at relatively low costs is shifting the balance again.

• Motivation and scope of the work The basic motivation of this work was to fulfill some design and implementation

requirements for the DST (Govt. of India) funded project on Embedded System Design for High Speed Data Communication. In our DST project there are experiments which generate high speed analog signals and for that we needed to develop a hardware which can convert these analog signals to digital values as extraction of useful information is easily possible in digital domain. After converting into digital domain processing is done. The experiments also required to communicate with the communication ports at the backbone network, so for that we had developed gigabit Ethernet connectivity.


FPGA(Field Programmable Gate Arrays)

• FPGA denotes an integrated circuit which is programmed in the field, i.e. by the system manufacturer. FPGAs are built from a programmable fabric of logic cells which emulate the user-defined functionality. Due to their programmable nature, FPGAs are rather Programmable Application Specific Standard Products (ASSPs) than custom logic.

• FPGAs are programmable logic devices:– Logic elements + interconnect.– Provide multi-level logic.

04/08/23 University Of Calcutta 5Fig: FPGA fabric

Terminology

•Configuration: bits that determine logic function + interconnect.•CLB: combinational logic block = logic element (LE).•LUT: Lookup table = SRAM used for truth table.•I/O block (IOB): I/O pin + associated logic and electronics.

Parts inside FPGA fabric


Fig : Slice with an LUT

FIG : four to five slices form a CLB

FIG 3: FPGA fabric containing CLB’s and programmable switch matrix

http://en.wikipedia.org/wiki/File:Logic_block2.svg

On board SPI (SERIAL PERIPHERAL INTERFACE) controlled DAC (digital to analog) digital to analog conversion.


Theory The Serial Peripheral Interface Bus or SPI (pronounced "ess-pee-i" or "spy") bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.

Fig 4: SPI bus: single master and single slave

During each SPI clock cycle, a full duplex data transmission occurs:the master sends a bit on the MOSI line; the slave reads it from that same linethe slave sends a bit on the MISO line; the master reads it from that same line[4]

Fig 5: A typical hardware setup using two shift registers to form an inter-chip circular buffer

Different master slave configurations


Fig 6: Typical SPI bus: master and three independent slaves

Fig7: Daisy-chained SPI bus: master and cooperative slaves

SPI communication

• The Spartan-3E Starter Kit board includes an SPI-compatible, four-channel, serial Digital to- Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header, which uses the Digilent 6-pin Peripheral Module format. The DAC and the header are located immediately above the Ethernet RJ-45 connector, as shown in the figure


Fig 8: chip diagram

SPI communication contd..

• As shown in the given figure the FPGA uses a Serial Peripheral Interface (SPI) to communicate digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous, character-oriented channel employing a simple four-wire interface. A bus master—the FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data (SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master.


Signal FPGA Pin Direction DescriptionSPI_MOSI T4 FPGA->DAC Serial data:

Master Output, Slave Input

DAC_CS N8 FPGA->DAC Active-Low chip-select. Digital-to-analogconversion starts when signal returns High.

SPI_SCK U16 FPGA->DAC ClockDAC_CLR P8 FPGA->DAC Asynchronous

, active-Low reset input

SPI_MISO N10 FPGA<-DAC Serial data: Master Input, Slave Output

Timing diagram and communication protocol


Signal Disabled Device Disable ValueSPI_SS_B SPI serial Flash 1AMP_CS Programmable pre-amplifier 1AD_CONV Analog-to-Digital Converter

(ADC)0

SF_CE0 StrataFlash Parallel Flash PROM 1FPGA_INIT_B Platform Flash PROM 1

DAC output voltage


Each DAC output level is the analog equivalent of a 12-bit unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.

The reference voltage associated with DAC outputs A and B is 3.3V ± 5%.

The reference voltage associated with DAC outputs A and B is 2.5V±5%.

Results

A fixed digital value of “1000 0000 0000” was given


Fig 9: Multimeter showing the voltage output to DAC output at A.

Analog capture circuit

• The Spartan-3E Starter Kit board includes a two-channel analog capture circuit, consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in Figure a


Detailed View of Analog Capture Circuit


Interfacing signals and Gain settings


Signal FPGA Pin Direction DescriptionSPI_MOSI T4 FPGA->AD Serial data: Master Output, Slave Input.

Presents 8-bit programmable gain settings, as defined in Table T3.2.

AMP_CS N7 FPGA->AMP Active-Low chip-select. The amplifier gain isset when signal returns High.

SPI_SCK U16 FPGA->AMP ClockAMP_SHDN P7 FPGA->AMP Active-High shutdown, resetAMP_DOUT E18 FPGA<-AMP Serial data. Echoes previous amplifier gain

Settings. Can be ignored in most applications.

SPI Control Interface


Figure highlights the SPI-based communications interface with the amplifier. The gain for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The most-significant bit, B3, is sent first.

Analog to digital conversion interface


Figure provides an example SPI bus transaction to the ADC.When the AD_CONV signal goes high, the ADC simultaneously samples both analog channels. The results of this conversion are not presented until the next time AD_CONV is asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s complement binary value.

Digital Outputs from Analog Inputs

• The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14-bit digital representation, D [13:0], as expressed by Equation


Results and lab views

Figure shows the digital values corresponding to the onboard analog voltage

• In present day technology there is an immense need of developing suitable data communication interfaces for real time embedded systems. Field Programmable Gate Array (FPGA) offers various resources which can be programmed for building up an efficient embedded system. This chapter proposes techniques as well as implementation methodology for real Time Data Communication which includes analog to digital conversion of real time audio signals, its subsequent processing and then conversion of digital signal to its analog counterpart to the outside world.


Analog and digital audio signals

Analog and digital audio signals contd..

• ANALOG TO DIGITAL AND DIGITAL TO ANALOG COMMUNICATION: Analog to digital and digital to analog converters are often used in the electronic world, and it is only because of their presence we can interface a digital system with the outside world which works in analog.

• In our implementation procedure we have used two twelve bit chips the PMOD-AD1 and the PMOD-DA2, which includes the ADCS7476MSPS [8] and the DAC121S101 [9] chips respectively.

• Here we are taking an audio signal as an analog input which is then converted into a digital value, processing it( amplifying and varying the sampling rate) and then again converting the processed digital value to it’s analog counterpart into the outside world. The two chips listed serialize their data (so they can fit in small form factors) and can be clocked to a maximum of 20MHz.

• Both chips require that data be available by the rising edge of the clock, and specify that they will present data on the falling edge of the same clock cycle.


Implementation of FSM(FINITE STATE MACHINE)


Implementation of the finite state machine: The four states used are namely: stationary, read_adc, process, write_data. The stationary state serves to set up pins and timing signals before the system is getting ready to execute, the “read_adc” state reads the 12 bit signal from the ADC, the “process” state performs a simple transform on the number, then varies the sampling rate of the audio signal, and the DAC is then updated to output the result of this transform [7].

ADC Chip Timing Diagram

• ADC (ANALOG TO DIGITAL): The ADC follows a simple format, where, after pulling CS low, four zeroes are transmitted, following by a twelve bit number. This twelve bit number describes the voltage acquired by the circuit. The data is clocked with the MSB first[10].


ADCS7476 Serial Interface Timing Diagram

DAC Chip Timing Diagram

• DAC (DIGITAL TO ANALOG): The DAC follows a similarly simple data scheme, whereby after pulling sync high (it can be left high for the duration of the procedure) 16 bits are written to the circuit. The first two need to be the zeroes, the next two are configuration bits, make certain they are zero as well. The last twelve bits describe the voltage that the DAC will output. In this case it will be the number obtained from the process step [11].


DAC121S101 Timing

FPGA BASED DATA ACQUISITION SYSTEM:


In our implementation we have used the audio signals as an analog input voltage. The analog to digital module converter board (the AD1™) converts [2] the analog value to the corresponding 12 bit digital value by (ex. 1)

D[11:0]= (Vin* 4096)/ Vref ---------------eqx1

Results and Analysis


Results for a sampling frequency 10 MHz.: (a) Analog signal at the DAC output and(b) Corresponding digital data at the input of DACCaptured through ChipScope.

(a) (b)

Comparative study of audio signals


(a)

Results for a sampling frequency 1 MHz.: (a) Analog signal at the DAC output and(b) Corresponding digital data at the input of DAC Captured through ChipScope.

Results for a sampling frequency 500 KHz..: (a) Analog signal at the DAC output and(b) Corresponding digital data at the input of DACCaptured through ChipScope.

Testing of the voltage


Fig a and b shows the audio signals interfacing and the corresponding voltages measured.

Input SignalVoltage(beforeADC)

DigitalValue(from ChipScope in Hex)

OutputVoltage(fromDAC)

Error(%)

3.3V FFE 3.298V 0.04

1.24V 5EB 1.233V 0.53

1.84V 8C1 1.80V 2.17

Table : The results for ADC and DAC conversion for different DC voltage signals.

(a) (b)

Figures below representing my friends getting a taste of the application.


RS232 Serial communication and peripheral test

• This small project shows the implementation procedure to create a simple processor system using Xilinx Platform Studio to test the integration and communication of peripherals to the processor on the processor local bus followed by transferring the testing data to the HyperTerminal of the PC through the RS232 serial cable from the FPGA prototyping board.

• This PROJECT will be an introduction to design techniques for EDK as it is related to the SPARTAN-3E platform. It will be necessary to have a null modem cable to communicate between the Hyper Terminal on the PC and the SPARTAN 3E FPGA platform [5].

• The objective is to understand the basics of the EDK software. This will be accomplished through the implementation of a UART in an FPGA. The circuit will be designed in such a way that the phrases as shown in the figure will be displayed to a HyperTerminal.


Our embedded design [12].


Processor architecture and the peripherals connected to the processor local bus


Block Diagram


Fig : processor connected to the BRAM. Fig: peripherals connected to the processor local bus.

Communication between the PC and the RS232 board.


Transmitted data (FPGA to Computer through RS232 serial port) Bit files are downloaded to FPGA using Xilinx Platform Cable USB II FPGA board are connected to PC from RS232 port (FPGA) through RS232 Cable

ABSTRACT VIEW


CPU here is analogous to MicroBlaze in the fpga Spartan 3e kit and the UART analogous to XPSUART_lite(an IP core).Universal asynchronous receiver and transmitter (UART) is a circuit that sends parallel data through a serial line. UARTs are frequently used in conjunction with the EIA (Electroni Industries Alliance) RS-232 standard, which specifies the electrical, mechanical, functional, and procedural characteristics of two data communication equipment.

Fig : transmission of a byte

The serial line is ’ 1 ’ when it is idle. The transmission starts with a start bit, which is ’O’, followed by data bits and an optional parity bit, and ends with stop bits, which are ’1’.

BLOCK DIAGRAM OF A COMPLETE UART


Pin diagram and hyperterminal settings


Results


ETHERNET

Ethernet is a local area network technology that transmits information among computers at speeds of 10 and 100Mbps as well as 1 and 10gbps.Currently 100Mbps is the most widely used version of Ethernet Technology. Ethernet was generally developed from ALOHA network (developed in late 60s) by Robert Metcalfe and his team at Xerox Palo Alto Research centre in the 70s(1973,22nd may).


How Xilinx EMAC Cores Fit into the OSI Model

ETHERNET SYSTEM

There are four basic blocks which complete an Ethernet System, those are:

• Ethernet Frame – standard used to carry bits over the system • Media Access Contoller(MAC) – control block for allowing

multiple system to access the Ethernet Channel fairly. • Signalling Components – Components used to recieve and

send data over the Ethernet Channel

• Physical medium – the cabling and other hardware used to carry the Ethernet signals among systems on the Ethernet.



Fig : Block diagram of an Ethernet System

ETHERNET SYSTEM(CONTD…)

An Ethernet Frame

8 bytes 6 bytes 6 bytes 2 bytes 46 to 1500 bytes

4 bytes

Preamble Destination Address

Source address

Length/type

data Frame check sequence(CRC)


Preamble -Used to give hardware in the system a signal startup time to recognize a frame transmissionDestination/source address – Unique 48 bit address,made up of a 24-bit Organizationally Unique Identifier(QUI) assigned by the IEEE standards Association,followed by a unique 24-bit vendor specific address(also known as the MAC,hardware,or physical address).Length/Type – used to carry length information; also used to identify what type of high-level protocol is being carried in the Data fieldData – can be between 46 bytes to 1500 bytes. Padding can be used if the length is less than 46 bytes to ensure every Ethernet System “hears” the frameFrame Check Sequence(FCS) – contains the CRC from the sending station to check frame integrity

Adding a custom peripheral


http://2.bp.blogspot.com/_DjItytnrr5U/SS69rKCtsAI/AAAAAAAAG4Q/mrxftVgR41M/s1600-h/create4.JPG


Illustrates the major functional blocks of the Ethernet MAC example design. All components are provided in HDL, with the exception of the Ethernet MAC

component.

Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper


The Virtex-5 Embedded Tri-mode Ethernet MAC is useful for designs requiring Ethernet connectivity.The generated example is a simple design that mirrors incoming Ethernet packets, swapping the source and destination MAC addresses

PHYSICAL LAYER


Physical Coding Sublayer [PCS] is the GMII sub-layer responsible for the interface to the Reconciliation layer. The PCS layer uses 8B/10B encoding.

Physical Medium Attachment [PMA] is the GMII sub-layer responsible for providing a medium-independent for the PCS to support serial bit-oriented physical media. This layer serializes code groups for transmission and deserializes bits received from the medium into code groups. The Gigabit Ethernet PMA interface is identical to the PMA interface used in fiber Channel, but the difference is FiberChannel utilizes 1.062-gigabaud signaling while Gigabit Ethernet utilizes 1.25- gigabaud signaling. Encoding is 8B/10B.

Physical Medium Dependent [PMD] is the GMII sub-layer responsible for mapping the physical medium to the PCS. The Medium Dependent Interface [MDI] is the physical layer interface, and is part of the PMD.

The Ten-Bit Interface is defined to provide compatibility among devices designed by different manufacturers.Connects the PCS and PMA sublayers.

Pop up showing connection …..


WireShark application detecting network traffic


Conclusion and future scope

• This work shows the different methodologies and implementation techniques for realizing real time data communication in FPGA based systems with both analog and digital type of data as well as transmitting data through high speed gigabit Ethernet connectivity.

• Our work also proves the effectiveness of FPGA based development of real time systems for different scientific and industrial work.

• The future work will target more complex real time applications involving real time data processing and transmission(audio video signals) through Ethernet port to the backbone network etc, which will enable to explore the possibilities of building embedded systems for complex real time operations.


Acknowledgements:

This project wouldn’t have been possible without the help of our Sir Dr. Amlan Chakrabarti and my senior Mr Suman Sau (DST research fellow)who really worked a lot for providing us a beautiful environment to work and other technical and non technical staffs.

Also we want to thank Mr Samik Basu ,employee of COREeL technologies for providing ideas to select tools and kits, with the help of which we developed the project and Mr Srikar Talla for giving us a nice training.

50University of Calcutta08/04/23

References



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