MULTI-MODULUS DIVIDER IN FRACTIONAL-N FREQUENCY SYNTHESIZER FOR DIRECT CONVERSION DVB-H RECEIVER A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University By John Hu, B.S. ***** The Ohio State University 2007 Master’s Examination Committee: Mohammed Ismail, Adviser Steven Bibyk Approved by Adviser Graduate Program in Electrical and Computer Engineering
Transcript
MULTI-MODULUS DIVIDER IN FRACTIONAL-N
FREQUENCY SYNTHESIZER FOR DIRECT
CONVERSION DVB-H RECEIVER
A Thesis
Presented in Partial Fulfillment of the Requirements for
Table 3.2: Frequency Division: Theoretic vs Measured at 2.5 GHz input
39
Figure 3.17: Testbench for Noise Simulation
3.3.2 Noise Simulation
A major advantage of current mode logic is its relatively low noise compared to
other topology. The phase noise generated by the divider can affect the synthesizer
noise performance [15].
Two types of simulations in Cadence Analog Design Environment are run: Pe-
riodic Steady-State Analysis (PSS) and Periodic Noise Analysis (Pnoise). The PSS
analysis computes the periodic steady-state response of a circuit. It determines the
circuit’s periodic operating point which is required starting point for Pnoise. Pnoise
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Figure 3.18: Multi-modulus Divider phase noise: 10k to 10 MHz
analysis then linearizes the circuit around the periodic operating point and computes
the resulting noise performance [4].
Figure 3.17 is the testbench for output noise simulation of the multi-modulus
divider. Figure 3.18 shows the output phase noise of the divider at 10 kHz to 10 MHz
frequency offset. The flicker noise corner is around 1 MHz offest, and the white noise
floor is less than or equal to -145 dBc/Hz.
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Component Models Voltage Supply Temperature Max. FrequencyFF 1.92 V -10 ≥ 2.5 GHz (100 %)TT 1.8 V 27 2.5 GHz (100 % )TT 1.8 V 57 2.3 GHz (92% )TT 1.62 V 27 2.3 GHz (92% )SS 1.8 V 27 2.3 GHz (92% )SS 1.62 V 57 1.9 GHz (76%)
Table 3.3: Maximum Operating Frequency under Different Process Corners
3.3.3 Corner Simulation
TSMC 0.18 µm CMOS process CDK contains detailed information about its RF
and baseband MOSFET as well as resistor, inductor, capacitor, varactor BSIM3
(V3.24) models. In addition to norminal parameters, which is typical N typical P,
Fast N Fast P, Slow N Slow P, Fast N Slow P, and Slow N Fast P corner models
are also available for MOSFETs. TT, FF and SS corner models for other circuit
components are also included, which gives designers options to simulate circuits in a
number of different scenarios.
As mentioned in section 3.3.1, divide-by-63 enables all the divide-by-2/3 cells for
divide-by-three action, which involves the most delay in terms of internal transmission
delay and contingent block feedbacks. Thus, divide-by-63 mode at 2.5 GHz maximum
input frequency is selected for comparison among all corners.
Fast corners and conditions, as well as nominal, or typical circuit parameters all
generate correct input output division ratio and frequency relationship. However,
slow corners demonstrate different degrees of slow down in speed, as shown in table
3.3. The worst case is when device shifts to slow corner, voltage supply drops and
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temperature rises at the same time, in which the multi-modulus divider lose as much
as 30% of its nominal operating speed.
3.3.4 Statistic Simulations
The manufacturing variations in components, including process variations and
mismatches, affect the production yield of any design that includes them. Monte
Carlo simulation of Cadence Design System provides a platform to study this influence
in details.
Monte Carlo simulation is a statistic simulation that specifies the possible range
that device models, process variations and mismatches etc would vary. It runs multi-
ple statistic independent runs with parameters picked from the range randomly with
the identical distribution from run to run. TSMC PDK includes Monte-Carlo model
files for MOSFET’s that could be used for Monte Carlo simulations. External pa-
rameters such as temperature and voltage supply are varied among a list of specific
values.
In order to guarantee proper operation across process, voltage supply and tem-
perature variations, a Monte Carlo analysis is performed on both transient and DC
operating point simulation. Alterations on both temperature (27 , -10 , 57 )
and voltage supply (1.8 V, 1.62 V and 1.98 V) are applied.
Figure 3.19 shows the transient behavior of the Multi-modulus Divider output
waveform at maximum moduli (divide-by-63 mode) with a 1.6 GHz sinusoid signal
as the input. The start up time of each run differs, but the output period stays the
same as 39 ns.
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Figure 3.19: Monte Carlo Transient Analysis at 1.6 GHz
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Figure 3.20: Monte Carlo Transient Analysis at 2.5 GHz
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Figure 3.21: Biasing Current Distribution under temperature (27 , -10 , 57 )variations
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Figure 3.22: Biasing Current Distribution under voltage supply (1.8 V, 1.62 V and1.98 V) variations
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Figure 3.20 shows the waveform at maximum moduli (divide-by-63 mode) with 2.5
GHz sinusoid signal input. With process variation, mismatch, voltage, temperature
selected randomly in a range, the output waveforms do not all satisfy the design
requirement. A few runs have less than expected period due to the missing of divide-
by-3 function because of the slowdown of the circuit.
Figure 3.21 shows the distribution of the biasing current of each divide-by-2/3
prescaler under temperature variations. Most of the distributions are in a bell curve,
with an exception for dual-modulus prescaler cell five under 1.92 Voltage supply,
which shows a slightly off distribution to the lower side. The standard deviation of
the biasing current, which is in the order of 30 µA, partly explained the existence of a
few transient simulation results that are off. In a current mode logic, the deviation of
biasing current high frequency cells directly translates to a variation of voltage swing,
which substantially influence the correctness of logic operation of the following stages.
3.4 Layout Efforts and Physical Verification
A complete VLSI design cycle involves efforts in three distinctive domains: behav-
ioral, structural, and physical. So far, we have conducted design in both behavioral
and structural domains. In section 3.1, the multi-modulus divider design is done in
the behavioral domain, which describes the functions of the divider and how it is
partitioned into different units (a chain of dual-modulus divide-by-2/3 prescalers). In
section 3.2, the design goes into structural domain where we look at how the func-
tional units are constructed (prescaler logic and end-of-cycle logic), how transistors
are used to implement the logic (the choice of MOS Current-mode Logic), and how
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the circuit are tailored to emphasize low power (the scaling of bias current in the
cells).
However, physical design is indispensable for a complete VLSI design cycle. Phys-
ical design describes the layout of the chip [33]. The layout of an integrated circuit
defines the geometries that appear on the masks used in fabrication [22]. The ge-
ometries include n-well, active, polysilicon, implants, interlayer contacts, and metal
layers etc. While device scaling has enhanced the raw speed of transistors, unwanted
interaction between different sections in the layout limit the speed and precision of
the integrated circuit [22]. So it is important to study these undesirable influences
through layout efforts and post-layout simulations.
AMI 0.6 µm CMOS process is one of the many processes available for chip fab-
rication at the Ohio State University. Since the architecture of the multi-modulus
divider described in section 3.1 is generic, and the principles of current-mode logic
remain valid regardless of the fabrication process, we migrated the circuit to AMI 0.6
µm CMOS process in order to verify the design methodology and probe the influences
caused by layout. For the rest of this chapter, the layout design and simulation results
refer to the ones conducted in AMI 0.6 µm process if not specified otherwise.
3.4.1 Layout Efforts
AMI Semiconductor 0.50 Micro C5 is a family of mixed-signal foundry process
with 3 metal layers, 2 poly layers, and a high resistance layer suitable for 5 volt appli-
cations [24]. It is widely used for digital circuits. The process supports both vendor
native rules, i.e. rules that are specific to this process, and vendor- independent,
MOSIS Scalable CMOS (SCMOS) rules. The SCMOS rules are a common set of
49
rules widely supported by MOSIS that intend to simplify and unify the layout design
and verification process. Circuit geometries are specified in the Mead and Conway’s
lambda based methodology [16].
Even though specific vendor’s layers and design rules usually lead to denser lay-
outs, they also yield designs that are less likely to be directly portable to another
process. [16] SCMOS rules allow us to work on abstract layer and metric units
“lambda”, which is associated to the feature size of the process. The minimum MOS-
FET channel length is defined to be equal to 2λ. In AMI C5 process family, “lambda”
is equal to 0.3 µm. Therefore, the minimum channel length is 0.6 µm.
Figure 3.23 shows the layout of the AND Latch cell in the first dual-modulus
prescaler cell. In addition to the basic design rules imposed by MOSIS, additional
layout strategies were applied for better performance of the circuit.
1. Source Sharing. CML circuits primarily consist of differential pairs. A good
matching of the MOSFET transistors is very helpful. Therefore, NMOS tran-
sistors in all three input differential pairs and the fourth pair in feedback con-
nection share the source terminals through overlapping. This practice reduces
the layout area, and it also avoids asymmetries, which would introduce input-
referred offsets in fully differential circuits [22].
2. Arrays of Substrate Taps. The n-wells for PMOS transistors need to be con-
nected to VDD, the highest voltage in the circuit, while the bodies for NMOS
transistors need to connected to GND, the lowest voltage potential, which are
to ensure the S/D junction diodes remain reverse-biased under all conditions
[22].
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Figure 3.23: Layout of an AND Latch in AMI C5N process
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Instead of using a single n-well tap or substrate tap, an array of taps are used
to reduce the equivalent resistance of the connection, which leads to less unde-
sirable voltage drop from power rails to the actual MOSFET terminals.
3. Metal wiring. AMI C5N process has three layers of metal for all interconnection.
In order to use them efficiently, a stick diagram (not included in the thesis) is
sketched before the actual layout of any circuit or sub-circuit unit is conducted.
In this design, Metal 1 and Metal 2 are used for intra circuit connection, with
Metal 1 in the horizontal orientation and Metal 2 in the vertical orientation.
Metal 3 is left for inter circuit interconnection and feedbacks.
The layout of a CML D latch is similar to the one shown in figure 3.23 except for
the absence of intermediate pitch in AND Latch, which is required for AND logic
but not present in a simple D latch layout.
Finally, it is important to consider the necessary output buffers for a chip in
order to properly drive inevitable loads and capacitance associated with measurements
and testing. A typical input capacitance of measuring cable is around 40 to 60 pF.
Therefore, we designed our output buffer to drive up to 60 pF off chip capacitance.
Figure 3.24 is the the output driving stage of the multi-modulus divider. The
input operational amplifier converts the differential input signals to a single-ended
output signal. The two source followers act as output buffers as well as voltage level
shifters. By increasing the sizes of the the driving NMOS’s and the biasing currents,
the buffer could gain the required driving capability.
Figure 3.25 shows the final layout of a two-bit multi-modulus divider in a Tinychip
area (1.5mm× 1.5mm). Hi-ESD (ElectroStatic Discharge) protection pad frame was
used for the chip.
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Figure 3.24: Differential-to-Single converter and source follower as output buffer
3.4.2 Physical Verification
After the layout creation is completed, we start the process of physical verification.
Generally, the physical verification procedures can be divided into three parts: the
Design Rule Check (DRC), Layout Versus Schematic check (LVS), and paRasitiC
eXtraction (RCX) [27]. DRC check makes sure the layout does not violate any design
rule. LVS ensures each device in the layout is completely matched to its corresponding
component in the original schematic. RXC extracts the parasitic R and C, which is
needed for post-layout simulation.
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Figure 3.25: Two-bit Multi-modulus Divider Chip in a Tinychip area
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Figure 3.26: Extracted View of the same AND Latch
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Figure 3.26 shows the extracted view of the same AND Latch cell illustrated in
figure 3.23. All the parasitic capacitance values are illustrated between the corre-
sponding terminals. The order of the parasitic capacitance is around several fempto
Fara. For example, at node +63 and +70, the gate capacitance is 3.09 fF, which
is consistent with the typical process parameters provided by MOSIS, which in-
dicates that Poly and N diffusion overlap capacitance is around 2430 aF/µm2 in
AMI C5 processes, or 2.2 fF in total for a 1.5µm by 0.6µm size NMOS transistor
(2.43fF/µm2 × (1.5µm · 0.6µm) = 2.187fF ).
After the paddings and the frame are included, the whole chip is extracted with
parasitic capacitance. Simulation is rerun on the extracted file. Figure 3.27 shows the
transient simulation of the chip after extraction. The two-bit multi-modulus divider
is able to divide by 4, 5, 6, and 7 according to the two control bits Ct1 and Ct2.
The main difference between schematic level simulation and post-layout simulation
in this case is the difference of their maximum operating frequencies. At schematic
level, the multi-modulus divider would be able to run at 250 MHz. After layout
extraction, the maximum operating frequency is only 130 MHz. Junction capacitance,
interconnection capacitance and resistance all contribute to the extra RC delay that
is not included at schematic level simulation. The total chip power consumption
also goes up from 4 mW to 14.6 mW after extraction and with off-chip capacitive
load, which shows the huge amount of dynamic power consumed in charging and
discharging the parasitic capacitance, a significant power burden otherwise unrevealed
by the schematic level simulations.
The post layout delay is substantial. One of the reasons could be that AMI
C5N process does not provide enough protection for transistors operating in high
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Figure 3.27: Post-layout transient simulation of the Multi-modulus Divider Chip at100 MHz input
57
frequencies. There is no guard ring around MOSFET, which makes the transistor
more susceptible to digital switching noise. The lack of triple well structure also
makes MOSFET’s vulnerable to substrate noise coupling. As a result, AMI C5N
process is not the first choice for commercial high frequency design or fabrication.
3.5 Comparison with Other Work
Over the years, many dual-modulus and multi-modulus frequency dividers have
been proposed in the literature. Table 3.4 include a few of the existing designs
of frequency divider that operates at similar frequency or bear similar application
purposes.
Frequency Division Ratio Power Tech CodeJSSC[6] 1.75 GHz 128/129 dual 24 mW 0.7-µm CMOSJSSC[15] 3 GHz 32/33 dual 27 mW 0.35-µm CMOSJSSC[32] 1.4–1.8 GHz 511 to 1023 4.4 mW 0.35-µm CMOS
[28] 2.4 GHz 256 to 271 28 mW 0.35-µm CMOS[26] 2.4–2.48 GHz 481 to 496 9 mW 0.18-µm CMOS
JSSC[8] 20–21 GHz 256 to 263 9 mW 0.13-µm CMOSThis work 1.6–2.5 GHz 32 to 63 23.3 mW TSMC 0.18 CMOS
Table 3.4: Comparison with Existing Designs
From table 3.4, we see that our design is comparable with existing literatures,
except for a relatively high power consumption compared to designs on similar tech-
nologies. This is certainly an area that could be improved in future work.
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CHAPTER 4
CONCLUSIONS AND FUTURE WORK
We have successfully shown in Chapter 3 how a Multi-modulus Divider can be
designed for a Delta-Sigma Fractional-N frequency synthesizer for dual-band DVB-H
receiver. Five divide-by-2/3 dual-modulus prescalers were placed in cascade to cover
the division ratio range of 32 to 63. Current mode logic circuit topology was used for
high speed division.
Layout efforts of a 2-bit Multi-modulus divider in AMI C5N process were also
shown. Post layout simulation confirmed the multi-modulus division functionality as
well as the current mode logic circuit principles, though a substantial slowdown in
maximum operating speed was detected due to the parasitic effects. Possible reasons
for the speed loss were explained.
A lot of work can still be done on this topic, such as further power reduction and
physical verification in an RF-friendly triple-well process. These can be pursued in
future Ph.D. studies.
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APPENDIX A
THE DERIVATION OF MINIMUM VOLTAGE SWINGFOR COMPLETE CURRENT STEERING IN CML GATES
This appendix is intended to show the minimum input differential voltage needed
to fully steer the tail current from one branch of a current mode differential pair to
the other.
Figure A.1: CMOS differential pair and its current-voltage relationship [23]
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The basis for all CML is the differential pair [23]. In figure A.1 , the tail current
as a function of drain currents can be written as:
IEE = iD1 + iD2 (A.1)
The input voltages can be written as the sum of gate-source voltages:
v1 = vGS1 − vGS2 (A.2)
The simple square law voltage-current relationship for a CMOS transistor is [22]:
iD =µCox
2(W
L)(vGS − vTH)2 (A.3)
which can be written as:
vGS =
√2
µCox
(L
W)√
iD + vTH (A.4)
Therefore, equation A.2 can be written as
v1 =
√2
µCox
(L
W)(√
iD1 −√
iD2) (A.5)
Now, making use of equation A.1,
v1 =
√2
µCox
(L
W)(√
iD1 −√
IEE − iD1) (A.6)
Squaring both sides of A.6, collecting terms, we could get
16
(µCox)2(
L
W)2(IEEiD − iD1
2) =4
(µCox)2 (
L
W)2IEE
2 − 4
µCox
(L
W)IEEv2
1 + v41 (A.7)
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This can be solved for iD1 [23]:
iD1 =IEE
2
1±
√√√√v21
µCox
IEE
(W
L)− (µCox)2
4I2EE
(W
L)2v4
1
(A.8)
The term inside the brackets will have a peak value of two at some input voltage
of v1max. This voltage can be determined by setting the derivative of A.8 to zero, and
the result is given by
v1max =
√√√√ 2IEE
µCox(WL
)(A.9)
Where the input differential voltage reaches v1min, the tail current IEE is com-
pletely switched to one branch or the other. For larger differential voltage swing,
one branch continues to take all the current and the other side just becomes more
firmly off. In real circuits, for larger v1, the source voltage then starts to follow input
voltage, limiting the effective differential input as v1max [23].
As a result, v1max is the minimum voltage swing for complete current steering.
When CML gates are in cascade, the out swing of the previous stage should be larger
or equal to this value to ensure the full switching of its following stages.
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APPENDIX B
VERILOG HDL SOURCE CODE FOR DUAL-MODULUSPRESCALER
The following is a list of Verilog HDL code used for behavioral simulation of the
divide-by-2/3 dual-modulus prescaler.
Module Div23 is the behavioral block for divide-by-2/3 prescaler.
module Div23 (modin, fin, modout, fout, P, rst);
input modin, fin, P, rst;
inout modout, fout;
wire d1, qb1, q2, qb2, d3, qb3, d4, q4, qb4;
wire modout, fout;
and (d3,q2,modin);
and (d4,modout, P);
and (d1,qb2,1’b1);
latch D1(fout, qb1, d1, fin, rst),
D2(q2, qb2, fout, ~fin, rst),
D3(modout, qb3, d3, fin, rst),
D4(q4, qb4, d4, ~fin, rst);
endmodule
Among the submodules called, latch is the module for a D Latch.
module latch(Q, Qb, D, clk, rst);
input D, clk, rst;
output Q, Qb;
reg Q;
63
wire Qb;
always @ (clk or rst or D)
begin
if(!rst) Q <= 1’b0;
else if(clk)
Q <= D;
end
assign Qb = ~Q;
endmodule
A simple test bench is needed to provide the driving clock and output waveforms.
‘timescale 100ps / 100ps
‘define Tclk 4
‘define TMod 112
module test();
reg fin, modin, rst, P;
wire fout, modout;
Div23 cell1( .modin(modin),
.fin(fin),
.modout(modout),
.fout(fout),
.P(P),
.rst(rst) );
initial begin
fin <= 1’b0;
rst <= 1’b0;
modin <= 1’b1;
P <= 1’b1;
#5 rst <= 1’b1;
end
initial forever
#‘Tclk fin <= ~fin;
initial forever
#‘TMod modin <= ~modin;
endmodule
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Figure B.1: Divide-by-2/3 dual-modulus prescaler
The figure B.1 shows the input output signals of module Div23. During the time
when modin is high, the output stays high for two input clock period and goes low
for the next input clock period, generating an equivalent divide by three action, as
described in section 3.1.2.
65
BIBLIOGRAPHY
[1] Massimo Alioto and Gaetano Palumbo. Model and Design of Bipolar and MOSCurrent-Mode Logic. Springer, 2005.
[2] Association Management Solutions (AMS). FLO Forum. http://www.
floforum.org/, October 2007.
[3] Victor Berman. Conflicting international standards pressure chip designers.IEEE Design and Test of Computers, 24(1):98–99, January 2007.
[4] Cadence Design Systems, Inc. SpectreRF User Guide, product version 5.0.33edition, October 2004.
[5] Mike Clendenin. China’s Mobile-TV Spec Similar to Europe’s. http://www.
eetimes.com/showArticle.jhtml;?articleID=196604027, December 2006.
[6] Jan Craninckx and Michiel S. J. Steyaert. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-µm cmos. IEEE Journal of Solid-State Circuits,31(7):890–897, July 1996.
[7] Digital Video Broadcasting Project (DVB). DVB-H - Broadcasting to HandheldDevices, October 2007.
[8] Yanping Ding and Kenneth K.O. A 21 ghz 8-modulus prescaler and a 20-ghzphase-locked loop fabricated in 130-nm cmos. IEEE Journal of Solid-State Cir-cuits, 42(6):1240–1249, June 2007.
[9] Broadcast Engineering. Dvb world wide: USA. http://www.dvb.org/about_
dvb/dvb_worldwide/usa/, October 2007.
[10] Ian Galton. Delta-sigma fractional-n phase-locked loops. In Behzad Razavi,editor, Phase-locking in high-performance systems : from devices to architectures,pages 25–33. Wiley-Interscience, 2003.
[11] Golsa Ghiaasi Hafezi and Mohammed Ismail. Low power frequency synthesizerfor dvb-h wireless receiver. SRC Student Symposium 2006, Raleigh NC, 2006.
66
[12] Hassan Hassan, Mohab Anis, and Mohammed Elmasry. Mos current mode cir-cuits: Analysis, design and variability. IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, 13(8):885–898, August 2005.
[13] Texas Instruments. DVB-H mobile digital TV. http://focus.ti.com/pdfs/
wtbu/ti_dvbh_overview.pdf, October 2007.
[14] David Johns and Ken Martin. Analog Integrated Circuit Design. Wiley, Firstedition, 1996.
[15] Salvatore Levantino, Luca Romano, Stefano Pellerano, Carlo Samori, and An-drea L. Lacaita. Phase noise in digital frequency dividers. IEEE Journal ofSolid-State Circuits, 39(5):775–784, May 2004.
[16] Antonio J. Lopez Martin. Tutorial: Cadence design environment. Klipsch Schoolof Electrical and Computer Engineering, New Mexico State University, October2002.
[17] Jason Musicer and Jan Rabaey. Mos current mode logic for low power, low noisecordic computation in mixed-signal environments. In Low Power Electronics andDesign 2000 ISLPED’00, Proceedings of the 2000 International Symposium on.Berkeley Wireless Research Center, Dept. of EECS, University of California atBerkeley, 2000.
[18] Nokia. Mobile TV forum. http://www.mobiletv.nokia.com/, October 2007.
[19] Korea Radio Promotion Association (RAPA). DMB-portal. http://www.t-dmb.org, October 2007.
[20] Behzard Razavi. Design considerations for direct-conversion receivers. IEEETransactions on Circuits and Systems II: Analog and Digital Signal Processing,44(6):428–435, June 1997.
[22] Behzard Razavi. Design of Analog Integrated Circuits. McGraw-Hill, 2001.
[23] John Rogers, Calvin Plett, and Foster Dai. Integrated Circuit Design for High-Speed Frequency Synthesis. Artech House Microwave Library, 2006.
[24] The MOSIS Service. Ami semiconductor 0.50 micro c5 process. http://www.
mosis.com/products/fab/vendors/amis/c5/, November 2007.
[25] Europe’s Information Society. Communications from the commis-sion to the council, the european parliament, the european eco-nomic and social committee and the committee of the regions.
centre/communic_reports/mobile_tv/acte_en.pdf, July 2007.
[26] Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, and EdgarSanchez-Sinencio. A low-power frequency synthesizer with quadrature signalgeneration for 2.4 ghz zigbee transceiver applications. In 2007 ISCAS InternationSymposium on Circuits and Systems, pages 429–432, May 2007.
[27] Taiwan Semiconductor Manufacturing Company, Ltd. TSMC PDK usage guide:An introduction on the usage of TSMC process design kits (PDK), release 0.1edition, September 2004.
[28] Sheng-Che Tseng, Chinchun Meng, Shao-Yu Li, Jen-Yi Su, and Guo-Wei Huang.2.4 ghz divide-by-256/271 single-ended frequency divider in standard 0.35-µmcmos technology. In Microwave Conference Proceedings 2005 APMC Asian-Pacific Conference Proceedings. Department of Communication Engineering, Na-tional Chiao Tung University, Hsinchu, Taiwan R.O.C., December 2005.
[29] ETSI EN 302 304 V1.1.1. Digital Video Broadcasting (DVB); Transmission Sys-tem for Handheld Terminals (DVB-H). European Telecommunications StandardInstitute (ETSI), November 2004.
[30] ETSI EN 300 744 V1.5.1. Digital Video Broadcasting (DVB); Framing struc-ture, channel coding and modulation for digital terrestrial television. EuropeanTelecommunications Standard Institute (ETSI), June 2004.
[31] I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis, G. Kamoulakos,A. Kyranas, C. Kapnistis, and N. Haralabidis. A 0.18µm CMOS Dual-BandDirect-Conversion DVB-H Receiver. In 2006 IEEE International Solid-StateCircuits Conference (ISSCC), Mobile TV Session, pages 2494–2503, Feburary2006.
[32] Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, UrsVoegeli, and Zhenhua Wang. A family of low-power truly modular programmabledividers in standard 0.35-µm cmos technology. IEEE Journal of Solid-StateCircuits, 35(7):1039–1045, July 2000.
[33] Neil H. E. Weste and David Harris. CMOS VLSI Design: A Circuits and SystemsPerspective. Addison-Wesley, Third edition, 2005.
[34] Jiren Yuan and Christer Svensson. High-speed cmos circuit technique. IEEEJournal of Solid-State Circuits, 24(1):62–70, February 1989.
