Thesis slides

Thesis Advisor: Dr. Selahattin Sayil

The Phillip M. Drayer Department of Electrical Engineering

Lamar University

Beaumont, TX

04/13/2023 Prajapati 1

A COMPARISON OF RADIATION TOLERANCE OF DIFFERENT LOGIC STYLES

Thesis DefenseMay 2011

Parthivkumar Prajapati

Outline

Introduction

Different Logic Styles

Simulations and Results

Analysis

Conclusion


Introduction


Motivation• With the continuous scaling of CMOS technologies,

the device reliability and power dissipation become major issues.

• Designers are now selecting different logic gate implementations to save the complexity of design and to minimize power issues.

• The sensitivity of semiconductor devices can become a major cause of temporal or soft errors.

Introduction


Motivation

• Soft error susceptibility can become cause of a system failure in deep submicron ICs.

• Need to study the radiation sensitivity of different logic implementations and choose the better radiation tolerant design.

• Need to find radiation sensitive nodes of different logic styles for reliable system design.

Background


Continues Downscaling Technologies

Transistor Density increases, total power increases

To reduce power consumption VDD are scaled down

Charge to make a logic value at a circuit node decreases, noise margin decreases

The systems are now susceptible to noise sources coming from radiation, cross talk, Power supply noise etc.

Single Event Effects


Single Event Hit on a Semiconductor

Reference: Baumann R. “Soft Errors in Commercial Integration Integrated Circuits” 2004


SEE is generated due to a highly energetic particle strike to a sensitive node on a Semiconductor device.

Main Sources:

• High energy Neutrons• Alpha particles

Higher SEEs as Technology advances due to smaller device sizes and lower noise margins with decreasing power supply voltage VDD.

Single event phenomena can be classified into three effects

• Single event upset (soft error)• Single event latchup (soft or hard error)• Single event burnout (hard failure)



• Q is the charge deposited by a particle strike, • τα is the charge collection time constant of the p-n

junction, and• τβ is the ion-track establishment time constant.

Double Exponential Current Pulse Model is Commonly used for Simulating Radiation Effects


Modeling of SE hit (The SE Current Pulse)

)()( //

tt ee

QtI

Reference: Baumann R. “Soft Errors in

Commercial Integration Integrated

Circuits” 2004


SET Generation in a CMOS Inverter• SET is a voltage glitch generated due to a particle strike at a

semiconductor device. • It may be positive or negative depending on the input conditions.

Single Event Transient

04/13/2023 Prajapati 10

SET and SEU in a 6-stage Inverter

'1'

Particle strike

OUTD Q

O1

O2

O3

O4 O

5O

6

VDD

I( t)

CLK

Single Event Soft Errors

SE Induced Soft Delay

04/13/2023 Prajapati 11

'1'

Particle strike

OUTD Q

O1

O2

O3

O4 O

5O

6

I( t)

CLK


SE Induced Clock Jitter and Race

04/13/2023 Prajapati 12

OUTIN

CLK

FF

tj

tr

Jitter Race

CLK

IN

OUT(No Upset)

OUT(Jitter)

OUT(Race)


SE Induced Crosstalk Noise (SECN)With the continuous shrinking in device sizes:• Device density is increasing rapidly in advanced ICs• Spacing between interconnecting metal wires is also constantly being reduced• Coupling capacitance between wires increases.

The noise generated on the neighbor (victim) line from the affecting (aggressor) line switching is called Crosstalk Noise.

04/13/2023 Prajapati 13

'1'

'1'

Particle strike

Aggressor

Victim

Cc

Cg

Cg

SET

SECN LogicError

OUT1

OUT2


SE Induced Crosstalk Delay (SECD)

04/13/2023 Prajapati 14

The delay generated in the victim signal caused by an SET at the aggressor line is called Single Event Crosstalk Delay (SECD).

'1'

Particle strike

Aggressor

Victim

Cc

Cg

Cg

SET

TimingError

OUT1

OUT2

SECD

'0'


Different Logic Styles

The high acceptance of low power VLSI integration added a crucial role to various design levels such as layout, circuit design, architecture, and fabrication technology.

Designers are now selecting different logic gate implementations to save the complexity of design and to minimize power issues.

Various Proposed logic styles are:• Complementary CMOS• Pass Transistor Logic• Transmission Gate• Gate Diffusion Input

04/13/2023 Prajapati 15

Complementary CMOS

04/13/2023 Prajapati 16

A complementary CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-down network (PDN).

Two networks of opposite type, in which the two conduction functions are complementary.

Any logic function can be fully realized using NMOS as well as PMOS connecting between the supply and the gate output.Reference: Rabaey, J.M. Digital

Integrated Circuits: A Design Perspective. 1994

Complementary CMOS

Advantages

• Robustness against voltage and transistor scaling• High noise margin• Sufficient speed• Ease of Design

Disadvantages

• High input load• Weak output driving skill

04/13/2023 Prajapati 17

Pass Transistor LogicThe basic difference of PTL compared to the CMOS logic style is that the source side of the logic transistor networks is connected to some input signals instead of the power lines.

It consists of NMOS or PMOS pass transistor logic with CMOS output inverters

Input inverters that buffer inputs and generates all signals for the pass transistor network

04/13/2023 Prajapati 18

Pass Transistor Logic

04/13/2023 Prajapati 19

The output buffers for speed improvement and voltage level restoration

Many different pass-transistor logic styles have been proposed such as:

• CPL• SRPL• DPL• LEAP• DPTL• EEPL• PPL

Reference: Reto Zimmermann and Wolfgang Fichtner “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic” 1997

Pass Transistor Logic

04/13/2023 Prajapati 20

Advantages

• Compact layout• Reduces number of transistor count

Disadvantages

• Require inverter at the output for level restoration• Static power consumption

Transmission Gate

04/13/2023 Prajapati 21

It builds on the complementary properties of NMOS and PMOS transistors: NMOS devices pass a strong 0 but a weak 1, while PMOS transistors pass a strong 1 but a weak 0.

NMOS and PMOS logic networks are used in parallel and applied the complementary signals at the gate of each transistor.

The control signal to the transmission gate is complementary

Transmission Gate

04/13/2023 Prajapati 22

The transmission gate acts as a bidirectional switch controlled by the gate signal.

Transmission gates can be used to build some complex gates very efficiently.

Transmission Gate

04/13/2023 Prajapati 23

Advantages

• Simple and efficient operation• Reduce voltage drop

Disadvantages

• Require more area• Require complement control signal• Increase transistor count

Gate Diffusion Input

04/13/2023 Prajapati 24

The GDI basic cell seems like a CMOS inverter built in SOI or dual well CMOS process.

The GDI cell contains three inputs:

• G(common gate input of nMOS and pMOS) • P (input to the source/drain of pMOS) • N (input to the source/drain of nMOS)

Bulks of both nMOS and pMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with a CMOS inverter.


04/13/2023 Prajapati 25

Advantages

• Reduce number of transistor count• Reduce supply voltage• Reduce Area, Power and Delay

Disadvantages

• Limitation with CMOS process• Increase manufacturing cost


04/13/2023 Prajapati 26

The all basic GDI logic gate functions cannot implement using the standard CMOS process.

All GDI logic gate functions only possible in SOI or Twin well CMOS process

Qualitative Comparisons

04/13/2023 Prajapati 27

Circuits Logic Design technique Area (µm2)

Power Consumptio

n (µW)

Signal Delay (ps)

C17CMOS 0.1521 2.283 39.66

PTL 0.2028 18.17 81.32TG 0.3042 5.146 51.82

C432 M2CMOS 0.1901 4.894 53.43

PTL 0.2493 15.84 78.15TG 0.3676 6.166 58.93

C6288 FACMOS 0.2282 5.809 90.58

PTL 0.3042 20.61 168.00TG 0.4563 12.32 118.8

Simulations and Results

04/13/2023 Prajapati 28

Circuits used for Experiments:• NAND String• Random circuit• ISCAS-85 c17• M2 module in ISCAS-85 c432• Full Adder module in ISCAS-85 c6288

All these circuits were constructed using: • Standard CMOS, VDD =1.2V

Software used:• Hspice, Custom Waveview

Device Parameters:• 45nm,65 nm, and 90nm BSIM 4.0 model card, University of California Berkeley

Simulations

04/13/2023 Prajapati 29

Radiation Sensitive nodes in TG NAND string

When A=1 and B=1, Sensitive nodes are N1, N2 and OUT1

When A=1 and B=0, Sensitive nodes are N2 and OUT1

Simulations

04/13/2023 Prajapati 30

4. The results of critical charges are obtained for a 45nm CMOS logic style.

5. Now, the same circuit is constructed using 65nm and 90nm CMOS logic style and results are obtained.

6. Steps 1-5 are repeated for logic style PTL and TG.

A

BC

DE

FG

O1O2

O3O4

O5

OUT

Particle Strike

1

11

11

1

1

1.An example circuit (NAND String) is first constructed using a 45nm CMOS logic style

2. The value of A=1 B=1, and A=1 B=0 is considered, respectively for positive and negative critical charge calculation.

3. A energetic particle hit is applied at primary NAND gate sensitive node, O1.

04/13/2023 Prajapati 31

Circuits Logic Style

Sensitive node

45nm 65nm 90nmNegative

Qcrit

Positive Qcrit

Negative Qcrit

Positive Qcrit

Negative Qcrit

Positive Qcrit

NAND String

CMOS O1 14fc 5fc 17fc 7fc 21fc 9fcPTL O1 6fc 8fc 8fc 12fc 10fc 13fc

TGN1 N/A 14fc N/A 31fc N/A 33fcN2 8fc 9fc 11fc 12fc 14fc 17fcO1 5fc 6fc 7fc 8fc 10fc 12fc

Random Circuit

CMOS OUT1 7fc 12fc 10fc 15fc 12fc 19fcPTL OUT1 8fc 13fc 10fc 16fc 12fc 20fcTG OUT1 7fc 12fc 10fc 16fc 14fc 19fc

C17

CMOS n7 8fc 6fc 10fc 7fc 12fc 9fcPTL n7 8fc 7fc 10fc 10fc 12fc 12fc

TGz3 N/A 14fc N/A 18fc N/A 27fcz4 8fc 9fc 11fc 12fc 14fc 15fcn7 5fc 6fc 7fc 8fc 9fc 11fc

C432 M2CMOS O1 8fc 9fc 10fc 11fc 12fc 13fc

PTL O1 6fc 9fc 8fc 11fc 10fc 14fcTG O1 8fc 8fc 10fc 10fc 12fc 13fc

C6288 FA

CMOS n1 4fc 8fc 7fc 11fc 8fc 15fc

PTL z1 N/A 12fc N/A 13fc N/A 16fcn1 7fc 9fc 9fc 11fc 12fc 14fc

TG z2 9fc N/A 11fc N/A 15fc N/An1 6fc 10fc 8fc 14fc 10fc 16fc

04/13/2023 Prajapati 32

Circuits Logic Style Sensitive node

Positive Charge for Soft Delay 200ps

45nm 65nm 90nm

NAND String

CMOS O1 9.0fc 9.0fc 20.5fcPTL O1 12.0fc 13.0fc 17.5fc

TGN1 42.0fc 52.0fc 62.0fcN2 21.0fc 25.7fc 28.0fcO1 16.0fc 20.5fc 24.0fc

Random CircuitCMOS OUT1 23.5fc 28.0fc 30.0fc

PTL OUT1 24.0fc 29.0fc 35.0fcTG OUT1 24.0fc 29.0fc 34.0fc

C17

CMOS n7 10.0fc 11.0fc 12.0fcPTL n7 11.0fc 13.5fc 17.0fc

TGz3 37.0fc 54.0fc 63.5fcz4 16.0fc 22.5fc 27.4fcn7 11.0fc 17.0fc 24.3fc

C432 M2CMOS O1 16.0fc 18.0fc 36.0fc

PTL O1 25.0fc 31.0fc 35.0fcTG O1 24.0fc 29.0fc 34.3fc

C6288 FA

CMOS n1 20.4fc 24.0fc 26.0fc

PTLz1 29.0fc 36.5fc 39.0fcn1 13.0fc 13.4fc 17.0fc

TG n1 27.0fc 28.0fc 39.0fc

Analysis

04/13/2023 Prajapati 33

Analysis Considerations are:• positive critical charge is assumed for SET

generation in logic styles.

• Lower critical charge node among the multiple sensitive nodes of logic style is considered.

04/13/2023 Prajapati 34

Critical Charge Comparisons in 90nm, 65 nm, and 45nm CMOS technologies

NAND String

Random Circuit

c17 c432 M2 c6288 FA

0

5

10

15

20

25

CMOSTGPTL

90nm

Cri

tica

l Ch

arge

(fc

)

NAND String

Random Circuit

c17 c432 M2 c6288 FA

0

5

10

15

20

CMOSTGPTL

65nm

Cri

tica

l Ch

arge

(fc

)

04/13/2023 Prajapati 35

Critical Charge Comparisons in 90nm, 65 nm, and 45nm CMOS technologies

NAND String

Random Circuit

c17 c432 M2 c6288 FA

0

5

10

15

CMOSTGPTL

45nm

Cri

tica

l Ch

arge

(fc

)

The value of critical charge (Qcrit) is least in CMOS logic style and highest in PTL logic style.

04/13/2023 Prajapati 36

Collected Charge comparisons for SD 200ps in 90nm, 65nm and 45nm CMOS technologies

NAND String

Random Circuit

c17 c432 M2 c6288 FA

01020304050

CMOSPTLTG

90nm

Ch

arge

(fc

)

NAND String

Random Circuit

c17 c432 M2 c6288 FA

0

10

20

30

CMOSPTLTG

65nm

Ch

arge

(fc

)

04/13/2023 Prajapati 37

Collected Charge comparisons for SD 200ps in 90nm, 65nm and 45nm CMOS technologies

NAND String

Random Circuit

c17 c432 M2 c6288 FA0

10

20

30

CMOSPTLTG

45nm

Ch

arge

(fc

)

TG logic style requires more collected charges to generate the same value of SD than other logic styles.

Conclusion

PTL logic style is least sensitive to soft errors in comparison to Complementary CMOS and TG.

TG implementation is the most radiation intolerant design among all other techniques considered.

The logic gate implementations other than static CMOS technique have more than one sensitive node.

04/13/2023 Prajapati 38

Conclusion

As transistor size decreases, combinational circuit becomes more susceptible to an energetic particle hit.

TG logic style is less susceptible to Soft Delay Error.

04/13/2023 Prajapati 39

References

04/13/2023 Prajapati 40

• Rabaey, J.M. Digital Integrated Circuits: A Design Perspective. 1994

• Baumann R. “Soft Errors in Commercial Integration Integrated Circuits” 2004

• Reto Zimmermann and Wolfgang Fichtner “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic” 1997

• Morgenshtein, A., A. Fish, and I.A. Wagner "Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits." 2002.

• http://radhome.gsfc.nasa.gov/radhome/see.htm

Questions and Comments

04/13/2023 Prajapati 41

Extras

04/13/2023 Prajapati 42

(a) (b)

(c)(a) Electron hole path created by charged particle (b) Example of three different particle strike paths and (c) Experimental result of collected charges at different particle strike paths (Karnik,

Hazucha and Patel 2004)

Extras

04/13/2023 Prajapati 43

In1

In2

In3

In4

In5

n1

n2

n3

n4

n5

n6

n7

n8

n9

n10

n11

OUT1

OUT2

Particle Strike

0

0

1

1

1

X1

A

E

PB

X2O1

O2

O31

1

0 Particle strike

B

A

Cin

S

Cout

n1

n2

n3

n4

n5

n6

n7

Particle Strike

0

0

1

A

B

C

D

E

OUT1

OUT2

OUT3

OUT4

OUT5OUT6

OUTPUT

1

1

1

0

0

Particle Strike

Thank You..!!!

04/13/2023 Prajapati 44

04/13/2023 Prajapati 45

A COMPARISON OF RADIATION TOLERANCE OF DIFFERENT LOGIC STYLES

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