This Lecture will cover 9How Circuit? - PSAU · This Lecture will cover 9How can you implement the...

This Lecture will coverThis Lecture will cover

How can you implement the Combinational Circuit?

Analysis and Design procedure

Bi AddBinary Adder

•Half Adder•Full Adder

Binary Subtractory

Dr. Saied M. Abd El‐atty Soliman [email protected]

4 May 2010

Combinational Logic• One or more digital signal inputs

• One or more digital signal outputs

• Outputs are only functions of current inputOutputs are only functions of current input values (ideal) plus logic propagation delays

Combinational Logic

I1 O1..

.

.

Im On

( ) ( ) ( )( )tItIFttO =Δ+

...

( ) ( ) ( )( )tItIFtt m,...O 111 =Δ+

( ) ( ) ( )( )tItIFtt mnn ,...O 1=Δ+


4 May 2010 Page 2

( ) ( ) ( )( )mnn ,1

Cont.

• Combinational logic has no memory!Combinational logic has no memory!– Outputs are only function of current input combination

N thi i k b t t t– Nothing is known about past events

– Repeating a sequence of inputs always gives the same output sequence

• Sequential logic (covered later) does have memoryRepeating a sequence of inputs can result in an entirely– Repeating a sequence of inputs can result in an entirely different output sequence


4 May 2010 Page 3

Analysis ExampleThe Rule

1) Label all gates outputs, determine the Boolean Expression of that o/p2) Label the gates at the second level and higher level and determine the Boolean 3) Repeat the process till you have obtained the final output

The Rule

3) Repeat the process till you have obtained the final output4) Obtain the final output as function of inputs

1

2

T B CT A BT A T

′=′=

3 1

4 2

5 2

1 3 4

T A TT D TT D TF T T

= +

= ⊕= += +


4 May 2010 Page 4

1 3 4

2 5

F T TF T

+=

1) From the specification of the circuit, determine the no. of I/P and O/P and label both of themand label both of them

2) Derive a truth table at each O/P) /

3) Obtain a simplified Boolean expression

4) Draw the logic diagram and verify the correctness of the design


4 May 2010 Page 5

Example: Design a Combination logic Circuit to covert the BCD code to Excess‐3 Code.

Decimal Digit BCD Excess‐3

0 0000 0011

1 0001 0100

2 0010 0101

3 0011 0110

4 0100 0111

5 0101 1000

6 0110 1001

7 0111 10107 0111 1010

8 1000 1011

9 1001 1100


4 May 2010 Page 6

9 1001 1100

We have named the BCD as 4 inputs and the Excess‐3 code as the 4 outputs.

Note that: All the other numbers from 10 to15 are represented by don’t care.

ABCD WXYZ

Input Output

Decimal Digit BCD Excess‐3

0 0000 0011

1 0001 0100

2 0010 0101

3 0011 01103 0011 0110

4 0100 0111

5 0101 1000

6 0110 1001

7 0111 1010


4 May 2010 Page 7

8 1000 1011

9 1001 1100

Z D ′= Y CD C D′ ′= +

X B C B D B C D′ ′ ′ ′= + + W A B C B D= + +


4 May 2010 Page 8

Z D ′Z D=

( )Y CD C D CD C D′ ′ ′= + = + +

( )X B C B D B C D

B C D B C D′ ′ ′ ′= + +′ ′ ′= + +( )( ) ( )C C

B C D B C D′ ′= + + +

( )W A B C B D

A B C D= + += + +


4 May 2010 Page 9

Logic diagram for BCD to Excess‐3 Code Converter


4 May 2010 Page 10

– Adds two binary (i.e. 1‐bit) inputs A and B• Produces a sum and carryout

– Problem: Cannot use it alone to build larger adders

– Adds three binary (i.e. 1‐bit) inputs A, B, and carryin• Like half‐adder, produces a sum and carryout

All b ildi M bi dd (M 1)– Allows building M‐bit adders (M > 1)• Simple technique

– Connect Cout of one adder to Cin of the nextout in

• These are called ripple‐carry adders• Shown in next section


4 May 2010 Page 11

Circuit diagramTruth table

x y S C

0 0 0 00 0 0 0

0 1 1 0

1 0 1 0

S xy x y′ ′= +

1 0 1 0

1 1 0 1

C xy=

S x yC xy= ⊕=


4 May 2010 Page 12

Truth table

x y z S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0 K f S K f C0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

K‐maps for S K‐maps for C

1 0 1 0 1

1 1 0 0 1

1 1 1 1 11 1 1 1 1

C xy xz yz= + +S xyz xyz xyz xyz′ ′ ′ ′ ′ ′= + + +

S x y z= ⊕ ⊕

y yy y y y

( )C xy x y z= + ⊕


4 May 2010 Page 13

C xy xz yz= + +S xyz xyz xyz xyz′ ′ ′ ′ ′ ′= + + +


4 May 2010 Page 14

How can you implement full adder by using two half adder?How can you implement full adder by using two half adder?

x y⊕ x y z⊕ ⊕

xy( )xy x y z+ ⊕

Implementation of Full adder with two half adder and an OR gate

S x y z= ⊕ ⊕ ( )C xy x y z= + ⊕


4 May 2010 Page 15

Subscript i: 3 012

Consider an example of adding two numbers of 4bits A=1011, B=0011

p 3 012

Input Carry

A d0 011 Ci

Augend

Addend

Sum

1 1100 110

1 011

Ai

BiSSum

Output carry 0 110

1 011 Si

Ci+1


4 May 2010 Page 164‐bit Adder

Consider an example of subtracting two numbers of 4bits A BConsider an example of subtracting two numbers of 4bits A‐B.We use a four bit adder‐subtractor circuit as shown in Figure, and using 2’s complement to perform the subtracting. M is called Mode input which controls the operation. If M=0 the circuit is adder but when M=1 the circuit becomes subtractoris adder but when M=1 the circuit becomes subtractor.When M=0 the XOR input is and C0=0When M=1 the XOR input is and C0=1

0B B⊕ =1B B ′⊕ =

Application Example

Subtract:1101

‐0011


4 May 2010Page 174‐bit Adder‐Subtractor

Cont.

If the two numbers are unsigned binary no., then C bit detects a carry after addition or a yborrow after subtraction.

4‐bit Adder‐Subtractor

If V=0, then no overflow occurred and the n‐bits

If the two numbers are signed binary no., then V bit detects an overflow.

,results is correct.

If V=1, then results contains n+1‐bits that is the


4 May 2010Page 18

overflow occurred and the correct results is n‐bits

1)Consider the combinational circuit shown in Figure (1)1)Consider the combinational circuit shown in Figure (1)a) Derive the Boolean expression for T1 through T4. Evaluate the outputs F1 and F2 as a function

of the four inputs.b) List the truth table with 16 binary combinations of the four input variables. Then list the ) y p

binary values for T1 through T4 and outputs F1 and F2 in the table.c) Plot the output Boolean functions obtained in part (b) on maps and shows that the

simplified Boolean expressions are equivalent to the ones obtained in part (a).


4 May 2010Page 19Figure (1)

2) Design a Combinational logic Circuit to convert the BCD code to Seven Segment decoder as shown in Figures ,a and b.

Help: first build the truth table and then K‐map and then implement the circuit logic diagram .

The six invalid combination should result in a blank (0000000) display.

3) Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is less than 3. The output is 0 otherwise

4) Design a combinational circuit with three inputs x, y, and z and three output A, B and C . ) g p , y, p ,When the binary input is 0,1,2 or 3, the binary output is one greater than the input. When the binary input is 4,5,6 or 7, the binary output is one less than the input.


4 May 2010Page 20

Exercises5) Obtain the simplified Boolean expression for output F and G in terms of the input variables in5) Obtain the simplified Boolean expression for output F and G in terms of the input variables in the circuit diagram of Figure (2)

Figure (2)


4 May 2010Page 21


4 May 2010 Page 22

Date post:	21-Apr-2018
Category:	Documents
Upload:	nguyenduong
View:	220 times
Download:	5 times

This Lecture will cover 9How Circuit? - PSAU · This Lecture will cover 9How can you implement the...

Documents