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Threshold voltage generation and supply-independent biasing in c.m.o.s. integrated circuits

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Threshold voltage generation and supply-independent biasing in c.m.o.s integrated circuits Y.P. Tsividis and R.W. Ulmer Indexing term: Field-effect integrated circuits Abstract: A method is presented for the generation of a voltage equal to an integer multiple of the n-channel threshold voltage in c.m.o.s. integrated circuits. Experimental results from an integrated prototype are given and possible applications are discussed. 1 Introduction The threshold voltage V T of m.o.s devices is one of the least predictable parameters in integrated circuits. Variations as high as IV can be expected for some processes. As a result, some circuit parameters are also unpredictable and can vary widely (e.g. power-supply dissipation in analogue subcircuits). A means to develop a voltage equal to V T on chip is desirable for at least two reasons. First, since it is a process rather than a circuit parameter, it can be used to provide a power-supply- insensitive reference (a temperature-insensitive, but not supply-insensitive, reference is described elsewhere 1 ). Secondly, if V T is available as an actual voltage in a circuit, one should in several circumstances be able to cancel, or at least reduce, the effect of its unpredictability, by suitable circuit means. A method for generating a voltage equal to an integer multiple of V T will be presented in the next Section. Then, higher-order effects will be discussed and experi- mental results will be presented. Finally, some possible applications will be briefly considered. 2 Description of the method 2.1 Preliminaries In the following we will assume that all m.o.s. devices operate in strong inversion and in the saturation region. Their operation can be approximately described by: 2 - V T f (Id) where K = k'S In the above equations / and V GS are the drain current and gate-to-source voltage, k' is a process-dependent parameter, and S is the ratio of channel width to channel length. To determine the appropriate value of V T to be used in eqn. 1, experimental values of \ZTare plotted against V GS . Over the operating range of interest, a straight line is passed through the points and is extended to \Jl = 0. Paper T289E, first received 3rd July and in revised form 6th November 1978 Dr. Tsividis is with the Department of Electrical Engineering and Computer Science, Columbia University, New York, NY 10027, USA, and Mr. Ulmer is with the Integrated Circuits Division, Motorola Semiconductors Inc., Austin, TX 78721, USA V T will then correspond to the intersection of the extended line with the V GS axis, and is called the (extrapolated) threshold voltage. We will use the symbols V TN and V TP to denote V T for the n-channel and the p-channel devices, respectively. 2.2 Principle of the method The circuit proposed is shown in Fig. 1. A topology that allows both ratioed current biasing and voltage differencing has been chosen. The bias current I R of the centre string is scaled and mirrored by a p-channel current source (M G —M H ) and an ^-channel cascode current source (M A -M B -M C -M D ). Considering the remaining transistors we have, for the output voltage V x , V r = V, GS,El GS,E2 ..+ GS,Em -v, GS,F (2) Assume devices M E1 .. . M Em are identical, and let I E and K E be their common values of / and K. These devices, as well as M F , have zero source-to-substrate voltages, and, DD O H m devices 0 111 o pin i -O Fig. 1 Grcuit with output referenced to the power-supply voltage ELECTRONIC CIRCUITS AND SYSTEMS, JANUARY 1979, Vol. 3, No. 1 1 0308-6984/79/010001 + 04 $01-50/0
Transcript
Page 1: Threshold voltage generation and supply-independent biasing in c.m.o.s. integrated circuits

Threshold voltage generation andsupply-independent biasing in c.m.o.s

integrated circuits

Y.P. Tsividis and R.W. Ulmer

Indexing term: Field-effect integrated circuits

Abstract: A method is presented for the generation of a voltage equal to an integer multiple of the n-channelthreshold voltage in c.m.o.s. integrated circuits. Experimental results from an integrated prototype are givenand possible applications are discussed.

1 Introduction

The threshold voltage VT of m.o.s devices is one of theleast predictable parameters in integrated circuits.Variations as high as IV can be expected for someprocesses. As a result, some circuit parameters are alsounpredictable and can vary widely (e.g. power-supplydissipation in analogue subcircuits). A means to developa voltage equal to VT on chip is desirable for at least tworeasons. First, since it is a process rather than a circuitparameter, it can be used to provide a power-supply-insensitive reference (a temperature-insensitive, but notsupply-insensitive, reference is described elsewhere1).Secondly, if VT is available as an actual voltage in a circuit,one should in several circumstances be able to cancel,or at least reduce, the effect of its unpredictability, bysuitable circuit means.

A method for generating a voltage equal to an integermultiple of VT will be presented in the next Section.Then, higher-order effects will be discussed and experi-mental results will be presented. Finally, some possibleapplications will be briefly considered.

2 Description of the method

2.1 Preliminaries

In the following we will assume that all m.o.s. devicesoperate in strong inversion and in the saturation region.Their operation can be approximately described by:2

- VTf (Id)

where

K = k'S

In the above equations / and VGS are the drain currentand gate-to-source voltage, k' is a process-dependentparameter, and S is the ratio of channel width to channellength. To determine the appropriate value of VT to beused in eqn. 1, experimental values of \ZTare plottedagainst VGS. Over the operating range of interest, a straightline is passed through the points and is extended to \Jl = 0.

Paper T289E, first received 3rd July and in revised form 6thNovember 1978Dr. Tsividis is with the Department of Electrical Engineering andComputer Science, Columbia University, New York, NY 10027,USA, and Mr. Ulmer is with the Integrated Circuits Division,Motorola Semiconductors Inc., Austin, TX 78721, USA

VT will then correspond to the intersection of the extendedline with the VGS axis, and is called the (extrapolated)threshold voltage. We will use the symbols VTN and VTP todenote VT for the n-channel and the p-channel devices,respectively.

2.2 Principle of the method

The circuit proposed is shown in Fig. 1. A topology thatallows both ratioed current biasing and voltage differencinghas been chosen. The bias current IR of the centre stringis scaled and mirrored by a p-channel current source(MG—MH) and an ^-channel cascode current source(M A -M B -M C -M D ) . Considering the remaining transistorswe have, for the output voltage Vx,

Vr = V,GS,El GS,E2 ..+ GS,Em -v,GS,F(2)

Assume devices ME1 . . . MEm are identical, and let IE andKE be their common values of / and K. These devices, aswell as MF, have zero source-to-substrate voltages, and,

DD

O

H

mdevices

01 1 1 o

pin i -O

Fig. 1 Grcuit with output referenced to the power-supply voltage

ELECTRONIC CIRCUITS AND SYSTEMS, JANUARY 1979, Vol. 3, No. 1 1

0308-6984/79/010001 + 04 $01-50/0

Page 2: Threshold voltage generation and supply-independent biasing in c.m.o.s. integrated circuits

therefore, we will assume that they have equal thresholdvoltages. From eqns. 1 and 2 then we have

Vr = m (3)

Assume that biasing and dimensions have been chosenso that the following relation holds:

(4)

(5)

Using eqns. 4 and \b in eqn. 3 we get

Vx = (m - \)VTN

— I = I — II —I—I + 1

An integer multiple of VTN can therefore be developedthat is independent of current to a first order, and there-fore is also independent of the power-supply voltage,VDD. Assuming perfect current sources, the ratio (IF/IE)

can be set by choosing appropriate dimensions for thecurrent mirror devices. It is seen from eqn. 4 and Fig. 1that the following relation must be satisfied among theZ/L ratios of the various devices:

(6)

In our implementation we have used m — 2, SH = SG andSE = SF. From eqn. 6 then, the required value for SA/SB

is 1-25. As will be seen in Section 2.3, this value willhave to be modified once the small-signal outputconductance of the devices is taken into account.

The circuit of Fig. 1 described above generates aconstant voltage referenced to VDD. If a voltage referencedto ground is desired instead, the circuit shown in Fig. 2can be used. The same equations apply.

2.3 Additional considerations

For the circuit of Fig. 1, the A2-channel current mirrorat the bottom must maintain a constant current ratio in the

c

t

"DD

m*" devices

1 1 J T

Fig. 2 Circuit with output referenced to ground

2

presence of large variations across its left branch (whichcan occur if VDD varies). Therefore, a cascode current sourceis desirable.3 If the additional voltage drop needed acrossMc and MD is objectionable, a simple current source withlong-channel devices can be used instead. If ?i\ = 2, acascade configuration cannot be used for the top p-channelcurrent source, since then Vx = VTN which would, ingeneral, be smaller than the voltage required for the cascodedevice to be in the saturation region.

Eqn. 1 does not contain the effect of nonzero 9/D/9PDS

in the saturation region. To investigate this effect one canperform small-signal analysis using a simple model containinga nonzero drain-to-source small-signal conductance g0.In our implementation all such output conductances for then-channel devices are negligible. However, this is not thecase for the p-channel devices, both because of low substratedoping and because of an effective channel length of only6/im. To investigate the effect of this, let a and |3 representthe small signal short-circuit current gain of the w-channelcurrent mirror and thep-channel current mirror, respectively.We have

.8mA

SmB

SmG + SOG

(7)

(8)

where gm is the transconductance. If the gms in eqns. 7and 8 are expressed in terms of device parameters and bias

4_ 3 A.currents,3 we get:

1-1

SmH

(9)

(10)

The sensitivity of Vx with respect to VDD can be obtainedthrough a small-signal analysis of the circuit

VDD SmESmFrt 01)where rt is the total small-signal resistance of the centrebias string. The condition for zero sensitivity is then, fromeqn.11

(12)m\gmF

If goG could be neglected, one could use eqns. 10 and 12to obtain eqns. 4 and 6 again, and, for the values given inSection 2.2, j3 = 1 and a= 1-25. In our case, however,the significant g0G reduces |3, as seen from eqn. 10. For thezero sensitivity condition (eqn. 12) to remain valid, a mustalso be reduced, which, from eqn. 9, requires a value of(SA/SB) smaller than 1-25. From Fig. 1 it is seen that thiswill result in a smaller IE. Therefore, the y/I/K terms ineqn. 3 instead of cancelling one another will contributea negative quantity to Vx. One concludes then, that forzero supply sensitivity in the presence of significant g0G,Vx must be smaller than the value predicted by eqn. 5.

ELECTRONIC CIRCUITS AND SYSTEMS, JANUARY 1979, Vol. 3, No. 1

Page 3: Threshold voltage generation and supply-independent biasing in c.m.o.s. integrated circuits

Threshold voltages for individual devices can generallybe matched within ± 20mV, and ratios of S values can berealised with accuracy, so that current matching of 0-2%is achieved for two adjacent devices. However, if very lowsupply sensitivity is desired, one trimming might benecessary, as discussed in the following Section.

3 Experimental results

The circuit of Fig. 1 has been implemented in integratedform using a standard c.m.o.s. process with a substratedoping of 10lscm~3, an effective p-well doping of2x 1016cm"3, and an oxide thickness of 1000A. Linewidth and spacing was 8/Lim. The mask channel length was20/im for MA . . . MD, and 10 ̂ m for ME1 . . . MF. Thelayout provided for externally changeable (SA/SB). Thiswas achieved by using an array of n-channel devices withbinary-weighted S values, of which an appropriate combina-tion can be connected externally in parallel to form MB.The best value at which (SA/SB) could be adjusted in thisway for close to zero sensitivity was 20/17, which is indeedsmaller than 1-25, as predicted above. The output voltageat 24° C was approximately 0-2 V less than the extrapolatedthreshold. A typical experimental plot of Vx against VDD isshown in Fig. 3. For the device used for these plots, theextrapolated VTN was 1 -79 V. The drop of Vx at very lowvalues of VDD is due to insufficient voltage drop acrossthe*, devices in the circuit, which causes Mc and MH tooperate in the nonsaturation region. The variation of Vx

due to temperature is due to the dependence of VTN ontemperature. The temperature coefficient of Vx, ascalculated from Fig. 3, is approximately — 3mV/°C,which agrees with typical values of the temperaturecoefficient exhibited by the threshold voltage.

A detail of the change in Vx with VDD is shown in Fig. 4.If VX(VDD, 0) denotes the output voltage as a function ofVDD and the temperature 6, the plots in Fig. 4 represent thequantity [VX(VDD, d)-Vx(20V, 0)] for three differentvalues of 0. The average slope over the range of 10 V to30 V does not exceed 1 -5 mV/V for any temperature between- 10° C and + 65° C, and it is as low as 200JUV/V at roomtemperature.

4 Applications

Perhaps the most useful application of the proposed circuitsis that of supply-independent biasing, using the outputvoltage either directly or converted to current. Vx can beused as the VGS for a device, resulting in a current propor-tional to Vj<- Of course, m>3 would be required, todevelop a Vx equal to at least 2 VT for this purpose. If thesquare-law dependence cannot be tolerated, a voltage-to-current convertor can be used if an operational amplifieris available, resulting in a current proportional to VT.Notice that if only a supply independent voltage is desired,the thresholds of devices ME1 . . . MEm and MF do notneed to match.

The proposed circuit can be used to bias the temperature-insensitive reference described elsewhere,1 so that areference insensitive to both temperature and power supplyvoltage can be obtained.

Circuits similar to those in Figs. 1 and 2 can be used todevelop VTP, but less accurately. This is because for astandard cm.o.s. process all p-channel devices would havea common substrate, and, therefore, their thresholdswill in general be different due to the substrate effect.Still, however, this difference in the various VTPs shouldbe small compared to the uncertainty of their total values.

For several circuits, the quantity VTN —\VTP\ is ofinterest. For example, a cm.o.s. inverter with KN = KP

will switch at an input voltage equal to 0-5 [VDD +(VTN — \VTP\)]. The values of VTN and \VTP\ can begenerated, and their difference formed using standardtechniques. Note that, if that difference is added to theinput voltage, the inverter will switch for an input equal to^ D D / 2 , resulting in a symmetry desirable in some circuits.

5 Suggestions for further improvement

The one major improvement that can be achieved is using abetter p-channel current source. Channels preferably longerthan 20/um should be used for MG and MH. This willresult in a value for (SA/SB) closer to the ideal, and to anoutput voltage closer to the threshold, for zero sensitivity.Note that SG and SH must be large, especially if m = 2,to insure that the small Vx does not prevent MH fromoperating in the saturation region.

20r

> 10>*

0-5

10 20 30

WFig. 3 Measured output voltage against power-supply voltage withtemperature as a parameter, for the circuit of Fig. 1

- 1 O ° C+ 24° C+65 f

ELECTRONIC CIRCUITS AND SYSTEMS, JANUARY 1979, Vol. 3, No. 1

Fig. 4 Measured values of VX(VDD, 0) - Vx(20 V, 9) againstVDD> with {he temperature 6 as a parameter

Note that 1^(20 V, 0) is different for each temperature

Page 4: Threshold voltage generation and supply-independent biasing in c.m.o.s. integrated circuits

The circuit can work with VDD < 5 V, if the cascodecurrent source is replaced by a simple configuration withsufficiently long channel devices.

6 Conclusions

We have presented a method for developing a voltageequal to an integer multiple of the threshold voltage ona cm.o.s. chip. Very good power supply rejection has beenmeasured on an integrated prototype. The method can beused for supply-independent biasing and possibly for

reducing the effect of the unpredictability of the threshold-voltage value on circuit performance.

7 References

1 TSIVIDIS, Y.P., and ULMER, R.W.: lA CMOS reference voltagesource', Digest of Technical Papers, International Solid-StateCircuits Conference, San Francisco, Feb. 1978, pp. 48-49

2 PENNEY, W.M., and LAU, L. (Eds): 'MOS integrated circuits'(Van Nostrand Reinhold, New York, 1972), p. 71

3 TSIVIDIS, Y.P.: 'Design considerations for single-channel MOSintegrated circuits-a tutorial', IEEE J. Solid-State Grcuits,1978, SC-13, pp. 383-391

European Journal of Operational Research

Special issue on locational decisions

CALL FOR PAPERS

The usual features of locational problems are comprehended by the inquiry: where to locate, in a given space, a number offacilities providing one or more goods or services so as to optimise one or more objective functions, subject to constraints. Anoperational research problem becomes locational decision when the question 'where?' plays an important role in it. Almost allthe work on optimal location of facilities has taken place over the last two decades. This special issue of EJOR will be thefirst one, in the operational research literature, to be entirely devoted to locational decisions.

Area of interest: The following types of articles are particularly sought:(a) Review articles: Comprehensive guides to relevant literature, including annotated bibliographies and critical assessments ofthe merits of various methods. Articles may cover a particular methodological or functional area.(b) Applications: Studies reporting significant applications (including instructive failures), of existing locational decisionmethods.(c) New methodology or theory: Analytic and algorithmic development of potential use in the practice of locationaldecisions.

Submission of papers: All articles will be subject to the normal refereeing process of EJOR. Authors of review articles areencouraged to contact the editor as early as possible. In general, papers should be limited to twenty double-spaced type-written pages, but exceptions may be made for papers of unusual quality. To be considered for inclusion in the special issue,papers should be submited by 1st June 1979. Reviewing of papers will however be initiated immediately upon their reception.

All enquiries on manuscripts should be addressed to Professor Jonathan Halpern, Editor, Locational decisions special issue,Faculty of Management, The University of Calgary, Calgary, Alberta, Canada T2N 1N4 (until July 1979) or Faculty ofIndustrial and Management Engineering, Technion, Haifa, Israel (after July, 1979).

L. Chua's research interests are in theareas of general nonlinear networkand system theory. He has been aconsultant to various electronics ind-ustries in the area of nonlinear net-work analysis, modelling andcomputer-aided design. He is the authorof the book 'Introduction to nonlinearnetwork theory', published by theMcGraw-Hill Book Company in 1969,and a co-author of the book 'Computer-

aided analysis of electronic circuits: algorithms andcomputational techniques', published by Prentice Hall in1975. He has also published many research papers in thearea of nonlinear networks and systems.

Y.W. Sing was born in Hong Kong in1954. He received his B.S. degree inelectrical engineering from theNational Taiwan University in 1975and his M.S. degree in electricalengineering from the University ofCalifornia, Berkeley, in 1977. Atpresent, he is a Ph.D. candidate withthe electrical engineering departmentat Berkeley. In 1975, he was a teachingassistant at the University of Cali-

fornia. From 1976 to 1977 he was a research assistant atthe Electronic Research Laboratory, University of Cali-fornia. In 1977 he joined Raytheon Company, Semi-conductor Division as a member of the technical staff. Hiscurrent interests are nonlinear electronic device modelling,semiconductor device physics and computer-aided circuitdesign.

ELECTRONIC CIRCUITS AND SYSTEMS, JANUARY 1979, Vol. 3, No. 1


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