Thru-Wafer Interconnects for Double-Sided(TWIDS) Fabrication of MEMS

Alexandra Efimovskaya, Yu-Wei Lin, and Andrei M. ShkelMicroSystems Laboratory, University of California, Irvine, CA 92697, USA

Email: {aefimovs, yuweil4, ashkel}@uci.edu

Abstract—This paper reports a new approach for fabrication

of high-aspect ratio low resistance vertical interconnects, provid-

ing an electrical interface between the front-side and the back-

side of the Silicon-on-Insulator (SOI) wafer. The method of Thru-

Wafer Interconnects for Double-Sided (TWIDS) fabrication of

MEMS is based on seedless copper electroplating, and allows

for voids free features and high aspect ratio (copper diameter

to wafer thickness ratio is 10:1). We introduced the fabrication

sequence, implemented and characterized prototypes of a MEMS

toroidal ring gyroscope with thru-wafer interconnects, thus

illustrating the process feasibility. Furthermore, the critical issue

of mechanical stability in air-gap interconnect structures under

15,000 g shock was investigated using 3D Finite Element Analysis

(FEA) models. Our simulations revealed that a partial filling

the gaps with Parylene C allows for 1.55x improvement in

mechanical stability without a significant increase in via parasitic

capacitance values.

INTRODUCTION

The vertical thru-wafer electrical interconnects have re-cently gained a lot of interest in semiconductor industry due tocompatibility with wafer-level packaging and multi-layer 3Dpackaging of MEMS and CMOS, as well as due to suitabilityof the approach for high-g shock environments. Packaging ofMEMS sensors requires thru-wafer interconnects with high-aspect ratio, low resistivity, and low parasitic capacitance.

Several techniques for fabrication of vertical interconnectshave been reported in literature, including single-crystal sil-icon vias, [1], polysilicon-filled vias, [2], and electroplatedmetal-filled vias, [3]. In most cases, silicon interconnects havehigher resistance due to the lower conductivity of silicon ver-sus metals. Electroplated metal-filled vias are typically formedby etching the vertical via holes, followed by deposition ofan insulating layer, a seed layer, and metal electroplating.

Although thru-wafer metal vias reported earlier have showna satisfactory performance, the realization of high aspect ratiointerconnects (better than 10:1) remains a challenge. In highaspect-ratio via filling, void formation inside the via filling is acommon problem. The main complication in the fabrication ofmetal, e.g. copper electroplated interconnects, is uneven fillingof the narrow and deep holes due to non-uniform deposition ofa seed layer. Insufficient wettability of via sidewalls and poorelectrolyte chemistry are some of the other reasons behind thevoids formation.

In this paper, we present a technology of thru-wafer in-terconnects, which is based on the bottom-up seedless copperelectroplating and allows for void-free high-aspect ratio struc-

Fig. 1. High-density array of copper electroplated thru-wafer interconnectsfor MEMS double-sided process (TWIDS).

tures, Fig.1. Our method enables co-fabrication of MEMS SOIsensors with low-resistance copper thru-wafer interconnects.

PROCESS FLOW

TWIDS fabrication process, [4], starts with a 600 µm thickSOI wafer with a thin 1 µm layer of low-stress silicon nitrideon the handle side, Fig.2(a). The approach involves DeepReactive Ion Etching (DRIE) of the blind thru-wafer holes,using a buried oxide layer as a stopper, Fig.2(b). Etchingis followed by removal of oxide and filling the holes withcopper, using a seedless electroplating method which doesnot require a conductive seed layer deposition and utilizesa highly doped silicon device layer to initiate the bottom-up plating process, Fig.2(c,d). Electroplating is performedin a custom-designed plating setup, consisted of a 4 inchcopper electrode, an Elmasonic P 120H Ultrasonic unit, a DCpower supply, and a bath with copper electrolyte (provided byTRANSENE, USA). The total electroplating time to fill the500 µm deep vias is approximately 25 hr with a maximumcurrent of 8 mA. To improve the quality of the filling, theultrasound sonication in the range of 37 kHz is used duringthe first 10 min of the plating process. Silicon nitride actsas a barrier layer to prevent parasitic copper growing on thehandle side of the wafer. Once plating is complete, the waferis lapped and insulating gaps are DRIE etched around thecopper-filled vias. Next, the SOI sensor’s features are definedon the front side of the wafer, Fig.2(e,f).

DESIGN AND FABRICATION

The TWIDS were designed for integration with SOI MEMSinertial sensors. 3D packaging of MEMS devices requires high

Fig. 2. TWIDS fabrication process: (a) SOI wafer, (b) thru-wafer via DRIE etch, (d) seedless copper electroplating and lapping, (e) defining insulating gaps,(f) sensor DRIE etch and release.

density array of interconnects with low resistance and lowparasitic losses, assuring a low impedance path for electricalsignals [5].

Fig. 3. Theoretical resistance and parasitic capacitance values for TWIDSas a function of diameter of copper-filled via

Theoretical resistance values for TWIDS are calculated asresistance of copper cylinder with a length of 500 µm andwith a diameter in the range of 40 µm to 130 µm and parallelresistance of hollow Si cylinder with the wall thickness in therange of 20 µm to 35 µm. Fig. 3a) depicts the total theoreticalresistance of TWIDS as a function of the copper via. Theactual resistance of copper electroplated interconnects mightbe larger than bulk copper. An excess resistivity is associatedwith defects in electroplated film, [6]. The total resistanceacross the vertical interconnect also includes connected inseries the resistance of a sensor contact pad. For the 380 µmcontact pads with 100 µm diameter copper via the calculatedtheoretical value of the total resistance is 22 m⌦. The exper-imental value of the resistance across the 100 µm diametercopper via with a 380 µm contact pad was identified using afour-wire resistance measurement method, [4]. The measuredvalue was less than 190 m⌦.

TWIDS parasitic capacitance arises primarily from coppervias, surrounded by insulating gaps and forming capacitorswith the silicon substrate. Excess parasitic capacitance can

lead to signal degradation, especially in high-frequency appli-cations. Substrate coupling capacitance values were calculatedas a function of the copper via diameter with a 35 µm donut-shaped air gap, Fig. 3b). The maximum value of 79 fF perinterconnect was calculated for 130 µm diameter via. Isolationby filling the gaps with insulating material, such as siliconnitride or parylene, is also possible. The filling may improvethe mechanical stability of interconnects, as shown in thispaper. The filling of gaps, however, results in an increasedparasitic capacitance of interconnects, Fig. 3b).

TWIDS with copper diameter in the range of 60 to 130 µmwere fabricated, Fig.4. The interconnects can be utilized forsensors with contact pads as small as 200 µm by 200 µm.Further reduction of the via is limited by the DRIE etch aspectratio, which is currently 16:1.

Fig. 4. Optical Microphotograph of the 60 µm diameter copper electroplatedthru-wafer interconnect

Prototypes of a miniature 3.3 mm by 3.3 mm MEMStoroidal ring gyroscope, [7], with 100 µm diameter copperinterconnects (copper diameter to wafer thickness up to 6:1)were fabricated using the TWIDS process, Fig.5. ScanningElectron Microscope (SEM) analysis was performed on thecross section of the electroplated thru-wafer vias and a con-tinuous voids-free filling was demonstrated, Fig.6.

EXPERIMENTAL RESULTS

Frequency response characterization of the sensors wasperformed using a custom-built test-bed, a Signatone probestation, and a set of probes for electrical connection of the

Fig. 5. A Prototype of MEMS toroidal ring gyroscope with co-fabricatedTWIDS: a) front-side (device) view, b) back-side (interconnect) view.

Fig. 6. SEM image of the MEMS inertial sensor with co-fabricated 100 µmdiameter copper thru-wafer interconnects, showing voids-free features.

device contact pads to the electronic PCB board. The test-bed with a holder allows for testing the prototypes, usingexcitation/detection thru the top electrodes, when the sensoris ”proof-mass-up”, or thru the vertical interconnects, whenthe sensor is flipped, ”proof-mass-down”.

For the sensor excitation, a DC voltage of 24.8 V wasapplied to the proof mass and 1.5 V AC signal was applied tothe drive electrodes. A series of experimental sweeps of thesame sensor were obtained, using excitation/detection thru thetop electrodes and thru the vertical interconnects, Fig.7.

The observed distortion of the frequency response is causedby the parasitic feedthrough currents, including TWIDSsubstrate coupling capacitance, pad-to-substrate capacitance,probe-to-probe capacitance, and PCB board parasitic capaci-tance. In order to identify the main source of the parasitics,we performed an analytical analysis of the transfer function ofthe overall system, including the parasitic effects, [8]. Shownin Fig.7, parasitic terms Cp (total capacitance in parallel withthe sensor) and Rp (total parasitic resistance) were identifiedby examining the real and imaginary parts of a series ofexperimentally obtained responses.

The mean value of parasitic capacitance extracted fromthe frequency sweeps, obtained with excitation thru via was1535 fF. The identified value of Rp was 2.2 M⌦. The meanvalue of parasitic capacitance extracted from the series offrequency sweeps, obtained with excitation thru top electrodeswas 1407 fF. This suggests that TWIDS parasitic contributioninto the response distortion was significantly lower that totalparasitics of the setup.

Fig. 7. Series of experimental sweeps of the sensor, obtained using excitationthru the top electrodes and thru vias.

To remove parasitic effects from the sensor output, the car-rier demodulation technique was used, [8]. For that purpose,a high-frequency carrier signal of 100 kHz and amplitudeof 0.5 V was applied to the structure. Frequency sweeps,obtained using excitation thru the top electrodes and thru vias,showed a good match, Fig.8.

Fig. 8. Frequency sweeps, obtained using carrier demodulation technique,showed a good match between excitation/detection thru device-side andinterconnect side.

MECHANICAL STABILITY

Limitations of the TWIDS technology are related to themechanical stability of the structure, that can be compromiseddue to a high-density array of insulating air gaps. The wafer-level mechanical reliability during the post-processing is a

Fig. 9. Normalized principle stress in a die under 15000 g shock as a functionof via diameter.

concern since once the integrity is lost, the wafers are proneto breakage [9]. The mechanical reliability of individual diesat the packaging assembly level, as well as during shock andvibrations is also an important issue.

The solution is sought in filling the insulating trenches by adielectric material, such as Parylene C or silicon nitride. Thechoice of the filling material depends on vias applications andis a trade-off between the electrical, thermal, and mechanicalproperties of the interconnects. Parylene C, which has lowrelative permittivity of 3.1, is a good candidate for gaps filling.It is applied at room temperature and does not introduceany concerns for thermomechanical reliability of copper via.Moreover, Parylene deposition rate (about 5 µm/hr) is com-paratively high, making it a suitable material for filling evenlarge gaps (up to 35 µm).

Finite Element Method was used to analyze mechanicalstability of via with the air gap and the insulator-filled gap.A model of a 3.3 mm by 3.3 mm silicon die with 600 µmthickness and 315 µm spacing between the vias was built.Stress distributions under shock with amplitude of 15000 gwere calculated for via diameter in the range from 70 µm to130 µm. We considered three cases: via with the 35 µm airgap, via with the gap fully filled with Parylene C or siliconnitride, and via with the gap partially filled with Parylene.Simulations showed that the maximum stresses are locatedat the point of via attachment to the contact pad and at thebonding interface, Fig. 9. Presented data is normalized to thevalues for solid wafers without via. Our study revealed thatfilling the gaps with parylene allows to reduce the stresses atthe bonding interface by more than 2.2 times.

As discussed earlier, the filling of gaps results in an in-creased parasitic capacitance of interconnects, which may leadto significant signal degradation, especially in high frequencyapplications. In this case, an alternative approach where gapsare only partially filled with insulating material can be uti-lized. For example, partial filling of the gaps with Parylene Callows for 1.55x improvement in mechanical stability without

a significant increase in via parasitic capacitance value (byless than 22 fF).

CONCLUSION

A novel approach for fabrication of high-aspect ratio lowresistance copper thru-wafer interconnects was presented. Themethod is compatible with a standard SOI process and allowsfor voids free features and high aspect ratio (copper diameterto wafer thickness up to 10:1). We implemented and character-ized prototypes of an SOI MEMS toroidal ring gyroscope withco-fabricated 6:1 aspect ratio thru-wafer interconnects. Theseries of experimental sweeps obtained with excitation thrutop electrodes and thru interconnects, verified the feasibilityof TWIDS technology. Furthermore, using FEA models, weinvestigated the mechanical stability of interconnects with air-gap and insulator-filled gap TWIDS under 15,000 g shock.Our simulations revealed that partial filling of the gaps withParylene C allows for 1.55x improvement in mechanical sta-bility without a significant increase in via parasitic capacitancevalue.

Due to the high aspect-ratio, low resistance and low para-sitic capacitance, TWIDS technology may find a wide scopeof applications, including 3D packaging of MEMS inertialsensors and RF MEMS.

ACKNOWLEDGMENT

This material is based upon work supported by DARPAgrant N66001-13-1-4021 (Program Manager Dr. Robert Lut-wak). Devices were designed, developed, and tested at UCIMycroSystems Laboratory. Authors would like to thank UCIINRF staff Jake Hes, and Mo Kebaili for their help andvaluable suggestions on the fabrication aspects of the project.

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