Thuc tap DSP KIT c6713

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TMS320C6416/C6713 DSK One-Day Workshop

Student Guide

Revision 3.1 – August 2003Technical TrainingOrganization

TTO

Notice Creation of derivative works unless agreed to in writing by the copyright owner is forbidden. No portion of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written permission from the copyright holder.

Texas Instruments reserves the right to update this Guide to reflect the most current product information for the spectrum of users. If there are any differences between this Guide and a technical reference manual, references should always be made to the most current reference manual. Information contained in this publication is believed to be accurate and reliable. However, responsibility is assumed neither for its use nor any infringement of patents or rights of others that may result from its use. No license is granted by implication or otherwise under any patent or patent right of Texas Instruments or others.

Revision History October 1999 – Version 1.0 (C6211 DSK) November 1999 – Version 1.1 November 2000 – Version 2.0 (C6711 DSK) March 2001 – Version 2.1 August 2001 – Version 2.2 (CCS v2.0) June 2003 – Version 3.0 (C6416/C6713 DSK and CCS v2.2) August 2003 – Version 3.1

Copyright 1999-2003 by Texas Instruments, Incorporated. All rights reserved.

For more information on TI Semiconductor Products, please call the SC Product Information Center at (972) 644-5580 or email them at [email protected].

C6416/C6713 DSK One-Day Workshop 0 - 1

C6416/C6713 DSK One-Day Workshop

Introduction The C6000 One-Day Workshop introduces you to the C6000 architecture, peripherals, and tools. In one day, we can’t make you a C6000 expert, though after this workshop you should be able to:

• Recognize the various peripherals of the C6000 family and determine which peripherals are on given device. • Describe the basic capabilities of the EDMA, McBSP, and HPI peripherals. • Enable the double-level cache. • Explain the concept of Software Pipelining and its value. • Create a CCS project; build and run a C program • Explain the –mv, -g, -gp, and –o compiler options. Choose settings for debug and code optimization. • Use the TI Software Foundation libraries (CSL, BIOS, DSPLIB, IMGLIB) in a CCS project. • List the benefits of TI’s system software tools and standards (XDIAS, IOM, RF). • Install the C6416 (or C6713) DSK hardware and software; and, run the included diagnostic utility.

Along with the Welcome introduction, this course consists of four chapters as outlined below. Each chapter concludes with a lab exercise, giving you the opportunity to observe and practice the topics discussed in class.

Workshop Outline

WelcomeIntroduction to C6000 and Code Composer Studio (CCS)Using C6000 PeripheralseXpressDSP – TI’s System SolutionOptimizing C6000 Code

Agenda

0 - 2 C6416/C6713 DSK One-Day Workshop

Chapter Topics C6416/C6713 DSK One-Day Workshop.................................................................................................. 0-1

Agenda .................................................................................................................................................... 0-3 Please Introduce Yourself ....................................................................................................................... 0-4 TI DSP and ‘C6x Family Positioning ..................................................................................................... 0-5

Applications / System Needs .............................................................................................................. 0-5 TI DSP Families ................................................................................................................................. 0-6

C6000 Roadmap...................................................................................................................................... 0-8 For More Information and Support ........................................................................................................ 0-9 Key C6000 Literature ............................................................................................................................0-10 For Information about Digital Signal Processing ….............................................................................0-11 … Textbooks on using the C6000 … ......................................................................................................0-11 … and finally, Workshops from TI .........................................................................................................0-12

Agenda


Agenda Today’s Agenda

8:30 - 9:00 Welcome9:00 - 11:00 Intro to C6000 and CCS

Lab 1: Generate and Graph a Sine Wave Algorithm

11:00 - 1:00 Using C6000 PeripheralsLab 2: Output Sine tone via the DSK’s Audio Codec(Break for lunch during this lab)

1:00 - 2:15 eXpressDSP – TI’s System SolutionDemo: Examine eXpressDSP using TI Reference Framework 3

(IOM drivers, XDAIS algorithms, and Real-Time Analysis)

2:15 - 4:00 Optimizing C6000 CodeLab 4: Optimize Image Correlation routine –

Using C Optimizer, DSP Image Library, and On-chip Cache

4:00 - 4:30 Wrap Up

As noted above, you will have lunch sometime during Chapter 2. Your facilitator will provide breaks as needed throughout the day.

Please Introduce Yourself


Please Introduce Yourself The following questions will help your facilitator better understand the general level of understanding for the class.

Introduce Yourself

A Show of Hands...Do you have experience with:

TI DSP’s (TMS320)Another DSPOther microprocessors

Will you use C, Assembly, or bothWho has used an OS or RTOS?Which C6000 DSP do you plan to use?

The two acronyms from above: • OS: Operating System • RTOS: Real-Time Operating System

While most engineers have used an operating system (e.g. Mac OS, Windows, Unix), many embedded system designers have never developed an application that included an operating system. Understanding the group’s level of OS knowledge may assist your facilitator during the eXpressDSP chapter and demo.

TI DSP and ‘C6x Family Positioning



Applications / System Needs DSP systems today face a host of system needs:

PerformanceInterfacingPower

Size

Ease-of Use• Programming• Interfacing• Debugging

Integration• Memory• Peripherals

Cost• Device cost• System cost• Development cost• Time to market

System Considerations

These needs challenge the designer with a series of tradeoffs. For example, while performance is important in a portable MP3 player, more important would be efficiency of power dissipation and board space. On the other hand, a cellular base station might require higher performance to maximize the number of channels handled by each processor.

Wouldn’t it be nice if the fastest DSP consumed the lowest amount of power? While TI is working on providing this (and making it software compatible), our goal is to provide you with a broad assortment of DSP families to cover a varying set of system needs. Think of them as different shoes for different chores …



TI DSP Families TI provides a variety of DSP families to handle the tradeoffs in system requirements.

Different Needs? Multiple Families

Lowest CostControl Systems

SegwayMotor ControlStorageDigital Ctrl Systems

C2000(C20x/24x/28x)

‘C1x ‘C2x

C6000(C62x/64x/67x)

‘C3x ‘C4x ‘C8x

Multi Channel and Multi Function App'sWireless Base-stationsDSLImaging & VideoHome TheaterPerformance AudioMulti-Media ServersDigital Radio

Max Performancewith

Best Ease-of-UseEfficiencyBest MIPS per

Watt / Dollar / SizeWireless phonesInternet audio playersDigital still cameras ModemsTelephonyVoIP

C5000(C54x/55x/OMAP)

‘C5x

The TMS320C2000 (‘C2000) family of devices is well suited to lower cost, microcontroller-oriented solutions. They are well suited to users who need a bit more performance than today’s microcontrollers are able to provide, but still need the control-oriented peripherals and low cost.

The ‘C5000 family is the model of processor efficiency. While they boast incredible performance numbers, they provide this with just as incredible low power dissipation. No wonder they are the favorites in most wireless phones, internet audio, and digital cameras (just to name a few).

Rounding out the offerings, the ‘C6000 family provides the absolute maximum performance offered in DSP. Couple this with its phenomenal C compiler and you have one fast, easy-to-program DSP. When performance and/or time-to-market counts, the ‘C6000 is the family to choose. It also happens to be the family this course was designed around, thus, the rest of the workshop will focus on it.



Millions shipped to hundreds of customers

World’s highest-performance DSPShipping at 720MHzSampled at 1GHz

Heart of solutions for new, high-bandwidth communications and video equipment

Wireless basestations and transcodersDSLHome theater audioIBOC digital radioImaging and video servers & gateways

New generation C64x DSP products fully code compatible

C64xTM DSP

Best DSP of 2001InStat/MicroDesignResources

2001 Innovation of the YearEDN Magazine

13 Products AUP: $9.95 - $250

C6000TM DSPTI DSPPlatforms

TI DSPPlatforms

Heart of advanced embedded control applications

Hard Disk Drive Servo ControlDigital Motor Control in White GoodsHVAC Motor ControlUn-interruptible Power Supply PFC Optical Lasers

New generation C28xTM DSP products fully code compatible

Tens of millions shipped to thousands of customers

47 ProductsAUP: $3 - $15

World’s most code-efficient DSP C28xTM DSPIn one of 2001’s Most Innovative ProductsSegway: Human Transporter

Leadership integration of analog and high speed Flash memory

C2000TM DSP

World’s most popular DSP ISAHundreds of millions shipped to thousands of customers

Heart of handheld solutions for the Internet era

Wireless terminals and OMAP™Digital Still CamerasInternet Audio playersVoIP

New generation C55xTM DSP fully code compatible

C55xTM DSP

Best DSPMicroprocessor Report

DSP Product of the Year 2001Internet Telephony

EDN 2000 Finalist

92 Products AUP: $5 - $120

World’s most power-efficient DSP

C5000TM DSPTI DSPPlatforms

C6000 Roadmap


C6000 Roadmap The ‘C6000 family has grown considerably over the past few years. With the addition of the 2nd generation of devices (‘C64x) a couple of years ago, and with the recent announcement of the upcoming 1GHz performance, the C6000 family dominates the high-end DSP market.

C62x: Fixed PointC67x: Floating PointC62x: Fixed PointC67x: Floating Point

C6000 Roadmap

Highest

Performance

Object Code Software CompatibilityFloating PointFloating Point

Multi-coreMulti-core C64x™ DSP1.1 GHz

C64x™ DSP1.1 GHz

C6201

C6701

C6202C6203

C6211C6711

C6204

1st Generation

C6713C6713

C6205

C6712

C6412C6412 DM642DM642

2nd Generation

C6415C6415

C6416C6416

C6411C6411

C6414C6414

TMS320C6000Easy to Use

Best C engine to dateEfficient C Compiler and Assembly OptimizerDSP & Image Libraries include hand-optimized codeeXpressDSP Toolset eases system design

SuperComputer Performance1.38 ns instruction rate: 720x8 MIPS (1GHz sampled)2880 16-bit MMACs (5760 8-bit MMACs) at 720 MHzPipelined instruction set (maximizes MIPS)Eight Execution Unit RISC Topology Highly orthogonal RISC 32-bit instruction setDouble-precision floating-point math in hardware

Fix and Float in the Same FamilyC62x – Fixed PointC64x – 2nd Generation Fixed PointC67x – Floating Point

Even with its growing family of devices, the ease of design with the C6000 architecture has not been abandoned. Software compatibility is addressed by the architecture, rather than by the hard-work of the programmer. With both the ‘C67x and ‘C64x devices being able to run ‘C62x object code, upgrading DSP designs is much easier.

For More Information and Support


For More Information and Support For support we suggest you try TI’s web site first. Then call your local support – either your local TI representative or Authorized Distributor Sales/FAE. Finally, here are a few other places to go:

For More Information . . .

Phone: 800-477-8924 or 972-644-5580Email: [email protected]

Information and support for all TI Semiconductor products/toolsSubmit suggestions and errata for tools, silicon and documents

USA - Product Information Center ( PIC )

Website: http://www.ti.comhttp://www.dspvillage.com

FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm Device information my.ti.comApplication notes News and eventsTechnical documentation Training

Enroll in Technical Training: http://www.ti.com/sc/training

Internet

Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm

Phone: Language NumberBelgium (English) +32 (0) 27 45 55 32France +33 (0) 1 30 70 11 64Germany +49 (0) 8161 80 33 11Israel (English) 1800 949 0107 (free phone)Italy 800 79 11 37 (free phone)Netherlands (English) +31 (0) 546 87 95 45Spain +34 902 35 40 28Sweden (English) +46 (0) 8587 555 22United Kingdom +44 (0) 1604 66 33 99Finland (English) +358(0) 9 25 17 39 48

Fax: All Languages +49 (0) 8161 80 2045Email: [email protected]

Literature, Sample Requests and Analog EVM OrderingInformation, Technical and Design support for all Catalog TISemiconductor products/toolsSubmit suggestions and errata for tools, silicon and documents

European Product Information Center (EPIC)

Key C6000 Literature


Key C6000 Literature Here is a brief summary of the C6000 manuals available from TI.

HardwareSPRU189 - CPU and Instruction Set Ref. GuideSPRU190 - Peripherals Ref. GuideSPRZ122 - SPRU190 Manual Update Sheet (important!)SPRU401 - Peripherals Chip Support Lib. Ref.SPRU609 - C67x Two-Level Internal Memory ReferenceSPRU610 - C64x Two-Level Internal Memory ReferenceSPRU656 - Cache Memory Users Guide

SoftwareSPRU198 - Programmer’s GuideSPRU423 - C6000 DSP/BIOS User’s GuideSPRU403 - C6000 DSP/BIOS API Guide

Code Generation ToolsSPRU186 - Assembly Language Tools User’s GuideSPRU187 - Optimizing C Compiler User’s Guide

Key C6000 Manuals

Please check the website for the latest versions of these and for additional manuals and applications notes.

For Information about Digital Signal Processing …


For Information about Digital Signal Processing … Looking for Literature on DSP?

“DSP Primer (Primer Series)”by C. Britton Rorabaugh; ISBN 0-0705-4004-7

“A DSP Primer : With Applications to Digital Audioand Computer Music”by Ken Steiglitz; ISBN 0-8053-1684-1

“DSP First : A Multimedia Approach”James H. McClellan, Ronald W. Schafer, Mark A. Yoder;ISBN 0-1324-3171-8

“A Simple Approach to Digital Signal Processing”by Craig Marven and Gillian Ewers; ISBN 0-4711-5243-9

… Textbooks on using the C6000 … Looking for Literature on ‘C6000 DSP?

“Digital Signal Processing Implementation using the TMS320C6000TM DSP Platform”

by Naim Dahnoun; ISBN 0201-61916-4

“C6x-Based Digital Signal Processing”by Nasser Kehtarnavaz and Burc Simsek;ISBN 0-13-088310-7

“ DSP Applications Using C and the TMS320C6x DSK”by Rulph Chassaing;ISBN 0471207543

… and finally, Workshops from TI


… and finally, Workshops from TI

http://www.ti.com/sc/training

DSP Workshops Available from TIAttend another workshop:

4-day C2000 Workshops4-day C5000 Integration Workshops4-day C6000 Integration Workshop4-day C6000 Optimization Workshop4-day DSP/BIOS Workshop4-day OMAP Software Workshop1-day versions of these workshops1-day Reference Frameworks and XDAIS

Sign up at:

C6000 Workshop ComparisonAlgorithm Coding and OptimizationSystem Integration (data I/O, peripherals, real-scheduling, etc.)

OP6000IW6000Audience

Using Peripherals (EDMA, McBSP, EMIF, HPI, XBUS)CPU Architecture & Pipeline DetailsC6000 Hardware

CSL, Hex6x, Absolute Lister, Flashburn, BSLCompiler Optimizer, Assembly Optimizer, Profiler, PBCTools

Software Pipelining LoopsDSP/BIOS, Real-Time Analysis, Reference FrameworksCreating a Standalone System (Boot), Programming DSK Flash

Calling Assembly From C, Programming in Linear AsmC Performance Techniques, Adv. C Runtime EnvironmentCoding & System Topics

You can find a more complete comparison between the two workshops in the Appendix of this book.

C6416/C6713 DSK One-Day Workshop - Intro to C6000 and CCS 1 - 1

Intro to C6000 and CCS

Introduction This chapter begins with a detailed look at the C6000 architecture. First, looking at how the C6000 generally fits into a system down to the various functional units that make up the core CPU. Using a technique called software pipelining, we can visualize how all the functional units might be able to work in parallel to achieve massive numerical performance.

The second part of this chapter introduces Code Composer Studio (CCS). After a CCS overview, we quickly examine CCS projects, C build options, and point out the DSP/BIOS Configuration Tool.

In Lab 1, you will use CCS to build and graph a sine-wave.

Outline Outline

C6000 OverviewC6000 ParallelismCCS OverviewLab: Build and Graph a SinewaveOptional Topics

CCS AutomationCPU Architecture DetailC6000 Instruction SetsBenchmarks

Connecting to a C6000 Device

1 - 2 C6416/C6713 DSK One-Day Workshop - Intro to C6000 and CCS

Chapter 1 Topics Intro to C6000 and CCS ........................................................................................................................... 1-1

Connecting to a C6000 Device ............................................................................................................... 1-3 Looking into the C6000 Device............................................................................................................... 1-8 Looking at the C6000 CPU..................................................................................................................... 1-9

What is Digital Signal Processing (DSP)?.......................................................................................... 1-9 C6000 Core CPU Architecture ..........................................................................................................1-10 C62x vs. C67x vs. C64x ....................................................................................................................1-11

Using the CPU’s Parallelism.................................................................................................................1-12 C62x Compiled Code ........................................................................................................................1-13 C67x Compiled Code ........................................................................................................................1-14 C64x Compiled Code ........................................................................................................................1-15 How many MMAC’s is that?.............................................................................................................1-16 How can we get such parallelism?.....................................................................................................1-17 Software Pipelining ...........................................................................................................................1-18

DSP Tools Overview ..............................................................................................................................1-20 C6000 DSK’s.....................................................................................................................................1-20 Code Composer Studio (CCS)...........................................................................................................1-22 CCS Projects......................................................................................................................................1-26 DSP/BIOS Configuration Tool..........................................................................................................1-29

Lab Preparation.....................................................................................................................................1-30 C64x or C67x Exercises? ..................................................................................................................1-30

Prepare Lab Workstation.......................................................................................................................1-31 Computer Login.................................................................................................................................1-31 Connecting the C6416 DSK to your PC ............................................................................................1-31 Testing Your Connection...................................................................................................................1-31 CCS Setup .........................................................................................................................................1-32 Set CCS – Customize Options...........................................................................................................1-36

LAB 1: Using Code Composer Studio....................................................................................................1-40 Sine Generation Algorithm................................................................................................................1-41

“Take Home” Exercises (Optional).......................................................................................................1-54 Lab1a – Customize CCS....................................................................................................................1-54 Lab1b - Using GEL Scripts ...............................................................................................................1-57 Lab1c – Using Printf..........................................................................................................................1-60 Lab1d – Fixed vs Floating Point........................................................................................................1-61 Lab1e – Explore CCS Scripting ........................................................................................................1-63 Lab Debrief........................................................................................................................................1-63

Optional Topics......................................................................................................................................1-64 Optional Topic: CCS Automation .....................................................................................................1-64 Optional Topic: CPU Architecture Details .......................................................................................1-68 Assorted C6000 Benchmarks ............................................................................................................1-78



Connecting to a C6000 Device C6000 devices contain a variety of peripherals to allow easy communication with off-chip memory, co-processors, and other devices. The diagram below provides a quick overview:

Example C6000 SystemClockoutTimer /

Counters

HWI

PCI

HPI

Utopia 2

McASP

McBSP

EMAC

C6000CPU

EDMA

VCP TCP

Boot Loader EMIF

ClockinClockoutx

PLL

ATM

Note: Not all ‘C6000 devices have all the various peripherals shown above. Please refer to the C6000 Product Update for a device-by-device listing.

Serial Codec

(TCP/IP stack avail)

Audio Codec/3/3

/3/3

/8

SDRAMSync

SRAMEPROM

PCI /32

EthernetHost µP /16 or 32

NMIReset

Ext Interrupts /4

/2/2

GPIO

SwitchesLamps

LatchesFPGA

Etc.

/ 0-16+

\ 16, 32, or 64-bits

Let’s quickly look at each of these connections beginning with VCP/TCP and working counter-clockwise around the diagram.

Viterbi Coprocessor (VCP) • Used for 3G Wireless applications • Supports >500 voice channels at 8 kbps • Programmable decoder parameters include constraint length, code rate, and frame length • Available on the ‘C6416

Turbo Coprocessor (TCP) • Used for 3G Wireless applications • Supports 35 data channels at 384 kbps • 3GPP / IS2000 Turbo coder • Programmable parameters include mode, rate and frame length • Available on the ‘C6416



Timer / Counters • Two (or three) 32-bit timer/counters • Use as a Counter (counting pulses from input pin)

or as a Timer (counting internal clock pulses) • Can generate:

− Interrupts to CPU − Events to DMA/EDMA − Pulse or toggle-value on output pin

• Each timer/counter as both input and output pin

General Purpose Input/Output (GPIO) • Observe or control the signal of a single-pin • Dedicated GPIO pins on ‘C6713 and all ‘C64x devices • All ‘C6000 devices have shared GPIO with unused peripheral pins

Hardware Interrupts (HWI) • Allows synchronization with outside world:

− Four configurable external interrupt pins − One Non-Maskable Interrupt (NMI) pin − Reset pin

• C6000 CPU has 12 configurable interrupts. Some of the properties that can be configured are: − Interrupt source (for example: Ext Int pin, McBSP receive, HPI, etc.) − Address of Interrupt Service Routine (i.e. interrupt vector) − Whether to use the HWI dispatcher − Interrupt nesting

• The DSP/BIOS HWI Dispatcher makes interrupts easy to use

Parallel Peripheral Interface • C6000 provides three different parallel peripheral interfaces; the one you have depends

upon which C6000 device you are using (see C6000 Product Update for which device has which interface)

HPI: Allows another processor access to C6000’s memory using a dedicated, async 16/32-bit bus; where C6000 is slave-only to host.

XBUS: Similar to HPI but provides but adds: 32-bit width, Master or slave modes, sync modes, and glueless I/O interface to FIFOs or memory (memory I/O can transfer up to full processor rates, i.e. single-cycle transfer rate).

PCI: Standard master/slave 32-bit PCI interface (latest devices – e.g. DM642 – now allow 66MHz PCI communication)



Direct Memory Access (DMA / EDMA) • EDMA stands for the Enhanced DMA

(each C6000 has either a DMA or EDMA) • Transfers any set of memory locations to any another (internal or external) • Allows synchronized transfers; that is, they can be triggered by any event (i.e. interrupt) • Operates independent of CPU • 4 / 16 / 64 channels (set’s of transfer parameters) (various by C6000 device type) • “If you are not using the DMA/EDMA, you’re probably not getting the full performance

from your ‘C6000 device.”

DMA: Offers four fully configurable channels (additional channel for the HPI), Event synchronization, Split mode for use with McBSP, and Address/count reload

EDMA: Enhanced DMA (EDMA) offers 16 fully configurable channels (64 channels on ‘C64x devices), Event synchronization, Channel linking, and Channel auto-initialization.

Boot Loader • After reset but before the CPU begins running code, the “Boot Loader” can be configured

to either: − Automatically copy code and data into on-chip memory − Allow a host system (via HPI, XBUS, or PCI) to read/write code and data into the

C6000’s internal and external memory − Do nothing and let the CPU immediately begin execution from address zero

• Boot mode pins allow configuration • Please refer to the C6000 Peripherals Guide and each device’s data sheet for the modes

allowed for each specific device.

External Memory Interface (EMIF) EMIF is the interface between the CPU (or DMA/EDMA) and the external memory and provides all of the required pins and timing to access various types of memory.

• Glueless access to async or sync memory • Works with PC100 SDRAM — cheap, fast, and easy!

(more recent designs now allow use of PC133 SDRAM) • Byte-wide data access • C64x devices have two EMIFs (16-bit and 64-bit width) • 16, 32, or 64-bit bus widths (please check the specifics for your device)



Ethernet • 10/100 Ethernet interface • To conserve cost, size and power – Ethernet pins are muxed with PCI

(you can use one or the other) • Optimized TCP/IP stack available from TI (under license)

Multi-Channel Buffered Serial Port (McBSP) • Commonly used to connect to serial codecs (codec: combined A/D and D/A devices), but

can be used for any type of synchronous serial communication • Two (or three) synchronous serial-ports • Full Duplex: Independent transmit and receive sections (each can be individually sync’d) • High speed, up to 100 Mb/sec performance • Supports:

− SPI mode − AC97 codec interface standard − Supports multi-channel operation (T1, E1, MVIP, …) − And many other modes

• Software UART available for most C6000 devices (Check the DSP/BIOS Drivers Developer Kit (DDK))

McASP • All McBSP features plus more … • Targeted for multi-channel audio applications such as surround sound systems

− Up to 8 stereo lines (16 channels) - supported by 16 serial data pins configurable as transmit or receive

− Throughput: 192 kHz (all pins carrying stereo data simultaneously) • Transmit formats:

− Multi-pin IIS for audio interface − Multi-pin DIT for digital interfaces

• Receive format: − Multi-pin IIS for audio interface

• Available on C6713 and DM642 devices.

Utopia • For connection to ATM (async transfer mode) • Utopia 2 slave interface • 50 MHz wide area network connectivity • Byte wide interface • Available on ‘C64x devices



PLL • On-chip PLL provides clock multiplication. The ‘C6000 family can run at one or more

times the provided input clock. This reduces cost and electrical interference (EMI). • Clock modes are pin configurable. • On most devices, along with the Clock Mode (configuration) pins, there are three other

clock pins: − CLKIN: clock input pin − CLKOUT: clock output from the PLL (multiplied rate) − CLKOUT2: a reduced rate clockout. Usually ½ or less of CLKOUT Please check the datasheet for the pins, pin names, and CKKOUT2 rates available for your device.

• Here are the PLL rates for a sample of C6000 device types: Device Clock Mode Pins PLL Rate C6201 C6204 C6205 C6701

CLKMODE x1, x4

C6202 C6203

CLKMODE0 CLKMODE1 CLKMODE2

x1, x4, x6, x7, x8, x9, x10, x11

C6211 C6711 C6712

CLKMODE x1, x4

C6414 C6415 C6416

CLKMODE0 CLKMODE1 x1, x6, x12

Power Down • While not shown in the previous diagram, the ‘C6000 supports power down modes to

significantly reduce overall system power.

For more detailed information on these peripherals, refer to the ‘C6000 Peripherals Guide.

Looking into the C6000 Device


Looking into the C6000 Device Going from the system connection to looking inside the C6000 device, along with each of the peripherals just discussed, we find the CPU and a number of internal busses.

As an example, here is an internal view of the C6414 device:

C6415 DSP (720MHz)

L2 Mem

ory

PLLPower Down Logic

JTAGRTDX

Enhanced DM

A C

ontroller (64 channels)

McBSP 0

McBSP 1

Utopia 2Utopia 2

EMIF 64

EMIF 16

McBSP 2

HPI / PCI133 MB/s

12.5 MB/s

12.5 MB/s

100 MB/s

1064 MB/s

266 MB/s

12.5 MB/s

C64xTM

CPU Core5760 MIPS

11.5 GB/s

23 GB/s

2.9 GB

/s

Timer 2Timer 1Timer 0

L1P Cache11.5 GB

/s

L1D Cache

11.5 GB

/s

or

From this diagram notice two things: • Dual-level memory (this will be discussed further in Chapter 4):

− L1 (level 1) program and data caches − L2 (level 2) combined program/data memory

• High-performance, internal buses − Buses as large as 64- and 256-bits allow an enormous amounts of info to be moved − Multiple buses allow simultaneous movement of data in a C6000 system − Both the EDMA and CPU can orchestrate moving information

Note: While we have looking into the C6414, you can extrapolate these same concepts to other C6000 device types. All device types have multiple, fast, internal buses. Most have a dual-level memory architecture, while a few have a single-level, flat memory.

Looking at the C6000 CPU


Looking at the C6000 CPU Before looking at the make-up of the C6000 CPU, let’s quickly review, “What is DSP?”. This will allow us to better see how/why the CPU was designed in a specific way.

What is Digital Signal Processing (DSP)? If asked, engineers come up with many definitions for DSP. Some include:

• Converting a signal from analog to digital, then processing it using software. • Numerical analysis of signals. • Performing traditional signal processing algorithms (filters, FFT’s, etc.). • Processing data within a time-limited duration; that is, executing code under real-time constraints. • And so on …

What Problem Are We Trying To Solve?

Digital sampling of an analog signal:

A

t

Most DSP algorithms can be expressed with MAC:

count

i = 1Y = Σ coeffi * xi

for (i = 0; i < count; i++){sum += c[i] * x[i]; }

DACx YADC DSP

Practically, it’s probably all of them. To summarize, you might say DSP is the processing of digital signals numerically, usually with real-time constraints.

Looking more carefully at the algorithms used in Digital Signal Processing, we almost always find it takes the form shown above. Often this form is called Sum of Products (SOP), or Multiply Accumulate (MAC). The first Digital Signal Processors (also abbreviated DSP) were derived from a standard 16-bit microprocessor. In order to meet the goals of DSP, though, they took on characteristics of RISC processing that ensured instructions executed in a single-cycle (not too common in those days). Also, they included hardware multipliers, which replaced at least 32 microcode instructions with a fast, single-cycle multiply. Further, their addressing capabilities were enhanced to allow quick and easy processing of the streaming data (usually collected into data buffers).

In many ways, DSP’s today – like the C6000 - are not that different from their forefathers. Then again, fast clock frequencies, wider buses, more registers and memory, and an architecture designed to efficiently operate C code make them vastly superior.



C6000 Core CPU Architecture Here’s a quick peek into the C6000 core CPU:

'C6000 CPU ArchitectureMemory

‘C6000 Compiler excels at Natural CWhile dual-MAC speeds math intensive algorithms, flexibility of 8 independent functional units allows the compiler to quickly perform other types of processingAll ‘C6000 instructions are conditional allowing efficient hardware pipelining‘C6000 CPU can dispatch up to eight parallel instructionseach cycle

A0

A31

..A15

..

.S1.S1

.D1.D1

.L1.L1

.S2.S2

.M1.M1 .M2.M2

.D2.D2

.L2.L2

B0

B31

..B15

..

Controller/DecoderController/Decoder

Dual MACs

Let’s point out a few things: • The C6000 architecture was co-developed with its C compiler. The CPU was designed for the

C language from the “ground-up” • All eight functional units can receive their own 32-bit instruction on every cycle. We might

say it another way, “we can execute eight instructions in parallel”. • The ability to control each execution unit independently is why the C6000 architecture is

often likened to VLIW (very long instruction word). • Both the C6000 architecture (called VelociTI – “velocity”) and VLIW allow such

granularity in how they control the individual functional units. − This is not possible with standard DSP (or GPP) architectures, where one single instruction controls all the functional

units at once. − For example, on other DSP processors, the only way to get all the functional units working all at the same time is to

use a MAC type instruction. In all other instructions, only a subset of functional units will operate. − Even if you have other things that could be done simultaneously, there is no way to tell the processor how to make

this happen.

• Unlike the C6000, though, VLIW architectures require and instruction code for each functional unit on every cycle. This often means that millions of NOP instructions are added to the program code. Due to the efficiency of the C6000 VelociTI architecture, these excess NOPs are not required.

For a more detailed explanation of the CPU building blocks, please refer to the CPU Architecture optional topic. Optionally, you may want to consider taking the 4-day, C6000 Optimization Workshop.



C62x vs. C67x vs. C64x Here’s a very quick synopsis of the various C6000 families.

Instruction Decode

Instruction Dispatch

Instruction Fetch Control Registers Interrupt C

ontrol

Emulation

Registers (B0 - B15)

D2+

M2

X

S2++

L2+

Registers (A0 - A15)

D1+

M1

X

S1++

L1+

Advanced Instruction Packing Advanced

Emulation

Registers (B16 - B31)Registers (A16 - A31)

+xxxxX +

+

+++

+xxxx X+

+

+++

This CPU block diagram shows the C64x. This block diagram can be converted to the C62x block diagram by removing the elements in light-colored boxes:

• Advanced Instruction Packing • Advanced Emulation • Registers A16-A31 and B16-B31 • Enhanced fixed-point instruction set (i.e. C64x is a super-set of the C62x instructions).

The light-colored boxes added to each functional-unit demonstrate the additional “packed-data” instructions provided only provided by the C64x.

The C67x block diagram is the same as the C62x diagram. The primary differences between these two are:

• C67x has 64-bit wide data-load buses • C67x functional-units include 32-bit single-precision (and 64-bit double-precision)

floating-point hardware. All other instructions are exactly the same.

Using the CPU’s Parallelism


Using the CPU’s Parallelism Here’s a quick look at a simple sum-of-products (Multiply-ACcumulate) loop written in linear assembly code.

Given this simple loop …y =

40

∑ cn xnn = 1

*

MVK .S1 40, cntloop:

LDH .D1 *cp++, cLDH .D1 *xp++, xMPY .M1 c, x, prodADD .L1 y, prod, ySUB .L1 cnt, 1, cnt

[cnt] B .S1 loopSTW .D y, *yp

cx

prody

cnt

*cp*xp*yp

.M1 .M1

.L1 .L1

.S1 .S1

.D1 .D1

short mac(short *c, short *x, int count) {for (i=0; i < count; i++) {sum += c[i] * x[i]; } …

Given our eight functional units, don’t you think we could perform some of these operations in parallel?



C62x Compiled Code Sure, on the C62x the compiler can achieve 2 results per cycle with 8 instructions executing in parallel.

L2: ; PIPED LOOP PROLOG

LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7

LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7

[B0] B .S1 L3 || LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7

[B0] B .S1 L3|| LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7

[B0] B .S1 L3|| LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7

MPY .M2 B7,A3,B4|| MPYH .M1 B7,A3,A5|| [B0] B .S1 L3|| LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7

MPY .M2 B7,A3,B4|| MPYH .M1 B7,A3,A5|| [B0] B .S1 L3|| LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7;** -----------------------*L3: ; PIPED LOOP KERNEL

ADD .L2 B4,B5,B5|| ADD .L1 A5,A0,A0|| MPY .M2 B7,A3,B4|| MPYH .M1 B7,A3,A5|| [B0]B .S1 L3|| [B0]SUB .S2 B0,1,B0|| LDW .D1 *A4++,A3|| LDW .D2 *B6++,B7;** -----------------------*

C62x Intense Parallelismshort mac(short *c, short *x, int count) {

for (i=0; i < count; i++) {sum += c[i] * x[i]; } …

Given this C codeThe C62x compiler can achieve Two Sum-of-Products per cycle

Given this C codeThe C62x compiler can achieve Two Sum-of-Products per cycle

Notice a few things: • Parallel bars “||” indicate that an assembly instruction is performed at the same time as

the previous instruction. − Hence, in our loop kernel, 8 instructions are performed in parallel.

Thereby using all 8 functional units. − Order of instructions is unimportant as they all get executed at once. − The rest of the code shown on this slide is used to ‘setup’ the loop.

• Two multiplies and two adds (i.e. two MACs) are performed each cycle. This gets us our two MACs per cycle.

• The “[BO]” indicates the branch (and subtract) are performed conditionally. That is, the branch to label L3 will only occur if B0 is non-zero. − All C6000 instructions (except NOP and IDLE) are conditional. This makes for fast,

code-execution on hardware pipelined processors – such as the C6000 devices.

Note: By the way, the C6000 toolset includes an Assembly Optimizer. This tool takes the linear assembly code (shown back one figure) and creates code similar to the compilers, highly-optimized standard assembly code.



C67x Compiled Code The C67x can accomplish the same rate of performance as the C62x, but does it with two 32-bit floating-point instructions done in parallel. This is where the C67x’s 64-bit internal bus (via the LDDW instruction) really pays off. It’s required in order to achieve this kind of throughput on 32-bit wide data.

C67x MAC using Natural C

;** --------------------------------------------------*LOOP: ; PIPED LOOP KERNEL

LDDW .D1 A4++,A7:A6|| LDDW .D2 B4++,B7:B6|| MPYSP .M1X A6,B6,A5|| MPYSP .M2X A7,B7,B5|| ADDSP .L1 A5,A8,A8|| ADDSP .L2 B5,B8,B8|| [A1] B .S2 LOOP|| [A1] SUB .S1 A1,1,A1;** --------------------------------------------------*

float mac(float *c, float *x, int count){ int i, float sum = 0;


A0

A15

..

.M1.M1

.L1.L1

.D1.D1

.S1.S1

.M2.M2

.L2.L2

.D2.D2

.S2.S2

B0

B15

..

Controller/DecoderController/Decoder

Memory

The C67x compiler gets two 32-bit floating-point

Sum-of-Products per iteration

The C67x compiler gets two 32-bit floating-point

Sum-of-Products per iteration

Notice: • The MPYSP and ADDSP instructions – where SP stands for single-precision, 32-bit

floating-point. • LDDW is loading two 32-bit values into two consecutive 32-bit registers.

Using two LDDWs means we’re getting four SP values per cycle.

Note: To allow the code to fit on a single PowerPoint slide, we had to modify it slightly. The C67x compiler actually creates a four-cycle loop that performs eight MACs. In other words, it’s the same rate – 2 MACs in one cycle – as we claim above, but the loop was just too large to fit on our slide.



C64x Compiled Code Even better yet, the C64x can do four MAC’s per cycle using it’s DOTP2 instruction:

C64x gets four MAC’s using DOTP2short mac(short *c, short *x, int count){ int i, short sum = 0;


;** --------------------------------------------------*; PIPED LOOP KERNELLOOP: ADD .L2 B8,B6,B6 || ADD .L1 A6,A7,A7 || DOTP2 .M2X B4,A4,B8 || DOTP2 .M1X B5,A5,A6 || [ B0] B .S1 LOOP || [ B0] SUB .S2 B0,-1,B0|| LDDW .D2T2 *B7++,B5:B4|| LDDW .D1T1 *A3++,A5:A4;** --------------------------------------------------*

A5

B5

A6

A7

x

=

+

m1 m0

n1 n0

m1*n1 + m0*n0

running sum

DOTP2

Combine this with its ability to run at 720 MHz and the C64x CPU will pump out a whopping 2880 MMAC (16-bit Mega MAC's). Heck, if all you need is 8-bit MAC's, the C64x can get twice as many – 5760 MMAC's.

What is a MMAC and how did we get the C64x doing 2880 of them?



How many MMAC’s is that? If we think of a MAC as a single Multiply-ACcumulate (multiply + add), then a million of these would be called a mega-MAC or MMAC.

In the following graphic, we see the calculation for the C6201 and C64x:

MMAC’sHow many 16-bit MMACs (millions of MACs per second) can the 'C6201 perform?

400 MMACs (two .M units x 200 MHz)

2 .M units x 2 16-bit MACs (per .M unit / per cycle)x 720 MHz----------------

2880 MMACs

How about 16x16 MMAC’s on the ‘C64x devices?

How many 8-bit MMACs on the ‘C64x?

5760 MMACs (on 8-bit data)

The C64x’s ability to perform two 16-bit multiplies (or four 8-bit multiplies) in each .M unit gives it a tremendous performance advantage.

While there is no single benchmark which does a good job of comparing different processor architectures, the number of MMAC’s probably comes the closes. Other benchmarks obfuscate the real picture (MHz, MIPs, MOPs, Dhrystone, Whetstone, FFT, etc.) – and we say this even knowing that many of these make the C6000 look better than its competition.

Note: The only true way to benchmark a processor is to compare your key real-time kernels written for each processor you are evaluating. It is the only way to the true performance you will achieve.



How can we get such parallelism? First, we’re aided by the fact that each C6000 has a double-set of functional-units. Two multipliers, ALU’s, and Data access units mean that right off the bat we should be able to get two MAC’s per cycle. (And the C64x’s DOTP instruction takes this up, yet, another level.)

But all this hardware doesn’t necessarily get us to our best performance. Figuring out how to use all this hardware is important, too.

To this end, the C6000 compiler uses a technique called Software Pipelining to get the high degree of performance previous shown.

How Do We Get Such High Parallelism?

Compiler and Assembly Optimizer use a technique called Software Pipelining

Software pipelining enables high performance (esp. on DSP-type loops)

Key point: Tools do all the work!

Software Pipelining isn’t a new technique. In fact, it’s similar to the form of hardware pipelining found in most high-performance processors available today. What stands software pipelining apart is how the instructions can be combined to build very tight loops of code.

Why don’t most other processors use software pipelining? Your architecture must have the ability to dispatch a separate instruction to each functional-unit every-cycle in order to get use this programming technique. As we mentioned earlier in the chapter, this is a capability unique to the C6000 CPU (and VLIW processors).

Let’s briefly look at examine concept of software pipelining …



Software Pipelining Software pipelining enables high performance code. The best thing, the tools do all the work. Great, but what is software pipelining? Let’s look at a simple example to demonstrate the concept...

LDH|| LDH

MPYADD

______________ cycles

How many cycles wouldit take to perform thisloop 5 times?

5 x 3 = 15

Looking at how these instructions would operate on the C6000’s eight function units:

7

1Cycle

2

3

4

5

6

Without Software Pipelining

ldh ldh

mpy

add

add

ldh ldh

mpy

ldh ldh

.M1 .M2 .L1 .L2 .S1 .S2.D1 .D2

Looking at the non-pipelined code above, you can see the inefficiency. Notice how the .D units are left unused when the first multiply occurs.

So, in seven cycles we can see we’re almost half way through the expected 15 cycles. If the code was software pipelined, though …



When software pipelining, we take advantage of the unused .D units in cycle 2 and go ahead and perform the next two loads. This allows us to pipeline the instructions resulting in a seven cycle loop – less than half the original number of cycles.

7

1Cycle

2

3

4

5

6

With Software Pipelining

ldh ldh

mpyldh ldh

addmpyldh ldh

addmpyldh ldh

addmpyldh ldh

addmpy

add

Completes in only 7 cyclesCompletes in only 7 cycles

.M1 .M2 .L1 .L2 .S1 .S2.D1 .D2

Translating the software pipelining above into code, each cycle gets a set of parallel instructions.

S/W Pipelining Translated to Code

7

1Cycle

2

3

4

5

6

.S1 .S2.D1 .D2ldh ldh

mpyldh ldh

addmpyldh ldh

addmpyldh ldh

addmpyldh ldh

addmpy

add

c1: LDH|| LDH

c2: MPY|| LDH|| LDH

c3: ADD|| MPY|| LDH|| LDH

Since most processors only allow one instruction to control all their functional units, they cannot take advantage of software pipelining. The granularity of the C6000 architecture gives it the extra flexibility to take advantage of this optimization strategy.

DSP Tools Overview


DSP Tools Overview

C6000 DSK’s

C6416 DSK

C6416 / C6713 DSK Features • TMS320C6416 DSP: 600MHz, fixed-point, 1M Byte internal RAM

or TMS320C6713 DSP: 225MHz, floating-point, 256K Byte internal RAM

• External SDRAM: 16M Bytes, C6416 – 64-bit interface C6713 – 32-bit interface

• External Flash: 512K Bytes, 8-bit interface • AIC23 Codec: Stereo, 8KHz –96KHz sample rate, 16 to 24-bit samples;

mic, line-in, line-out and speaker jacks • CPLD: Programmable "glue" logic • 4 User LEDs: Writable through CPLD • 4 User DIP Switches: Readable through CPLD • 3 Configuration Switches: Selects power-on configuration and boot modes • Daughtercard Expansion I/F: Allows user to enhance functionality with add-on

daughtercards • HPI Expansion Interface: Allows high speed communication with another DSP • Embedded JTAG Emulator: Provides high speed JTAG debug through widely

accepted USB host interface

DSP Tools Overview


Here’s a block diagram view of the C6416 DSK.

C6416 DSK

The C6713 would be almost exactly the same. (We pulled this diagram from the C6416 help file. Look in the C6713 help file <CCS Help menu> to find a similar diagram for that platform.)

DSK Diagnostic Utility

Test/Diagnose DSK hardwareVerify USB emulation linkUse Advanced tests to facilitate debuggingReset DSK hardware

DSP Tools Overview


Code Composer Studio (CCS) The Code Composer Studio (CCS) application provides all the necessary software tools for DSP development. At the heart of CCS you’ll find the original Code Composer IDE (integrated development environment). The IDE provides a single application window in which you can perform all your code development; from entering and editing your program code, to compilation and building an executable file, and finally, to debugging your program code.

SIM

Simulator

Code Composer Studio

DSK’s Code Composer Studio Includes:Integrated Edit / Debug GUI

Edit

DSK

EVM

Third Party

BIOS: Real-time kernelReal-time analysis

DSP/BIOSLibraries

DSP/BIOSConfigTool

Debug

Code Generation Tools

CompilerAsm Opto

Asm

Standard Runtime Libraries

.outLink

XDS

DSP Board

When TI developed Code Composer Studio, it added a number of capabilities to the environment. First of all, the code generation tools (compiler, assembler, linker) were added so that you wouldn’t have to purchase them separately. Secondly, the simulator was included (only in the full version of CCS, though). Third, TI has included DSP/BIOS. DSP/BIOS is a real-time kernel consisting of three main features: a real-time, pre-emptive scheduler; real-time capture and analysis; and finally, real-time I/O.

Finally, CCS has been built around an extensible software architecture which allows third-parties to build new functionality via plug-ins. See the TI website for a listing of 3rd parties already developing for CCS. At some point in the future, this capability may be extended to all users. If you have an interest, please voice your opinion by calling the TI SC Product Information Center (you can find their phone number and email address in last module, “What Next?”.)

DSP Tools Overview


Here’s a snapshot of the CCS screen:

Since it’s hard to evaluate a tool by looking at a simple screen capture, we’ll provide you with plenty of hands-on-experience throughout the week.

DSP Tools Overview


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DSP Tools Overview


Closer Look at the C6000 Code Generation Tools and File Extensions Using Code Composer Studio (CCS) you may not need to know all these file extension names, but we included a basic review of them for your reference:

Code Generation

.outEditor

.sa

AsmOptimizer

.c / .cpp

Compiler

Asm.asm

Linker.obj

Link.cmd

.map

• C and C++ use the standard .C and .CPP file extensions. • Linear Assembly is written in a .SA file. • You can either write standard assembly directly, or it can be created by the compiler and

Assembly Optimizer. In all cases, standard assembly uses .ASM. • Object files (.OBJ), created by the assembler, are linked together to create the DSP’s

executable output (.OUT) file. The map (.MAP) file is an output report of the linker. • The .OUT file can be loaded into your system by the debugger portion of CCS.

If you want to use your own extensions for file names, they can be redefined with code generation tool options. Please refer to the TMS320C6000 Assembly Tools Users Guide for the appropriate options.

DSP Tools Overview


CCS Projects Code Composer works within a project paradigm. If you’ve done code development with most any sophisticated IDE (Microsoft, Borland, etc.), you’ve no doubt run across the concept of projects.

Essentially, within CCS you create a project for each executable program you wish to create. Projects store all the information required to build the executable. For example, it lists things like: the source files, the header files, the target system’s memory-map, and program build options.

What is a Project?

Project (.PJT) file contain:References to files:

SourceLibrariesLinker, etc …

Project settings:Compiler OptionsDSP/BIOSLinking, etc …

The project information is stored in a .PJT file which is created and maintained by CCS. To create a new project, you need to select the Project→New… menu. This is different from Microsoft’s Designers Studio as they provide project new/open commands on the File menu.

Project Menu

Access via pull-down menu or by right-clicking .pjt file in project explorer window

Project MenuHint:Create and open projects from the Project menu, not the File menu.

Hint:Create and open projects from the Project menu, not the File menu.

Build Options... Next slide

DSP Tools Overview


Build Options Project options direct the code generation tools (i.e. compiler, assembler, linker) to create code according to your system’s needs. Do you need to logically debug your system, improve performance, and minimize code size? Your results can be dramatically affected by the project options available for the C6000 platform. To make it easier to choose build options, CCS provides a graphical user interface (GUI) for the various compiler options. Shown below is a capture of the Basic Compiler options.

Build Options-g -q -fr"c:\modem\Debug" -mv6700

Eight Categories of Compiler options

There is a one-to-one relationship between the items in the text box and the GUI check and drop-down box selections. Once you have mastered the various options, you’ll probably find yourself just typing in the options.

By the way, the linker page looks like:

Options Description

-o<filename> Output file name-m<filename> Map file name-c Auto-initialize global/static C variables-x Exhaustively read libs (resolve back ref's)

Linker Options

-q -c -m".\Debug\lab1.map" -o".\Debug\lab1.out" -x

.\Debug\lab1.out

Run-time Autoinitialization

By default linker options include the –o optionWe recommend you add the –m option".\Debug\" indicates one subfolder level below the projects .pjt folderRun-time Autoinit tells compiler to initialize global/static variables before calling main().\Debug\lab1.map

DSP Tools Overview


Compiler Options There are probably about a 100 options available for the compiler alone. Usually, this is a bit intimidating to wade through. To that end, we’ve provided a condensed set of options. These few options cover about 80% of most users needs.

Options Description

-mv6700 Generate ‘C67x code (‘C62x is default)-mv6400 Generate 'C64x code-fr <dir> Directory for object/output files-fs <dir> Directory for assembly files

-q Quiet mode (display less info while compiling)-g Enables src-level symbolic debugging-s Interlist C statements into assembly listing

Compiler’s Build OptionsNearly one-hundred compiler options available to tune your code's performance, size, etc.Following table lists the most common options:

debug options

In Chapter 4 we will examine the options which enable the compiler’s optimizer

We’ll add three more important options to this list in Chapter 4, when we discuss optimization.

DSP Tools Overview


DSP/BIOS Configuration Tool The DSP/BIOS Configuration Tool (often called Config Tool or GUI Tool or GUI) creates and modifies a system file called the Configuration DataBase (.CDB). If we talk about using CDB files, we’re also talking about using the Config Tool.

The following figure shows a CDB file opened within the configuration tool:

The GUI (graphical user interface) simplifies system design by: • Automatically including the appropriate runtime support libraries • Automatically handles interrupt vectors and system reset • Handles system memory configuration (builds CMD file) • When a CDB file is saved, the Config Tool generates 5 additional files:

Filename.cdb Configuration Database

Filenamecfg_c.c C code created by Config Tool

Filenamecfg.s62 ASM code created by Config Tool

Filenamecfg.cmd Linker commands

Filenamecfg.h header file for *cfg_c.c

Filenamecfg.h62 header file for *cfg.s62

When you add a CDB file to your project, CCS automatically adds the C and assembly (S62 or S64) files to the project under the Generated Files folder. (You must manually add the CMD file, yourself.)

• In the System Tools chapter, we will point out a few more CDB objects. To get all the details on this tool, we recommend you attend the 4-day DSP/BIOS Workshop.

Lab Preparation


Lab Preparation Before beginning Lab 1, you need to prepare your lab workstation. This involves: • Hooking up your DSK • Running the DSK Diagnostic Utility to verify the USB connection and DSK are working • Running CCS Setup to select the proper emulation driver (DSK vs. Simulator) • Starting CCS and setting a few environment properties

C64x or C67x Exercises? We support processor types in these workshop lab exercises. Please see the specific callouts for each processor as you work. Overall, there are very little differences between the procedures.

Lab Exercises – C67x vs. C64xWhich DSK are you using?We provide instructions and solutions for both C67x and C64x.We have tried to call out the few differences in lab steps as explicitly as possible:

Prepare Lab Workstation


Prepare Lab Workstation The computers used in TI’s classrooms and dedicated workshops may be configured for one of ten different courses. The last class taught may have been DSP/BIOS, TMS320 Algorithm Standard, or a C5000 workshop. To provide a consistent starting point for all users, we need to have you complete a few steps to reset the CCS environment to a known starting point.

Computer Login 1. If the computer is not already logged-on, check to see if the log-on information is posted on

the workstation. If not, please ask your instructor.

Connecting the C6416 DSK to your PC The software should have already been installed on your lab workstation. All you should have to do physically connect the DSK

2. Connect the supplied USB cable to your PC or laptop.

If you connect the USB cable to a USB Hub, be sure the hub is connected to the PC or laptop and power is applied to the hub.

3. Plug-in the appropriate audio connections. − Connect your headphone or speaker to the audio output. − An audio patch cable is provided to connect your computer’s soundcard (or your

music source) to the line-in connector on the DSK board.

4. Plug the AC power cord into the power supply and AC source.

Note: Power cable must be plugged into AC source prior to plugging the 5 Volt DC output connector into the DSK.

5. Plug the power cable into the board.

6. When power is applied to the board, the Power On Self Test (POST) will run. LEDs 0-3 will flash. When the POST is complete all LEDs blink on and off then stay on.

Hint: At this point, if you were installing the DSK for the first time on your own machine you would now finish the USB driver installation. We have already done this for you on our classroom PC’s.

Testing Your Connection 7. Test your USB connection to the DSK by launching the DSK Diagnostic Utility

from the icon on the PC desktop.

From the diagnostic utility, press the start button to run the diagnostics. In approximately 20 seconds all the on-screen test indicators should turn green.

Note: If using the C6713 DSK, the title on this icon will differ accordingly.



CCS Setup While Code Composer Studio (CCS) has been installed, you will need to assure it is setup properly. CCS can be used with various TI processors – such as the C6000 and C5000 families – and each of these has various target-boards (simulators, EVMs, DSKs, and XDS emulators). Code Composer Studio must be properly configured using the CCS_Setup application.

In this workshop, you should initially configure CCS to use either the C6713 DSK or the C6416 V1.1 DSK. Between you and your lab partner, choose one of the DSK’s and the appropriate driver. In any case, the learning objectives will be the same whichever target you choose.

8. Start the CCS Setup utility using its desktop icon:

Be aware there are two CCS icons, one for setup, and the other to start the CCS application.

You want the Setup CCS C6000 icon.

Sidebar: CCS Setup Installed the version of CCS that ships with the DSK will not place the Setup CCS 2 icon on the desktop, nor will the shortcut appear under the Windows start menu:

Start → Programs → Texas Instruments → Code Composer Studio 2 (‘C6000) → Setup Code Composer Studio

The setup program <cc_setup.exe> is installed to the hard drive for both the full and DSK versions of CCS, although the desktop icon and Start menu shortcut are only added when installing the full version of CCS.

When installing the lab files for this workshop, for your convenience we also place an icon on the desktop. If, for some unexpected reason, this icon has been deleted, you can find and run the program from:

c:\ti\cc\bin\cc_setup.exe (where “\ti\” is the directory you installed CCS)



9. When you open CC_Setup you should see a screen similar to this:

Note: If you don’t see the Import Configuration dialog box, you should open it from the menu using File → Import… Once the Import Configuration dialog box is open, you can change the CC_Setup default to force this dialog to open every time you start CC_Setup. Just check the box in the bottom of the import dialog.



10. Clear the previous configuration.

Before you select a new configuration you should delete the previous configuration. Click the Clear System Configuration button. CC_Setup will ask if you really want to do this, choose “Yes” to clear the configuration.

11. Select a new configuration from the list and click the “Import” button.

If you are using the C6416 DSK in this workshop, please choose the C6416 V1.1 DSK:

64



If you are using the C6713 DSK in this workshop, please choose the C6713 DSK:

12. Save and Quit the Import Configuration dialog box.

13. Go ahead and start CCS upon exiting CCS Setup.

67 67



Set CCS – Customize Options There are a few option settings that need to be verified before we begin. Otherwise, the lab procedure may be difficult to follow.

• Disable open Disassembly Window upon load • Go to main() after build • Program load after build • Clear breakpoints when loading a new program • Set CCS Titlebar information

14. Open the Options→Customize Dialog.

15. Set Debug Properties

Here are a couple options that can help make debugging easier. − Unless you want the Disassembly Window popping up every time you load a program (which

annoys many folks), deselect this option. − Many find it convenient to choose the “Perform Go Main automatically”. Whenever a

program is loaded the debugger will automatically run thru the compilers initialization code to your main() function.



16. Set Program Load Options

On the “Program Load Options” tab, select the two following options: • Load Program After Build • Clear All Breakpoints When Loading New Programs

By default, these options are not enabled, though a previous user of your computer may have already enabled them.

Conceptually, the CCS Integrated Development Environment (IDE) is made up of two parts:

• Edit (and Build) programs Uses editor and code gen tools to create code.

• Debug (and Load) programs Communicates with processor/simulator to download and run code.

The Load Program After Build option automatically loads the program (.out file) created when you build a project. If you disabled this automatic feature, you would have to manually load the program via the File→Load Program menu.

Note: You might even think of IDE as standing for Integrated Debugger Editor, since those are the two basic modes of the tool



17. CCS Title Bar Properties

CCS allows you to choose what information you want displayed on its titlebar.

Note: To reach this tab of the “Customize” dialog box, you may have to scroll to the right using the arrows in the upper right corner of the dialog.

• We have chosen the “Board Name”, “Current Project”, and “Currently loaded program”. − The first item allows you to quickly confirm the chosen target (simulator, DSK, etc.). − The other two let us quickly determine which project is active and what program we have

loaded. Notice how these correlate to the two parts of CCS: Edit and Debug. • For our convenience we have also enabled the remaining two features on this dialog page.



Choose Text-Based Linker CCS includes two different linkers. The Visual Linker is now obsolete; therefore we want to make sure it is not selected.

18. Open the CCS linker selection dialog.

Tools → Linker Configuration

19. Select Use the text linker and click OK (as shown below).

Now you’re done with the Workstation Setup, please continue with the Lab 1 exercise …

LAB 1: Using Code Composer Studio


LAB 1: Using Code Composer Studio This lab has four goals:

• Build a project using C source files. • Load a program onto the DSK. • Run the program and view the results. • Use the CCS graphing feature to verify the results.

Lab 1 – Create & Graph a Sine Wave

Hook up DSK hardwareCreate and build a projectExamine variables, memory, codeRun, halt, step, multi-step, use breakpointsGraph results in memory (to see the sine wave)

Introduction to Code Composer Studio (CCS)

CPUbuffersineGen()

These take-home (optional) exercises are provided, as well, for those of you who finish the lab early. If you do not get the chance to complete them during the assigned lab time, please try them at home.

• Lab1a – Customize Your Workspace • Lab1b – Using GEL • Lab1c – Try adding a printf() statement • Lab1d – Fixed vs Floating Point • Lab1e – Explore CCS Scripting



Lab Source Files

Sine Generation Algorithm We’ll use a block sine-wave generator function to create our data samples, which we can then graph. The block sine-wave generator function is a basic for loop that uses the following routine to generate individual sine values:

Creating a Sine Wave

t

ASine_float.cGenerates a value for each output sample

float y[3] = {0, 0. 0654031, 0};float A = 1. 9957178;

short sineGen() {y[0] = y[1] * A - y[2]; y[2] = y[1];y[1] = y[0];

return((short)(32000*y[0]);}

There are many ways to create sine values, we have chosen this simple model based upon a monostable IIR filter.



block_sine.c // ======== block_sine.c ================================= // The coefficient A and the three initial values // generate a 500Hz tone (sine wave) when running // at a sample rate of 48KHz. // // Even though the calculations are done in floating // point, this function returns a short value since // this is what's needed by a 16-bit codec (DAC). // ======== Prototypes =================================== void blockSine(short *buf, int len); short sineGen(void); // ======== Definitions ================================== // Initial values #define Y1 0.0654031 // = sin((f_tone/f_samp) * 360) // = sin((500Hz / 48KHz) * 360) // = sin (3.75) #define AA 1.9957178 // = 2 * cos(3.75) // ======== Globals ===================================== static float y[3] = {0,Y1,0}; static float A = AA; // ======== sineGen ====================================== // Generate a single element of sine data short sineGen(void) { y[0] = y[1] * A - y[2]; y[2] = y[1]; y[1] = y[0]; // To scale full 16-bit range we would multiply y[0] // by 32768 using a number slightly less than this // (such as 32000) helps to prevent overflow. y[0] *= 32000; // We recast the result to a short value upon returning it // since the D/A converter is programmed to accept 16-bit // signed values. return((short)y[0]); } // ======== blockSine ======== // Generate a block of sine data using sineGen void blockSine(short *buf, int len) { int i = 0; for (i = 0;i < len; i++) { buf[i] = sineGen(); } }



Lab1.c // Include files #include <c6x.h> // C6000 compiler definitions #include "lab1cfg.h" // Declarations #define BUFFSIZE 128 // Global Variables static short gBuffer[BUFFSIZE]; // ======== main ======== // Simple function which calls blockSine void main() { blockSine(gBuffer, BUFFSIZE); // Fill buffer with sine data return; }



Lab 1 Procedure

Create the Lab1 project 1. Create a new project.

Create a new project C:\c60001day\labs\lab1\LAB1.PJT by choosing:

Project → New

It should look like:

2. Verify that the new project was created correctly.

Verify the newly created project is open in CCS by clicking on the + sign next to the Projects folder in the Project View window. Click again on the + sign next to lab1.pjt.

If you don’t see the new project, notify your instructor.

3. Create a new CDB file.

As mentioned during the discussion, configuration database files (*.CDB) control a range of CCS capabilities. In this lab, the CDB file will automatically create the reset vector and specify the memory to the linker.

Create a new CDB file (DSP/BIOS Configuration…) as shown:

67 If using the C6713 DSK, the target should read, “TMS320C67XX”



When the dialog box appears, select the dsk6416.cdb (or dsk6713.cdb) template and click OK.

Hint: In some TI classrooms you may see two or more tabs of CDB templates; e.g. TMS62xx, TMS54xx, etc. If you experience this, just choose the ‘C6x tab.

4. Save your CDB file.

File → Save As

C:\c60001day\labs\lab1\Lab1.CDB

Then, close the CDB Config Tool.

5. Add files to your project.

You can add files to a project in one of three ways:

• Project → Add Files to Project

• Right-click the project icon in the Project Explorer window and select Add files…

• Drag and drop files from Windows Explorer onto the project icon

Using one of these methods, add the following files from C:\c60001day\labs\lab1 to your project:

LAB1.C LAB1.CDB LAB1cfg.CMD block_sine.c

67 If using the C6713 DSK, choose the “dsk6713.cdb” file



6. Verify your files were added to the project.

The project should look similar to:

Examine the C Code 7. Open and inspect lab1.c

Open lab1.c and inspect its contents (double-click on the file in the Project window). − Notice the buffer (gBuffer) in memory of length 128. This buffer will receive values

generated by the block sine wave generator routine. After running the code, you will graph the values in this buffer.

− Look at the main( ) routine. We simply call the block sine function and then return.

Building the program (.OUT) Now that all the files have been added to our project, it’s time create the executable output program (.OUT file). By default, CCS names the program after the project name. Therefore, your output program should be named lab1.out.

8. Build the program.

There are two ways to build (compile and link) your program:

• Use the REBUILD ALL toolbar icon:

• Select Project → Rebuild All

Choose one of the above methods and build your program. The Build Output window appears in the lower part of the CCS window. Note the build progress information.

If you don’t see “0 Errors, 0 Warnings, 0 Remarks”, please ask your instructor for help.



9. Verify program is automatically loaded.

Since you enabled the Program Load after Build option (step 16, pg. 1-37), CCS should download the program lab1.out once it builds without errors

The yellow arrow indicates the position of the program counter. Once the program is loaded,

it should be pointed to the beginning of main().

Why? Setting the Perform Go Main Automatically option (step 15, pg 1-36) causes CCS to run to main after being loaded. If we didn’t enable this option, you could do it manually using the Debug → Go Main menu option.

Hint: While main( ) is the beginning of our code, there are many initialization steps that occur between reset and your main program. These issues are discussed in the various user guides and the 4-day workshops. Sorry, we don’t have time for this detail today.



Watch Variables 10. Add gBuffer to the Watch window.

Select and highlight the variable gBuffer in the lab1.c window. Right-click on gBuffer and choose Add to Watch Window.

Note: The value shown for gBuffer will most likely differ from that shown below.

Adding a variable to the Watch window opens it automatically. Alternatively, you could have opened the watch window, selected gBuffer, and drag-n-dropped it onto the Watch 1 window.

Click on the + sign next to gBuffer to see the individual elements of the array.

Note: At some point, if the Watch window shows an error “unknown identifier” for a variable, don’t worry, it's probably due to the variable’s scope. Local variables do not exist (and thus, don’t have a value) until their function is called. If requested, Code Composer will add local variables to the Watch window, but will indicate they aren’t valid until the appropriate function is reached.

Viewing and Filling Memory 11. View the memory contents at the address gBuffer.

Another way to view values in memory is to use a Memory window. Select

View → Memory

and type in the following: • Title = gBuffer

• Address = gBuffer

• Q-Value = 0

• Format = 16-Bit Hex-TI Style

Click OK and resize the window so that you can see your code and the buffer. Because we have just come out of reset and this memory area was not initialized, you should see random values.



12. Record the address of the gBuffer array.

There are many ways to find this address. Two of them are: • The address shown for the +gBuffer value in the Watch Window; or • The address associated with gBuffer in the Memory View window

Address of gBuffer: ________________________________________________________

13. Initialize the gBuffer array to zero.

While not necessarily required since gBuffer will be overwritten by our code, let’s go ahead and initialize it anyway. Select:

Edit → Memory → Fill

and fill in the following: • Address = gBuffer

• Length = 64

• Fill Pattern = 0

Click OK.

The buffer was 128 16-bit values in length (they were defined as “shorts” in the C file). The fill memory function fills integer, or 32-bit values. Therefore, we only need to fill sixty-four 32-bit locations in order to zero out the 128x16 array.

Single-Stepping Code 14. Click on the Watch Locals tab of the Watch window.

15. Single-Step through your code.

Single-step the debugger until you reach the blockSine() function; it contains local variables.

Use toolbar -or- Debug menu

Once you have single-stepped to the for loop, you’ll notice that Watch Locals will look similar to.

Use icon with the yellow arrow. • Yellow arrow for source-stepping. • Green arrow for assembly stepping.



Multiple Operations Toolbar CCS has a new feature that provides multi-operations from a toolbar. Let’s try to single-step our source code another eight times using this feature.

16. Verify the Multiple Operations toolbar is visible. It should look like:

If you cannot find it, it can be opened from the View menu:

View → Debug Toolbars → Multiple Operations

17. Set the Multiple Operations values as shown in the proceeding step and execute.

Source Step Into 8 Execute

You should see it executing multiple single-steps, just as in step 15.

Setting Breakpoints While single-stepping is quite useful, it can take a long time to get to the end of your program. A faster way to accomplish this is to set a breakpoint (a marker which tells the processor to stop) and use the RUN command.

18. Set a break point.

Set a break point on the return; command in main( ). Breakpoints can be set in 3 different ways. Choose the one you like best and set the breakpoint:

• Place the cursor on the end brace of main() and click on the:

• Right-click on the line with the end brace and choose Toggle Breakpoint

• Double-click in the grey area next to the end brace (as shown below):



Running Code 19. Run your code.

Run the code up to the breakpoint. There are 3 different ways to cause CCS to run your code:

• Use toolbar icon:

• Select: Debug → Run

• Press F5

The processor will halt at the breakpoint that you’ve set.

Notice that the watch window changes to show the new values of gBuffer[]. You may have to click on the + sign next to buffer to see the values. Code Composer allows you to collapse and expand aggregate data types (structures, arrays, etc.).

Hint: Values highlighted in red have changed with the last update



Windows and Workspaces 20. Rearrange windows.

As long as a window is not maximized in CCS, it can be moved around to any location you prefer. Windows can float or be docked.

Select the Watch window, right-click on the upper portion, and select Float In Main Window. Then, move it around. Try docking it again.

21. Save your Workspace

When you have the windows exactly where you want them, save your workspace by choosing:

File → Workspace → Save Workspace As

Pick a filename and save it in any location you prefer (the lab1 directory may be convenient).

Note: The workspace includes the current open project. So, when you retrieve the workspace, it will retrieve the project. If you don’t wish to save the project info with the workspace, close the project before saving your workspace.

If you want to retrieve a previously saved workspace, select:

File → Load Workspace

Graphing Data 22. Graph your sine data.

The watch window is a great way to view data in CCS. But, can you tell if this is really a sine wave? Wouldn’t it be better to see this data graphed? Well, CCS allows us to do this. Select:

View → Graph → Time/Frequency

Modify the following values:

• Graph Title gBuffer

• Start Address gBuffer

• Acquisition Buffer Size 128

• Display Data Size 128

• DSP Data Type 16-bit signed integer

• Sampling Rate 49152

Click OK when finished.



Your graph should look something like this:

23. Other graphing features

CCS supports many different graphing features: time frequency, FFT magnitude, dual-time, constellation, etc. The sine wave that we generated was a 500Hz wave sampled at 48KHz. Let’s use the FFT magnitude plot to see the fundamental frequency of the sine wave.

Right click on the graphical display of gBuffer and select Properties. Change the display type to FFT Magnitude and click OK. You can now see the frequency spectrum of the wave.

24. Save your workspace again.

This will also save your graph window to the workspace.

End of Lab1 We highly recommend trying the first couple optional exercises, if time is still available.

Before going on, though, please let your instructor know when you have reached this point.

“Take Home” Exercises (Optional)


“Take Home” Exercises (Optional) Optional exercises are additional labs that you can use to extend your knowledge of the ‘C6000 and CCS toolset. If you finish the main exercise early, you are welcome to begin working on these labs.

Lab1a – Customize CCS

Add Custom Keyboard Assignment While most CCS commands are available via hotkeys, you may find yourself wanting to modify CCS to better suit your personal needs. For example, to restart the processor, the default hotkey(s) are:

Debug → Restart

CCS lets you remap many of these functions. Let’s try remapping Restart.

1. Start CCS if it isn’t already open.

2. Open the CCS customization dialog.

Option → Customize…

3. Choose the Keyboard tab in the customize dialog box.

4. Scroll down in the Commands list box to find Debug → Restart and select it.

5. Click the Add button.

6. When asked to, “Press new shortcut key”, press:

F4

We already checked and this one isn’t assigned within CCS, by default.

7. Click OK twice to close the dialog boxes.

8. From now on, to Restart and Run the CPU, all you need to do is push F4 then F5.



Customize your Workspace You may not find the default workspace for CCS as convenient as you’d like. If that’s the case, you can modify as needed.

9. Close CCS if it’s open, and then open CCS.

This is forces CCS back to its default states (i.e. no breakpoints, profiling, etc.).

10. Move the toolbars around as you’d like them to be.

For example, you may want to close the BIOS and PBC toolbars and then move the Watch toolbar upwards so that you free up another ½ inch of screen space.

11. If you want the Project and File open dialogs to default to a specific path, you need to open a project or file from that path.

12. Make sure you close any project or file from step 11.

13. Save the current workspace.

File → Workspace → Save Workspace As...

Save this file to a location you can remember. For example, you might want to save it to:

C:\c60001day\labs\

14. Close CCS.

15. Change the properties of the CCS desktop icon.

Right-click on the CCS desktop icon Add your workspace to the Target, as shown below

16. Open up CCS and verify it worked.

This should be the path and name of your workspace.

c:\c60001day\labs






Lab1b - Using GEL Scripts GEL stands for General Extension Language, a fancy name for a scripting tool. You can use GEL scripts to automate processes as you see necessary. We’ll be using a few of them in the lab in just a few minutes….

GEL Scripting

GEL: General ExtensionLanguage

C style syntaxLarge number of debugger commands as GEL functionsWrite your own functionsCreate GEL menu items



Technical TrainingOrganization

T TO

Using GEL Scripts When debugging, you often need to fill memory with a known value prior to building and

running some new code. Instead of constantly using the menu commands, let’s create a GEL (General Extension Language) file that automates the process. GEL files can be used to execute a string of commands that the user specifies. They are quite handy.

1. Start CCS and open your project (lab1.pjt) and load the program (lab1.out), if they’re not already open and loaded.

2. Create a GEL file (GEL files are just text files)

File → New → Source File

3. Save the GEL file

Save this file in the lab1 folder. Pick any name you want that ends in *.gel.

File → Save

We chose the name mygel.gel.



4. Create a new menu item

In the new gel file, let’s create a new menu item (that will appear in CCS menu “GEL”) called “My GEL Functions”. Type the following into the file:

menuitem “My GEL Functions”;

You can access all of the pre-defined GEL commands by accessing:

Help → Contents

Select the Index tab and type the word “GEL”.

5. Create a submenu item to clear our arrays

The menuitem command that we used in the previous step will place the title “My GEL Functions” under the GEL menu in CCS. When you select this menu item, we want to be able to select different operations. Submenu items are created with the hotmenu command.

Enter the following into your GEL file to create a submenu item to clear the memory array: (Don’t forget the semicolon – as with C, it’s important!)

hotmenu ClearArray() { GEL_MemoryFill(gBuffer, 0, 64, 0x0); }

The MemoryFill command requires the following info: • Address • Type of memory (data memory = 0) • Length (# of 32-bit values) • Memory fill pattern.

This example will fill our array (gBuffer) with zeros. For more info on GEL and GEL_ commands, please refer to the CCS help file.

6. Add a second menu item to fill the array

In this example, we want to ask the user to enter a value to write to each location in memory. Rather than using the hotmenu command, the dialog command allows us to query the user.

Enter the following:

dialog FillArrays(fillVal “Fill Array with:”) { GEL_MemoryFill(gBuffer, 0, 64, fillVal); }

7. Save then Load your new GEL file

To use a GEL file, it must be loaded into CCS. When loaded, it shows up in the CCS Explorer window in the GEL folder.

File → Save File → Load GEL and select your GEL file



8. Show gBuffer array in Memory window

Without looking at the arrays, it will be hard to see the effect of our scripts. Let’s open a Memory window to view gBuffer.

View → Memory…

Title: gBuffer Address: gBuffer Q-Value: 0 Format: 16-bit hex – TI style

A couple notes about memory windows: • C Style adds 0x in front of the number, TI Style doesn’t. • Select the Format based on the data type your are interested in viewing. This will make it

easier to ‘see’ your data.

9. Now, try the GEL functions.

GEL → My GEL Functions → ClearArray GEL → My GEL Functions → FillArray

You can actually use this GEL script throughout the rest of the workshop. It is a very handy tool. Feel free to add or delete commands from your new GEL file as you do the labs.

10. Review loaded GEL files.

Within the CCS Explorer window (on the left), locate and expand the GEL files folder. CCS lists all loaded GEL files here.

Hint: If you modify a loaded GEL file, before you can use the modifications you must reload it. The easiest way to reload a GEL file: (1) Right-click the GEL file in the CCS Project Explorer window (2) Pick Reload from the right-click popup menu



Lab1c – Using Printf If you want to use printf() to output the value of y, two steps are required.

Lab 1c: Using Printf

#include <stdio.h>

short func1(short *m, short count);

short a[4] = {40,39,38,37};int y = 0;

main(){

y = function();printf("y = %x hex\n", y);

}

1.

2.

1. Open lab1.pjt project, if it is not still open.

2. Open the lab1.c file by double-clicking on it in the Project Explorer window.

3. To use printf(): • First you must remember to include the header file as in step #1 in the above graphic. • Next, you must add the printf() command to your c file.

For example, try adding a simple printf() to main.

void main() { blockSine(gBuffer, BUFFSIZE); // Fill buffer with sine data printf("gBuffer (at location 0x%x) was filled with sine values\n", gBuffer); return; }

4. Build and load the .OUT file.

When you build and load this program, the Build/Messages window will add a third tab called Stdout which will contain the output from printf().

5. Verify that it works. This can be done by viewing the printed statement in the output window, Stdout tab of the Output window.

6. Close the project.



Lab1d – Fixed vs Floating Point We included a functioning integer sinewave routine for comparison to the float routine used throughout the workshop. Notice the additional effort required make integer math routines work correctly. This extra work is required so that the 16-bit integer values do not overflow and cause data corruption.

The method used to solve overflow in this application is often called Q-math. Maybe a better name for it is fractional, fixed-point math. The beauty of fractions is that when multiplied together, their value gets smaller. Hence the result is always bounded (i.e. no overflow).

The problem with integer math is not confined to TI DSPs (or DSPs in general), rather it is a side affect between the fact that integer numbers get bigger when add or multiply them and that the C language provides no means of handling overflow for signed numbers. In fact, the C language leaves signed math that overflows undefined – every compiler writer can handle it however they want (so much for portability).

The dynamic range of floating-point variables sure makes life easier. It’s why many folks choose floating-point to decrease their engineering time (and get to market more quickly). Of course, this is why the C6713 is so popular – as it’s designed to do floating-point math in hardware.

We have provided a project for you to compare different versions of sineGen: • Standard fixed-point math • Q-math (fractional, fixed-point) • Floating-point math

You will find LAB1d.PJT already built in the LAB1d folder:

C:\c60001day\labs\lab1d\

Try running the project and comparing all three results in three different graphs. To simplify setting up the graph windows, try using the provided workspace LAB1d.wks.






Lab1e – Explore CCS Scripting A number of CCS Scripting examples have been included in the Scripting folder. You will find them at: C:\c60001day\labs\scripting\

These scripts are contained in Excel spreadsheets and are written in VBA (Visual Basic for Applications). Scripts can also be written in perl or any COM compliant language. Please feel free to explore them.

Lab Debrief

Lab 1 Debrief

1. What differences are there in Lab1 between the C6713 and C6416 solutions?

2. What do we need CCS Setup for?3. Why did we return from main?4. What did you have to add to LAB1.C to get

printf to work?5. Did you find the “clearArrays” GEL menu

command useful?

Optional Topics


Optional Topics

Optional Topic: CCS Automation As evidenced by the optional lab exercise, CCS ships provides scripting/automation tools. They are mentioned here to make you aware of their presence. To explore them further, please examine the online documentation.

Command Line Window Provides a convenient way to type in CCS commands, rather than using the pull-down menus.

Command Window

Some frequently used commands:load <filename.out>reloadresetrestartba <label >wa <label>

helpdlog <filename>,adlog closealias ...take <filename.txt>

runrun <cond>go <label>step <number>cstep <number>halt

For those of you ‘ol timers, who remember the old command line debugging tools, you can use the same commands you’ve used for years.

Optional Topics


GEL Scripting

GEL Scripting





• Notice the GEL folder in the Project View window. You can load/unload GEL scripts by right-

clicking this window. • GEL syntax is very C-like. Notice that QuickTest() calls LED_cycle(), defined earlier in the file.

(This happens to be a C6711 DSK GEL script.) • You can add items to the GEL menu. An example is shown in the above graphic. • Finally, a GEL file can be loaded upon starting CCS. The startup GEL script is specified using the

CCS Setup application.

Optional Topics


CCS Scripting CCS Scripting is a CCS plug-in. After installing CCS on your PC, you should use the Update Advisor feature (available from the Help menu) to download and add the CCS Scripting plug-in.

Hint: You may find other useful tools, application notes, and plug-ins available via the CCS Update Advisor.

CCS scripting provides a method of controlling the CCS debugger from another scripting language. Any Microsoft COM (i.e. OLE) compliant language should be able to use the CCS Scripting library, but VB Script and Perl are the two languages for which examples are provided.

The graphic below is an example of a VB Script using CCS Scripting:

Debug using VB Script or PerlUsing CCS Scripting, a simple script can:

Start CCSLoad a fileRead/write memorySet/clear breakpointsRun, and perform other basic testing functions

Debug using VB Script or PerlUsing CCS Scripting, a simple script can:

Start CCSLoad a fileRead/write memorySet/clear breakpointsRun, and perform other basic testing functions

CCS Scripting

Among other things, CCS Scripting is very useful for testing purposes. For example, if you have a number of test vectors you would like to run against your system, you can use CCS Scripting to automate this process. Your script could then:

• Build • Run • Capture data, memory values, benchmarks • And compare the results against what you expect (or hope) • Over and over again …

At this time, the CCS Scripting Plug-in (v1.2) only ships with C5000 based examples. For your convenience, we have written and included some C6000 based examples along with the workshop lab files.

Optional Topics


TCONF Scripting (Textual Configuration) CCS now provides a textual scripting method for creating and editing CDB files.

TCONF Scripting (CDB)Tconf Script (.tcf) hello_dsk62cfg.tcf

#include <log.h>

extern LOG_Obj trace; /* created in hello.tci */

int main() {LOG_printf(&trace, "Hello World!\n");return (0);

}

Your Application hello.c

utils.loadPlatform("dsk6211"); /* load DSK6211 platform into TCOM */utils.getProgObjs(prog); /* make all prog objects JavaScript global vars */LOG_system.bufLen = 128; /* set buffer length of LOG_system to 128 */utils.importFile("hello"); /* import portable application script */prog.gen(); /* generate cfg files (and CDB file) */

var trace = LOG.create("trace"); /* create a new user log, named trace */trace.bufLen = 32; /* initialize its length to 32 (words) */

Tconf Include File (.tci) hello.tci

• A textual way to configure CDB files• Runs on both PC and Unix• Create #include type files (.tci)• More flexible than Config Tool

• A textual way to configure CDB files• Runs on both PC and Unix• Create #include type files (.tci)• More flexible than Config Tool

Some users find ‘writing code’ preferable to using the Graphical User Interface (GUI) of the Configuration Tool. This is especially true for users who build their code in the Unix environment, as there is no Unix version of the GUI.

Optional Topics


Optional Topic: CPU Architecture Details Again, before more closely examining the C6000 CPU architecture, it’s beneficial to remind ourselves of the purpose of a Digital Signal Processor. In other words, what is digital signal processing?

What is Digital Signal Processing (DSP)? We already explored this topic back on page 1-9. As a reminder, here is the graphic that summed up the answer to our question.

What Problem Are We Trying To Solve?

Digital sampling of an analog signal:

A

t

Most DSP algorithms can be expressed with MAC:

count

i = 1Y = Σ coeffi * xi

for (i = 0; i < count; i++){sum += c[i] * x[i]; }

DACx YADC DSP

Optional Topics


CPU Architecture What is the core part of DSP algorithms? In layman's terms, you might say it’s the Sum of Products (SOP) or Multiply-Accumulate (MAC).

MultMult

ALUALUMPY c, x, prodADD y, prod, y

y =40

∑ cn xnn = 1

*

The Core of DSP : Sum of Products

The ‘C6000Designed to

handle DSP’smath-intensive

calculations

ALUALU

.M.M

MPY .M c, x, prod.L.L ADD .L y, prod, y

Note:You don’t have to specify functional units (.M or .L)

The C6000 CPU has a separate Multiply (.M) unit, along with an arithmetic logic unit (.L). The variables operated upon by the CPU are stored in a register file. Register file “A” holds 16 or 32 registers, depending upon which C6000 CPU you are using.

y =40

∑ cn xnn = 1

*Register File A

cx

prod

32-bits

y...

.M.M

.L.L

Working Variables : The Register File

16or

32

regi

ster

s

MPY .M c, x, prodADD .L y, prod, y

The heart of the Sum of Products routine is easily handled by these two units as shown above

Optional Topics


with the Multiply (MPY) and Add instructions. To make this into a real Sum of Products, though, we need to put them into a loop.

Making Loops

1. Program flow: the branch instruction

2. Initialization: setting the loop count

3. Decrement: subtract 1 from the loop counter

B loop

SUB cnt, 1, cnt

MVK 40, cnt

Adding these instructions to our example:

y =40

∑ cn xnn = 1

*

“.S” Unit: Branch and Shift Instructions

MVK .S 40, cntloop:

MPY .M c, x, prodADD .L y, prod, ySUB .L cnt, 1, cntB .S loop

.M.M

.L.L

.S.S

Register File A

32-bits

cx

prody...

cnt

Note:C64x could use BDEC in place of SUB and Branch

16 o

r 32

regi

ster

s

If you (or the compiler) were coding for the C64x, you could optimize the code using the Branch with Decrement (BDEC) instruction.

When using a standard branch (B), though, how can we tell our loop counter has reached zero and that we can stop branching and move on?

Optional Topics


By putting a conditional [reg] statement before the branch, as shown below.

Conditional Instruction Execution

Note: If condition is false, execution is essentially replaced with nop

Code Syntax Execute if:[ cnt ] cnt ≠ 0[ !cnt ] cnt = 0

Execution based on [zero/non-zero] value of specified variable

To minimize branching, all instructions are conditional

[condition] B loop

y =40

∑ cn xnn = 1

*

Loop Control via Conditional Branch

MVK .S 40, cntloop:

MPY .M c, x, prodADD .L y, prod, ySUB .L cnt, 1, cnt

[cnt] B .S loop

.M.M

.L.L

.S.S

Register File A

32-bits

cx

prody...

cnt

16 o

r 32

regi

ster

s

A great thing about the C6000 is that all instructions allow for [conditional] execution. While this may not sound that cool at first, it can make a tremendous difference in how efficient you can code a hardware pipelined processor.

Optional Topics


Since a register can only hold a single value at a time, we have to load our variable registers each time through the loop. The C6000 has a forth functional unit to manage data loads and stores (.D). We use the pointer concept in assembly code, just as you might in C code. The pointer indicates where the data array exists in memory; that is, where we load the data from.

Memory Access via “.D” Unit

.M .M

.L .L

.S .S y =

40

∑ cn xnn = 1

*

MVK .S 40, cntloop:

LDH .D *cp , cLDH .D *xp , xMPY .M c, x, prodADD .L y, prod, ySUB .L cnt, 1, cnt

[cnt] B .S loop

Data Memory:x(40), a(40), y

Register File Acx

prody

cnt

*cp*xp*yp

.D .D

16 o

r 32

regi

ster

s

Note: No restrictions on which regscan be used for address or data!

Note: No restrictions on which regscan be used for address or data!

Loads can be performed in many different widths, depending upon your chosen data type.

Memory Access via “.D” Unit

.M .M

.L .L

.S .S y =

40

∑ cn xnn = 1

*

MVK .S 40, cntloop:

LDH .D *cp , cLDH .D *xp , xMPY .M c, x, prodADD .L y, prod, ySUB .L cnt, 1, cnt

[cnt] B .S loop


Register File Acx

prody

cnt

*cp*xp*yp

.D .D

16 o

r 32

regi

ster

s

Instr. Description C Type SizeLDB load byte char 8-bitsLDH load half-word short 16-bitsLDW load word int 32-bitsLDDW* load double-word double 64-bits* Only available on the C64x and C67x

Instr. Description C Type SizeLDB load byte char 8-bitsLDH load half-word short 16-bitsLDW load word int 32-bitsLDDW* load double-word double 64-bits* Only available on the C64x and C67x

Optional Topics


Since we are loading data from arrays in memory, how can we increment the pointers each time through the loop? Again, we use the same increment (++) syntax used by the C language. In this case, the ++ comes after the pointer to indicate we are incrementing the address value contained in the pointer (after using the current value).

Auto-Increment of Pointers

Register File Acx

prody

cnt

*cp*xp*yp

y =40

∑ cn xnn = 1

*

MVK .S 40, cntloop:

LDH .D *cp++, cLDH .D *xp++, xMPY .M c, x, prodADD .L y, prod, ySUB .L cnt, 1, cnt

[cnt] B .S loop

.M .M

.L .L

.S .S


.D .D

16 o

r 32

regi

ster

s

Finally, we use a third pointer to store the final result back into our resultant variable.

Storing Results Back to Memory

Register File Acx

prody

cnt

*cp*xp*yp

y =40

∑ cn xnn = 1

*

MVK .S 40, cntloop:

LDH .D *cp++, cLDH .D *xp++, xMPY .M c, x, prodADD .L y, prod, ySUB .L cnt, 1, cnt

[cnt] B .S loopSTW .D y, *yp

.M .M

.L .L

.S .S


.D .D

16 o

r 32

regi

ster

s

Optional Topics


So far, we’ve only told you a half-truth. In reality, the C6000 has eight functional units, rather than four. Also, there are two register sets of 16 or 32 registers each.

Dual Resources : Twice as Nice

A0A1A2A3A4

Register File A

A15or

A31

A5A6A7

cn

xn

prdsum

cnt

..

*c*x*y

.M1.M1

.L1.L1

.S1.S1

.D1.D1

.M2.M2

.L2.L2

.S2.S2

.D2.D2

Register File BB0B1B2B3B4

B15or

B31

B5B6B7..

32-bits

....

32-bits

As you will see later, having both sets of functional units can dramatically improve our processor's performance.

Optional Topics


In the assembly coding we’ve examined thus far, we have used symbols (i.e. labels) to specify registers. This is the preferred method of coding when using Linear Assembly code – as described in this module. You also have the option to specify specific registers and/or functional units if you wish to provide constraints to the Assembly Optimizer.

MVK .S1 40, A2loop: LDH .D1 *A5++, A0

LDH .D1 *A6++, A1MPY .M1 A0, A1, A3ADD .L1 A4, A3, A4SUB .S1 A2, 1, A2

[A2] B .S1 loopSTW .D1 A4, *A7

y =40

∑ cn xnn = 1

*

Optional - Resource Specific Coding

A0A1A2A3A4

Register File A

A15or

A31

A5A6A7

cn

xn

prdsum

cnt

..

*c*x*y

.M1.M1

.L1.L1

.S1.S1

.D1.D1

32-bits

..

It’s easier to use symbols rather thanregister names, but you can use

either method.

Optional Topics


C6000 Instruction Set All C6000 processors have the same basic CPU architecture.

'C6000 System Block Diagram

ExternalMemory

.D1

.M1

.L1

.S1

.D2

.M2

.L2

.S2

ReggisterSet B

Register Set A

CPU

On-chipMemoryP

ERIPHERALS

Internal Buses

To summarize each units’ instructions ...

One major difference is the instructions each CPU can execute.

‘C62x RISC-like instruction set

.L .L

.D .D

.S .S

.M .M

No Unit UsedIDLENOP

.S UnitNEGNOT ORSETSHLSHRSSHLSUBSUB2XORZERO

ADDADDKADD2ANDBCLREXTMVMVCMVKMVKH

.L UnitNOTORSADDSATSSUBSUBSUBCXORZERO

ABSADDANDCMPEQCMPGTCMPLTLMBDMVNEGNORM

.M UnitSMPYSMPYH

MPYMPYHMPYLHMPYHL

.D UnitNEGSTB (B/H/W) SUBSUBAB (B/H/W) ZERO

ADDADDAB (B/H/W)LDB (B/H/W)

MV

Optional Topics


The C67x adds a whole set of floating-point instructions to the C62x capabilities:

‘C67x: Superset of Fixed-Point

.L .L

.D .D

.S .S

.M .M

No Unit RequiredIDLENOP

.S UnitNEGNOT ORSETSHLSHRSSHLSUBSUB2XORZERO

ADDADDKADD2ANDBCLREXTMVMVCMVKMVKH

ABSSPABSDPCMPGTSPCMPEQSPCMPLTSPCMPGTDPCMPEQDPCMPLTDPRCPSPRCPDPRSQRSPRSQRDPSPDP

.L UnitNOTORSADDSATSSUBSUBSUBCXORZERO

ABSADDANDCMPEQCMPGTCMPLTLMBDMVNEGNORM

ADDSPADDDPSUBSPSUBDPINTSPINTDPSPINTDPINTSPRTUNCDPTRUNCDPSP

.M UnitSMPYSMPYH

MPYMPYHMPYLHMPYHL

MPYSPMPYDPMPYIMPYID

.D UnitNEGSTB (B/H/W) SUBSUBAB (B/H/W) ZERO

ADDADDAB (B/H/W)LDB (B/H/W)LDDWMV

Similarly, the C64x is a superset of the C62x …

'C64x: Superset of ‘C62x Instruction Set

.L .L Data Pack/UnPACK2PACKH2PACKLH2PACKHL2PACKH4PACKL4UNPKHU4UNPKLU4SWAP2/4

Dual/Quad ArithABS2ADD2ADD4MAXMINSUB2SUB4SUBABS4Bitwise LogicalANDNShift & MergeSHLMBSHRMBLoad ConstantMVK (5-bit)

.D .D

.S .S

.M .M

Bit OperationsBITC4BITRDEALSHFLMoveMVD

AverageAVG2AVG4ShiftsROTLSSHVLSSHVR

MultipliesMPYHIMPYLIMPYHIRMPYLIRMPY2SMPY2DOTP2DOTPN2DOTPRSU2DOTPNRSU2DOTPU4DOTPSU4GMPY4XPND2/4

Mem AccessLDDWLDNWLDNDWSTDWSTNWSTNDWLoad ConstantMVK (5-bit)

Dual ArithmeticADD2SUB2Bitwise LogicalANDANDNORXORAddress Calc.ADDAD

Data Pack/UnPACK2PACKH2PACKLH2PACKHL2UNPKHU4UNPKLU4SWAP2SPACK2SPACKU4

Dual/Quad ArithSADD2SADDUS2SADD4Bitwise LogicalANDNShifts & MergeSHR2SHRU2SHLMBSHRMB

ComparesCMPEQ2CMPEQ4CMPGT2CMPGT4Branches/PCBDECBPOSBNOPADDKPC

Optional Topics


Assorted C6000 Benchmarks Here are a few assorted benchmarks for the C62x. Actually, these benchmarks evaluate both the device and the C compiler, as they’re benchmarks of natural C code:

Sample C62x Compiler Benchmarks

TI C62x™ Compiler Performance Release 4.0: Execution Time in µs @ 300 MHz Versus hand-coded assembly based on cycle count

100%0.912740.93279Mean Sq. Error Computation

in Vector Quantizer

MSEMSE between two 256 element vectors

100%0.16470.1751Vector SumTwo 44 sample vectors

100%0.19580.2061VSELP based voice coders

MACTwo 40 sample vectors

93%0.25750.2370FilterIIR – cascaded biquads10 Cascaded biquads(Direct Form II)

100%0.13380.1443FilterIIR Filter16 coefficients

90%4.3913183.951185Search Algorithms

Minimum Error SearchTable Size = 2304

85%0.932800.79238VSELP based voice coders

All-zero FIR Filter40 samples, 10 coefficients

100%0.20590.2061Search Algorithms

Vector Max40 element input vector

100%3.209613.26977CELP based voice codersCodebook Search

87%1.344021.16348For motion

compensation of image data

Block Mean Square ErrorMSE of a 20 column image matrix

% Efficiency vs

Hand CodedC Time

(µs)C Cycles (Rel 4.0)

Assembly Time (µs)

AsmCyclesUsed InAlgorithm

Completely natural C code (non ’C6000 specific)Code available at: http://www.ti.com/sc/c6000compilerCompletely natural C code (non ’C6000 specific)Code available at: http://www.ti.com/sc/c6000compiler

Optional Topics


The following sample of benchmarks shows the performance for both the C62x and C64x. While the C62x is no slouch in performance, the C64x is just that much better. At 720MHz today, with 1GHz speeds already demonstrated, the C64x is the family to use for extreme performance.

* Includes traceback

Sample Imaging & Telecom Benchmarks

5.5x2.3x0.330.77Polyphase Filter - Image Scaling (8-bit) cycles/output/filter tap

8.4x3.5x1.284.5Correlation - 3x3(8-bit) cycles/pixel

8.4x3.5x4701680Reed Solomon Decode:

Syndrome Accumulation (204,188,8) Packet cycles/packet

6.5x2.7x14*38.25Viterbi Decode (GSM)(16 states) cycles/output

cycles/pixel 18.2x7.6x0.1260.953Motion Estimation - 8x8 MAD (8-bit)

cycles/pixel 10.3x4.3x2.19.0Median Filter - 3x3(8-bit)

cycles/data 5x2.1x6.012.7FFT - Radix 4 - Complex (size = N log (N)) (16-bit)

720MHz C64x vs

300MHz C62x

Cycle Improvement

C64:C62C64xC62x

PerformanceCycle CountDSP & Image

Processing Kernels

You can find more C6000 benchmarks at:

http://dspvillage.ti.com/docs/catalog/generation/details.jhtml?templateId=5154&path=templatedata/cm/dspdetail/data/c6000_benchmarks

Optional Topics


Lab Debrief Answers 1. What differences are there in Lab1 between the C6713 and C6416 solutions?

• Each uses a different CDB template file • One uses the –mv6700 option, while the other uses the –mv6400

(by the way, what is this option for?)

2. What do we need CCS Setup for? • It allows you to specify which target CCS should talk to. • In this workshop, it was either the C6713 or C6416 DSK.

3. Why did we return from main? • When using a CDB file, returning from main invokes the DSP/BIOS scheduler. • This is discussed a bit more in Chapter 3. And in much greater detail in both of the

following 4-day workshops: − C6000 Integration Workshop (IW6000) − DSP/BIOS Workshop

4. What did you have to add to LAB1.C to get printf to work? • Reference to the standard C I/O header file <stdio.h> • The printf() statement itself.

5. Did you find the “clearArrays” GEL menu command useful? • We hope so!

C6416/C6713 DSK One-Day Workshop - Using Peripherals 2 - 1

Using Peripherals

Introduction A big part of any design is getting data in and out of the processor. Configuring and using peripherals has often been one of the most tedious chores. To this end, TI has created a library of functions, data types, and macros called the Chip Support Library (CSL). This library can replace much of what you might have otherwise needed to write on your own.

As the name implies, the Chip Support Library handles the peripheral resources found on-chip. For TI produced development boards (like the C6416 and C6713 DSK’s), a Board Support Library (BSL) is also provided. Similar to the CSL, it provides code for using the peripheral resources contained on the board, but outside of the DSP chip.

In the next chapter, we briefly discuss how the CSL and BSL can be used to build an encapsulated device driver. In this chapter we’ll use these software libraries directly, in order to output the sine wave we created in previous lab exercise.

CPUHWI

AIC

sineGen McBSP

transmit interrupt

DSK6416_AIC23_write()

Chapter Outline Outline

Audio Output (McBSP, Codec)McBSP is connected to the CodecMcBSP – a closer look

Using CSL & BSLHardware Interrupts (HWI)Lab 2 – Output a Sinewave Tone

Audio Output – McBSP and the AIC23 Codec

2 - 2 C6416/C6713 DSK One-Day Workshop - Using Peripherals

We intended for this page to be almost blank.



Chapter 2 Topics Using Peripherals ...................................................................................................................................... 2-1

Audio Output – McBSP and the AIC23 Codec........................................................................................ 2-4 C6416 DSK – McBSP↔Codec Interface........................................................................................... 2-4 C6713 DSK – McBSP↔Codec Interface........................................................................................... 2-5 McBSP Block Diagram ...................................................................................................................... 2-6

Programming Peripherals with CSL and BSL ........................................................................................ 2-8 What is CSL and BSL?....................................................................................................................... 2-8 Generic Procedure for CSL and BSL ................................................................................................2-10 CSL and BSL Documentation ...........................................................................................................2-13

Hardware Interrupts (HWI) ...................................................................................................................2-14 Enabling Interrupts ............................................................................................................................2-15

Lab 2 ......................................................................................................................................................2-16 The Paperwork...................................................................................................................................2-17 Lab2 Procedure..................................................................................................................................2-21

Lab2a (optional) ....................................................................................................................................2-27 Lab 2 Debrief .........................................................................................................................................2-28




DSK

DSPCPU

AIC23McBSP

Audio Connections

The DSK uses two McBSPs to talk with the AIC23 codecOne for control, Another for data

McBSP

C6416 DSK – McBSP↔Codec Interface

Control

Data

McBSP1

McBSP2

C6416 DSK: McBSP ↔ Codec Interface

McBSP1 connected to program AIC23’s control registersMcBSP2 is used to transfer data to A/D and D/A convertersProgrammable frequency: 8K, 16K, 24K, 32K, 44.1K, 48K, 96K24-bit converter, Digital transfer widths: 16-bits, 20-bits, 24-bits, 32-bits



C6713 DSK – McBSP↔Codec Interface

Data

McBSP0

McBSP1

C6713 DSK: McBSP ↔ Codec Interface

McBSP0 connected to program AIC23’s control registersMcBSP1 is used to transfer data to A/D and D/A convertersProgrammable frequency: 8K, 16K, 24K, 32K, 44.1K, 48K, 96K24-bit converter, Digital transfer widths: 16-bits, 20-bits, 24-bits, 32-bits

Control

Notice that the two DSK’s use different McBSP’s to communicate with the codec. Other than this, the two boards audio output works in exactly the same way.



McBSP Block Diagram Here’s a block diagram of the C6000’s Multi-Channel Buffered Serial Port (McBSP). Notice the independent Receive and Transmit pins and data paths. You might also notice that either the CPU or the EDMA can access the memory-mapped Data Receive Register (DRR) or Data Transmit Register (DXR). Companding (µLaw/aLaw data compression) is optional on both receive and/or transmit.

McBSP Block Diagram

CPU

DMA

Internal

Bus

DXR

DXXSR

CLKR

FSR

CLKX

FSX

McBSP ControlRegisters

CLKS

RBR

DRR 32

DRRSRExpand(optional)

Compress(optional)

Additional Background graphics for McBSP

The first slide shows what hardware event causes the Receive and Transmit interrupts.

McBSP Interrupts

In Lab 2:XRDY generates McBSP transmit interrupt (XINT2) to CPU when DXR is emptied (and ready for a new value)

In Lab 3 (IOM Device Driver):XRDY generates transmit event to EDMA when the DXR is ready for a new value

DRR RBR

DXR XSR

RRDY=1

XRDY=1

“Ready to Read”

“Ready to Write”

CPURINTXINT

DMAREVTXEVT

RRDY & XRDY in McBSP control register displays the “status” of read and transmit ports:

0: not ready 1: ready to read/write



The following two slides provide a basic description of the McBSP’s synchronous, serial data transfer.

Basic Definitions - Bit, Word

SP Ctrl (SPCR)Rcv Ctrl (RCR)Xmt Ctrl (XCR)Rate (SRGR)

Pin Ctrl (PCR)

Serial Port

CLK

b7 b6 b5 b4 b3 b2 b1 b0

Word

FS

a1 a0

Bit

D

“Word” or “channel” contains #bits specified by WDLEN1 (8, 12, 16, 20, 24, 32)

RWDLEN157

XWDLEN157

“Bit” - one data bit per SP clock period

RFRLEN1814

XFRLEN1814

Basic Definitions - Frame

SP Ctrl (SPCR)Rcv Ctrl (RCR)Xmt Ctrl (XCR)Rate (SRGR)

Pin Ctrl (PCR)

Serial Port

“Frame” - contains one or multiple words

w0 w1 w2 w3 w4 w5 w6 w7

FrameWord

w6 w7D

FS

RFRLEN1814

XFRLEN1814

FRLEN1 specifies #words per frame (1-128)

Programming Peripherals with CSL and BSL


Programming Peripherals with CSL and BSL TI Software Foundation Libraries

Board Support Library (BSL) Board-level routines supporting DSK-specific hardwareHigher level of abstraction than CSLBSL functions make use of CSL

CodecLedsSwitchesFlash

Chip Support Library (CSL) Low-level routines supporting on-chip peripherals

Serial PortsEDMAEMIFCacheTimersEtc.

TI DSP

CSL helps with: 1. Configure Peripherals2. Managing Multiple Resources (e.g. McBSP channels)

What is CSL and BSL? The Chip Support Library (CSL) and Board Support Library (BSL) provide a set of data structures and functions to assist you in building a TMS320 DSP based system.

This library supports the use of the on-chip peripherals by providing a set of low-level functions and data structures to ease their implementation. CSL has been designed to support multiple invocations – such as you might find when using the multiple serial ports or DMA channels found on TI’s DSP devices.

Simplified directions for using the CSL are located in the lab exercises and in the appendix of this workshop. For complete details, please refer to the C6000 CSL Reference Guide (SPRU401.pdf).

BSL is build upon CSL. Essentially, BSL provides a higher-level system interface than CSL, taking into account the peripherals found on the board (but outside the DSP “chip”).



CSL Benefits Why CSL and BSL? Here are a few reasons:

Increased Portability • Supports all ‘C6000 DSPs. When changing from one device to another, no (or little) re-coding is

required for peripherals.

• Where possible, TI has used the same API’s for both the C5000 and C6000 DSP families. This makes porting C code between processors much easier. Taking into account the cross-platform support of DSP/BIOS makes TI’s software tools quite powerful.

• The goal is to provide compatibility at the _open(), _close(), _config() level. The initialization data structures may be different, but we have striven to make the functions as compatible as possible

Easier to use • When TI’s DSP 3rd parties and customers use the same CSL/BSL functions, it becomes easier to

use and understand code written by others.

Increased Reliability / Decreased Maintenance • When libraries such as CSL/BSL are made available to a large population of users, they become

more reliable. The large user base quickly finds any coding bugs (if any).

Additionally, suggestions and recommendations come from a large base of knowledgeable users.



Generic Procedure for CSL and BSL Here’s a rough description for using the CSL ( and BSL) libraries.

1. Include Header FilesLibrary and individual module header files

2. Declare variablesUsually handle & configuration

3. Open peripheralReserves resource; returns handle

4. Configure peripheralApplies your configuration to peripheral

5. Use peripheralSome periph’s have use-oriented functions(like read and write)

1. Include Header FilesLibrary and individual module header files

2. Declare variablesUsually handle & configuration

3. Open peripheralReserves resource; returns handle

4. Configure peripheralApplies your configuration to peripheral

5. Use peripheralSome periph’s have use-oriented functions(like read and write)

General Procedure for using

CSL & BSL

1. #include <csl.h>#include <csl_timer.h>

2. TIMER_Handle myHandle;TIMER_CONFIG myConfig = {control, period, counter};

3. myHandle = TIMER_open(TIMER_DEVANY, ...);4. TIMER_config(myHandle, &myConfig); 5. TIMER_start (myHandle);

Timer Example:

To some this syntax will appear quite familiar. To those of use who spent most of our careers writing assembly language, though, this may be a new method of programming.

These libraries provide two levels of support: • A set of macros, functions, and data structures to ease symbolic programming of the resource

(module). • Basic resource management.

Let’s see how the five parts of the timer example shown above correlate to these two ideas.

1. Include the appropriate header files.

As most of you already know, whenever you use a library, there are usually one or more header files you have to include. In the case of CSL, you must first include the general CSL.H file, and then the header file for each module of functions.

2. The first two lines of the example define the required data structures.

The data type called TIMER_Handle is defined in CSL. Essentially, it is used to point to one of the timers (as we will see later). Not all CSL modules require the use of a handle (i.e. pointer), only those peripherals where there is more than one resource. For example, timers, DMA, EDMA, McBSP, etc. The handle is used to specify which one of the timers you are working with.

The second line defines a data structure. The variable name is myConfig and its data type is TIMER_Config. Again, this data type is defined in the CSL. This variable represents a C data



structure that will be used to define a timer configuration. In other words, all the values you would need to program the timer peripheral are stored in this structure.

Note: The myHandle and myConfig names are arbitrary. We could have called them julie and frank. The choice is yours.

3. The third line of the example contains code that opens the peripheral. In this case, “open” means two things: • The CSL code checks to see if the specified resource has already been opened. In other

words, is the resource available? In this example, we have requested TIMER_DEVANY, which means we are asking for any available timer.

• If it is available, the timer resource is marked as being used and a pointer to the specific timer is returned as a TIMER_Handle. If the specific resource has already been opened, then the function returns “INV” for invalid. Your code could check if the INV error code has been returned. (We didn’t do that in our example since there wasn’t much room on the slide.

Where does the CSL keep track of opened resources? The CSL maintains a series of data elements (you could think of them as flags) to keep track of this information. Could you have done this? Yes, you probably could; but isn’t it nice to have this code already written for you? Even further, if you later decide to use this code on another ‘C6000 processor, you won’t have to find and change all the resource management code. You only need to indicate to the CSL that you have switched CHIPs and the rest is done for you automatically.

4. The fourth line of the example configures the peripheral. In this case, the timer specified by myHandle is configured with the myConfig data structure. The actual CSL code copies each of the values in the myConfig data structure to the appropriate memory-mapped peripheral registers. (How many times have I had to write this kind of code in assembly. I’d be pouring over the reference guide trying to type in all the bits and memory addresses without making a typo mistake – which, of course, happened too often.)

5. Finally, the last line of code is an example of how to use the peripheral. There are many functions that allow you to easily use the peripheral. In the case of the timer, we can: start, stop, pause, etc. With the McBSP serial port, you could: read, write, reset, etc.

Even if you have never written code along these lines before, you will find it quickly becomes second-nature. And if ease-of-use wasn’t enough reason to use CSL, the reliability, portability, and optimization features of CSL will make you never want to go back to the old ways.






CSL and BSL Documentation

CSL Reference Guide: SPRU401.PDF

CCS Help files: CC_C64xW.HLPor CC_C67xW.HLP

Examine source code (header files) located at:C:\ti\c6000\bios\include\csl_<MODULE>.h

e.g. C:\ti\c6000\bios\include\csl_mcbsp.h

C6000 CSL Documentation

DSK Board Support LibraryC6416DSK.HLP/C6713DSK.HLP – BSL Help fileReview the header source files (*.h)

C:\ti\c6000\dsk6416\include\dsk6416_<mod>.he.g. C:\ti\c6000\dsk6416\include\dsk6416_aic23.h

BSL Documentation

Hardware Interrupts (HWI)


Hardware Interrupts (HWI) How do Interrupts Work?

• DMA• HPI• Timers• Ext pins• Etc.

1. An interrupt occurs

3. CPU acknowledges interrupt and …• Stops what it is doing• Turns off interrupts globally• Clears flag in register• Saves return-to location• Determines which interrupt• Calls ISR

2. Sets a flag in a register

. . .

4. ISR (Interrupt Service Routine)• Saves context of system*• Runs your interrupt code (ISR)• Restores context of system*• Continues where left off*

* Can be performed by DSP/BIOS dispatcher

When an interrupt occurs (step 1), the corresponding bit is set in the Interrupt Flag Register (step 2). If the interrupt is enabled as shown in the next figure, the CPU will automatically acknowledge and respond to the interrupt (step 3 above).

Finally, the process reaches the Interrupt Service Routine (ISR), which you have to write. The ISR can be written in assembly or C, though nowadays most programmers choose to write their routines in C. There are a few methods of handling the context save and restore within your ISR; in this workshop we will show you the easiest, most robust method:

DSP/BIOS Hardware Interrupt Dispatcher



Enabling Interrupts

Receiving Interrupts

IER“Individual

Enable”

GIE“MasterEnable”

‘C6000CPU

IFRInterrupt

Flag0

1

0

XINT1(McBSP1 xmit)

EXTINT4(ext int pin 4)

etc …

Interrupt Flag Reg (IFR)bit set when int occurs

Interrupt Enable Reg (IER)enables individual ints

IRQ_enable(IRQ_EVT_XINT2)IRQ_enable(IRQ_EVT_XINT1)

Global Interrupt Enable (GIE) bit in Control Status Reg

enables all IER-enabled interruptsIRQ_globalEnable() IRQ_globalDisable()

The above diagram shows the logic flow an interrupt signal goes through to reach the CPU. As you can see, there are two ‘switches’ that must be enabled for the CPU to respond to an interrupt.

• Individual enable • Global enable

The diagram also shows the CSL functions that can be used to enable interrupts. A couple notes: • CSL enumerates each interrupt event; that is, we give each one its own name. The

example above demonstrates the event name for the McBSP2 transmit interrupt and the McBSP1 transmit event.

• While it’s handy to have CSL functions for enabling/disabling the global interrupt enable, you may not ever need to call them yourself. − First, interrupts are automatically enabled when the DSP/BIOS scheduler is started

(which occurs when you return from main). − Second, the DSP/BIOS interrupt dispatcher handles all the necessary global interrupt

enable/disable required when going into and out-of an ISR. (The dispatcher even makes nesting interrupts very easy – even when writing ISR’s in C.)

Lab 2


Lab 2 In this lab, we're going to use all of the information that we discussed in this chapter to send sine wave samples out through the McBSP connected to the AIC23 codec. We are going to use a HWI to synchronize the CPU to the codec rate.

CPU

DSK

DSP

HWI

AIC

sineGen McBSP

transmit interrupt

Lab 2 - Output a Sinewave


Use hardware interrupts to output a sine wave to the codec

Here are the goals of this lab: • Use the BSL for the DSK to open the codec • Use the Configuration Tool to set up a HWI for the McBSP • Write generated sine wave values to the codec

Lab 2


The Paperwork To get started, we are going to take a moment to think about what we need to do in this lab and put it down on paper. The file below is a copy of what you will need to write to finish this lab. Take a moment to figure out the value for each blank line, before moving on to enter the code on the computer. This way, you can think about what you are doing before you actually need to do it.

In order to fill in the blanks, you may need some help with the DSK's BSL. The good news is that excellent documentation for the BSL comes with DSK and Code Composer Studio. You just need to find it. Follow these steps to find the documentation for the BSL.

1. Open Code Composer Studio.

Use the desktop icon to open CCS.

2. Open up the CCS Help File.

Help → Contents

You should see something like this:

Take a look at the codec API summary. This lists most of the information that you will need

to complete the lab.

3. Please fill in the blanks in the file on the next page.

Lab 2


lab2.c #include " .h" // need DSK specific header file

#include " .h" // need AIC23 specific header file // Codec configuration settings

DSK6 _AIC23_Config config = { \ // which DSK are you using?

0x0017, /* 0 DSK6416_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6416_AIC23_RIGHTINVOL Right line input channel volume */\ headsetVol, /* 2 DSK6416_AIC23_LEFTHPVOL Left channel headphone vol */ \ headsetVol, /* 3 DSK6416_AIC23_RIGHTHPVOL Right channel headphone vol */ \ 0x0011, /* 4 DSK6416_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6416_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6416_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6416_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6416_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6416_AIC23_DIGACT Digital interface activation */ \

}; // Declare BSL Handle for AIC23 Codec /* * main() - Main code routine, initializes BSL and a hardware interrupt */ void main() { // Initialize the board support library, this must be called first // Open the codec // Enable the McBSP interrupt for IRQ_EVT_XINT2 (for 6416 DSK) // or Enable the McBSP interrupt for IRQ_EVT_XINT1 (for 6713 DSK) // Invoke DSP/BIOS scheduler return; } /* * myHWI() - ISR called when the McBSP wants more data */ void myHWI(void) { static short mySample; static int leftChan = 1; if(leftChan) { mySample = sineGen(); leftChan = 0; } else { leftChan = 1; } // Send a sample to the McBSP (which then sends it to the AIC23 codec) }

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Lab 2


lab2.c (hints) The 6416 (or C6713) DSK Board Support Library is divided into several modules, each of which has its own include file.

• First of all, the file dsk6416.h (or dsk6713.h) must be included in every program that uses the BSL. • You also need to include the header file for the AIC23 codec since this is the BSL module used in this exercise.

We created a structure called “config” which has the parameters needed to initialize the AIC23 codec. BSL creates a new datatype for this configuration information. We left part of this blank. The main reason we left it blank was because it the remaining three characters are specific to the DSK you are using (either C6416 or C6713).

DSK6???_AIC23_Config

By the way, to understand the values we chose for the AIC initialization; please refer to the DSK’s help file.

You need declare a handle for AIC23 codec. This step is similar to part of Step 1 as described for the generic CSL procedure (page 2-10). Similar to above, BSL creates a new datatype for the handle of the AIC23 codec.

The BSL library contains a BSL function to initialize itself. It must be called before any other BSL function. Take a look at this function in the DSK’s help file.

Next, you need to open the codec. The BSL function that opens the codec returns a handle. This step is similar to part of Step 3 as described for the generic CSL procedure (page 2-10).

FYI, the BSL function that opens the codec actually does a number of things:

− Opens both of the McBSPs it requires − Configures both McBSPs − Configures the AIC23 − Returns a handle to the AIC23 (which essentially points to the two McBSPs)

Looking at the block diagram for this lab (pg 2-16), we can see that we’re using the McBSP transmit interrupt to tell the CPU when to create another sine wave value and output it to the codec.

To allow this to happen, we must enable the McBSP transmit interrupt as shown on page pg 2-15. In this same diagram we listed the CSL function used to enable individual interrupts. Remember, though, that each DSK (C6416 vs C6713) uses a different McBSP to talk to the codec. In other words, you need to choose the correct transmit event name based upon which DSK you are using. (Rather than making you look up the event names for the McBSP transmit interrupts, we have provided the names for you in the code's comments.)

Note: The GIE bit is enabled automatically when you exit main() and return to the DSP/BIOS scheduler.

Once more, look for a BSL function which ‘writes’ a sample to the codec. You should be able to find this in the DSK help file.

Note: What really happens is that the codec write function writes the value to the McBSP data transmit register (DXR), which then sends it to the AIC23 codec, which then converts it to the analog signal which we hear.

Lab 2


lab2.c (answers) Note: For the C6713 DSK, just replace “6416” with “6713” in all the answers below.

#include " dsk6416 .h" // need DSK specific header file

#include " dsk6416_aic23 .h" // need AIC23 specific header file // Codec configuration settings

DSK 6416 _AIC23_Config config = { \ // which DSK are you using? 0x0017, /* 0 DSK6416_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6416_AIC23_RIGHTINVOL Right line input channel volume */\ headsetVol, /* 2 DSK6416_AIC23_LEFTHPVOL Left channel headphone vol */ \ headsetVol, /* 3 DSK6416_AIC23_RIGHTHPVOL Right channel headphone vol */ \ ...

}; // Declare BSL Handle for AIC23 Codec DSK6416_AIC23_CodecHandle hCodec; /* * main() - Main code routine, initializes BSL and a hardware interrupt */ void main() { // Initialize the board support library, this must be called first DSK6416_init(); // Open the codec hCodec = DSK6416_AIC23_openCodec(0, &config); // Enable the McBSP interrupt for IRQ_EVT_XINT2 (for 6416 DSK) // Enable the McBSP interrupt for IRQ_EVT_XINT1 (for 6713 DSK) IRQ_enable(IRQ_EVT_XINT2); or IRQ_enable(IRQ_EVT_XINT1); // Invoke DSP/BIOS scheduler return; } /* * myHWI() - ISR called when the McBSP wants more data */ void myHWI(void) { static short mySample; static int leftChan = 1; if(leftChan) { mySample = sineGen(); leftChan = 0; } else { leftChan = 1; } // Send a sample to the McBSP (which then sends it to the AIC23 codec) DSK6416_AIC23_write(hCodec, mySample); }

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Lab 2


Lab2 Procedure 4. Create a new project called LAB2.PJT in the C:\c60001day\labs\lab2 subdirectory.

Project → New…

You will encounter the Project Creation dialog. Fill in the Project Name and Location as shown below:

5. You can also use the … button to specify the correct path.

Create a CDB file As mentioned during the discussion, configuration database files (*.CDB), created by the Config Tool, control a range of CCS capabilities. In this lab, the CDB file will be used to automatically create the reset vector and perform memory management.

6. Create a new CDB file (DSP/BIOS Configuration…) as shown below:

If you are using the C6713 DSK, the Target field should read:

TMS320C67XX

Lab 2


7. CCS allows you to select a template configuration file. Since no simulator specific CDB template is available, we’ll choose the dsk6416.cdb or dsk6713.cdb template.

Select the dsk6416.cdb (or dsk6713.cdb) template

Note: In some TI classrooms you may see two or more tabs of CDB templates; e.g. TMS6xxx, TMS54xx, etc. If you experience this, just choose the ‘C6xxx tab and make your selection.

The CDB templates automate the process of setting up numerous system objects/parameters. Those shown above are shipped with the C6416 DSK. You can create your own CDB templates, just copy a CDB file you have created to the directory where the above files are stored (C:\ti\c6000\bios\include).

8. While there are many objects displayed in the configuration editor, we only need to configure one of them (which we’ll do starting in step 15). The other dsk6416 (or dsk6713) defaults will work fine.

9. Save your CDB file as LAB2.CDB in C:\c60001day\labs\lab2 directory.

File → Save As…

If you are using the C6713 DSK, please choose its template file:

dsk6713.cdb

Lab 2


Adding files to the project 10. You can add files to a project in one of three ways:

• Select the menu Project → Add files to Project… • Right-click the project icon in the Project Explorer window and select Add files… • Drag and drop files from Windows Explorer onto the project icon

Using one of these methods, add the following files from C:\c60001day\labs\lab2 to your project:

LAB2.C LAB2.CDB LAB2cfg.CMD block_sine.c

Add BSL Library to the project 11. We also need to add the DSK BSL library file to our project. Use one of the methods from

step 10 to add one of the two files to your project. (Please choose the library appropriate to your DSK).

c:\ti\c6000\dsk6416\lib\dsk6416bsl.lib

or

c:\ti\c6000\dsk6713\lib\dsk6713bsl.lib

Edit Files 12. Open lab2.c for editing by double-clicking on it in the Project Explorer pane.

13. Use your answers from the paperwork exercise back on page 18 to make the appropriate changes to lab2.c. You should find a place commented in the file to make each of the changes (one change has question marks for you to replace). If you have any questions, feel free to ask your instructor for help.

14. When you're done, save lab2.c.

Configure a HWI 15. Open lab2.cdb.

16. Navigate to the Scheduling folder inside the Configuration Tool.

17. Inside this folder, find the "HWI – Hardware Interrupt Service Routine Manager" and open it by clicking on the little + sign next to it.

18. You can pick any interrupt, from HWI_INT4 to HWI_INT15, that you want to use for the lab. The lab instructions are going to use HWI_INT12 (this was an arbitrary choice).

Lab 2


19. Open the properties of the interrupt that you chose by right-clicking and choosing Properties.

20. Change the “interrupt source” of the HWI interrupt number that you have selected to: • C6416: McBSP 2 Transmit Interrupt (MCSP_2_Transmit) • C6713: McBSP 1 Transmit Interrupt (MCSP_1_Transmit)

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Lab 2


21. Change the function property of the interrupt to call the myHWI() function (defined in lab2.c). You will need to add an underscore in front of the function name since it is a C function. Here's what it should look like:

Note: The TI C compiler (as with most compilers) differentiate C source labels from assembly source labels by prepending an “_” to all C labels as it generates assembly code. In this dialog box, the HWI function property requires an “assembly” label; hence, we need the underscore.

22. Click on the Dispatcher tab in the interrupt properties. We want to use DSP/BIOS's HWI Dispatcher to take care of everything (i.e. context save/restore) for the ISR. Enable the Dispatcher by clicking on the check box:

23. When you're all done with the changes, click on OK to save the HWI_INT properties.

24. Save the changes that you made to the .cdb file. Go ahead and close the .cdb file.

From the previous step. if you are using the C6713 DSK, the interrupt source should be:

MCSP_1_Transmit

Lab 2


Build and Run the code 25. Build your code.

Project → Build or click on

26. If your program doesn't load automatically, then load the program.

File → Load Program…

27. Run the program.

Debug → Run or click on

If everything is working correctly, you should hear a 500 Hz tone coming from the speaker or headphones connected to the DSK. If you don't, make sure everything is connected up to the DSK correctly. If you're having trouble, ask your facilitator for help.

Lab2a (optional)


Lab2a (optional) Now that you've successfully got the DSK to spit out some sound, wouldn't you like to be able to turn it off? Is there anything on the DSK that we might be able to use as a switch to turn the sine wave on and off? Yeah, the DIP switches could be used to do that.

Now, if we only had a function that made it easy to read one of the DIP switches. Do you think the BSL might have something like that? If so, you could simply read the DIP switch then decide whether to send a new sine wave sample or a 0 to the codec, effectively turning the sine wave off.

CPU

DSK

DSP

HWI

AIC

sineGen McBSP

transmit interrupt

Take Home Lab 2a – Use DIP Switch


Use DIP switch on DSK to turn the sine tone on/off

Here are the basic steps that you'll need to perform in order to do this: • In the HWI routine, right before you write the new sine wave to the codec, read a DIP switch.

− If the DIP switch is on, then write the sine wave value that you calculated. − If the DIP switch is off, simply write a 0 to the codec

• Don’t forget to add any necessary header files to your C file.

Lab 2 Debrief


Lab 2 Debrief Lab 2 Debrief

1. First, let’s quickly review the values we filled-in.

2. How much differs between the C6713 and C6416 solutions?

3. What would be the benefit if we could eliminate hardware specific references in our code?

Click Here to Open Lab2.c

1. Please refer to the solutions file for the results.

2. The differences are: • The BSL calls we had you complete in Lab2.c. • The CDB template file. • The reference to the BSL library.

3. If we eliminate the hardware specific references, we would could write and maintain a single piece of code for all C6000 platforms. This highlights two key points: • One, the consistency between families of the C6000 architecture makes porting code

between them very easy. Even more important, if you learn one family, you’ve basically learned all of them.

• The increased modularity and reuse of a single code-base used across multiple families usually enhances the stability and robustness of the code.

• DSP/BIOS device drivers (SIO/PIP/IOM) are discussed briefly in the next chapter. These can allow us to achieve hardware independence in our code.

C6416/C6713 DSK One-Day Workshop - eXpressDSP Tools 3 - 1

eXpressDSP Tools

Introduction TI provides solutions to DSP engineers facing ever increasing complexity in their systems. Providing efficient, capable code libraries, I/O driver schemes, certified Algorithm Standards, and extraordinarily robust starter applications (reference designs, so to speak).

While a single chapter in a one-day workshop cannot begin to describe the many details of these tools and libraries, hopefully we can give you a sense of what they offer and how they might help you finish your designs more quickly.

Outline Outline

Overview of eXpressDSPDSP/BIOS SchedulerReal Time AnalysisDevice Drivers (IOM)Algorithm Standard (XDAIS)Reference Frameworks (RF)

eXpressDSP Demo (based on RF3)

What is eXpressDSP?

3 - 2 C6416/C6713 DSK One-Day Workshop - eXpressDSP Tools

Chapter Topics eXpressDSP Tools ..................................................................................................................................... 3-1

What is eXpressDSP? ............................................................................................................................. 3-3 DSP/BIOS ............................................................................................................................................... 3-4

DSP/BIOS Scheduler.......................................................................................................................... 3-4 Real-Time Analysis ...........................................................................................................................3-11 Device Drivers (IOM) .......................................................................................................................3-13

TMS320 DSP Algorithm Standard (XDAIS) ..........................................................................................3-19 Introduction .......................................................................................................................................3-19 XDAIS (background info) .................................................................................................................3-20 Thousands of XDAIS Compliant Algorithms ...................................................................................3-24

Reference Frameworks ..........................................................................................................................3-25 RF3 Demo..............................................................................................................................................3-27

Inspect the .cdb file............................................................................................................................3-28 Use Real-time Analysis Tools ...........................................................................................................3-35

Flashing RF3 .........................................................................................................................................3-39 Create the Flash Image ......................................................................................................................3-39 Use Flashburn to Burn the Image ......................................................................................................3-41 Flashing POST...................................................................................................................................3-42

Lab/Demo Debrief .................................................................................................................................3-44 eXpressDSP Summary ...........................................................................................................................3-44

What is eXpressDSP?


What is eXpressDSP? What is eXpress DSP?

A premier, openDSP software strategy

for TI’s LeadershipTMS320 DSP Family

XDAISDSP/BIOSCCS

3rd Party Network

Target Content

DSP/BIOS


DSP/BIOS DSP BIOS Consists Of:

Real-time analysis toolsAllows application to rununinterrupted while displayingdebug data

Real-time schedulerPreemptive thread mgmtkernel

Real-time I/O (Drivers)Allows two-way communication between threads or between threads and hardware

DSP/BIOS Scheduler

DSP/BIOS Thread Types

Prio

rity

HWIHardware Interrupts

Used to implement 'urgent' part of real-time eventTriggered by hardware interruptHWI priorities set by hardware

SWISoftware Interrupts

Use SWI to perform HWI 'follow-up' activitySWI's are 'posted' by softwareMultiple SWIs at each of 15 priority levels

TSKTasks

Use TSK to run different programs concurrently under separate contextsTSK's are usually enabled to run by posting a 'semaphore‘ (a task signaling mechanism)

IDLBackground

Multiple IDL functions Runs as an infinite loop, like traditional while loop

DSP/BIOS


DSP/BIOS Scheduler (background information)

TI DSP

Example – Multi-Rate System

Previous RequirementLet’s say we originally had only one algorithm to execute

New RequirementThen we’re asked to add a second algorithmAlgo2 independent of Algo1Issues:

Do we have enough bandwidth (MIPS)?Will one routine conflict with the other?

Algo1

Algo2

While Loop?

Possible Solution – “While” Loop

Algo2

Algo1

main{while(1){

}}

Potential Problems:

Algos run at different rates:Algo1: 8kHzAlgo2: 4Hz

What if one algorithm starves the other for recognition or delays its response?

Put each routine into an endless loopunder main

DSP/BIOS



running

idle

Time 1 2 3 54 6 70

Possible Solution – Use Interrupts (HWI)

Period Compute CPU Usage

Algo1: 125 µs 7 µs 6%

main{

while(1);}

Timer1_ISR{

}

Timer2_ISR{

}Algo2

Algo1

An interrupt driven system places each function in its own ISR

Interrupt is missed…

Algo2: 250 ms 100 ms 40%

46%

Allow Preemptive Interrupts - HWI

Use DSP/BIOS HWI dispatcher for context save/restore, and allow preemptionReasonable approach if you have limited number of interrupts/functionsLimitation: Number of HWI and their priorities are statically determined, only one HWI function for each interrupt

running

idle

Time 1 2 3 54 6 70

Nested interrupts allow hardware interrupts to preempt each othermain

{while(1);

}

Timer1_ISR{

}

Timer2_ISR{

}Algo2

Algo1

DSP/BIOS


Software Interrupts (SWI)

Use Software Interrupts - SWI

main{ …// return to O/S;}

DSP/BIOS

Make each algorithm an independentsoftware interruptSWI scheduling is handled by DSP/BIOS

HWI function triggered by hardwareSWI function triggered by software, e.g. a call to SWI_post()

Why use a SWI?No limitation on number of SWIs, and priorities for SWIs are user-defined!SWI can be scheduled by hardware or software event(s)Defer processing from HWI to SWI

Algo2

Algo1

HWIs signaling SWIsInterrupt

HWI:urgent codeSWI_post();

SWI

ints disabled rather than all this time

read serial port process data (filter, etc.)

HWIFast response to interruptsMinimal context switchingHigh priority onlyCan post SWICould miss an interrupt while executing ISR

SWILatency in response timeContext switch performedSelectable priority levelsCan post another SWIExecution managed by scheduler

DSP/BIOS


Tasks (TSK)

Another Solution – Tasks (TSK)

main{ …// return to O/S;}

DSP/BIOS

DSPBIOS tasks (TSK) are similar to SWI, but offer additional flexibilityTSK is more like traditional O/S taskTradeoffs:

SWI context switch is faster than TSKTSK module requires more code spaceTSKs have their own stack

User preference and system needs usually dictates choice. It’s easy to use both!Algo2

Algo1

SWIs and TSKs

Similar to hardware interrupt, but triggered by SWI_post()All SWI's share system software stack

SWI SWI_post

start

end

“run tocompletion”

SEM_post() triggers execution

Each TSK has its own stack, which allows them to pause

TSK

start

end

Pause

SEM_post

(blockedstate)

SEM_pend

DSP/BIOS


Enabling BIOS – Return from main()

main{ …// return to BIOS}

DSP BIOS

Algo2

Algo1

The while() loop is removedmain() returns to BIOS IDLE allowing BIOS to schedule events , transfer info to host, etcA while() loop in main() will not allow BIOS to activate

BIOS Scheduler In Action

Priority Based Thread SchedulingHWI 2

HWI 1

SWI 3

SWI 2

SWI 1

MAIN

IDLEint1

rtn

post2 rtn

int2

post3 rtn

post1 rtn

rtn

rtn

User sets the priority...BIOS does the scheduling

(highest)

(lowest)

SWI_post(&swi2);

DSP/BIOS


SWI Properites & Setting their Priorities

SWI Properties

Managing SWI Priority

Drag and Drop SWIs to change priorityEqual priority SWIs run in the order that they are posted

Drag and Drop SWIs to change priorityEqual priority SWIs run in the order that they are posted

DSP/BIOS


Real-Time Analysis

DSP BIOS Consists Of:


Real-Time Analysis ToolsGather data on target (3-10 CPU cycles)Send data during BIOS IDLE (100s of non-critical cycles)Format data on host (1000s of host PC cycles)Data gathering does NOT stop target CPU

Analyze time NOT spent in IDLE

CPU Load Graph

Execution GraphSoftware logic analyzerDebug event timingand priority

DSP/BIOS


Built-in Real-Time Analysis Tools

Statistics ViewProfile routines w/ohalting the CPUCapture & analyze data without stopping CPU

LOG_printf (&logTrace, “addSine ENabled”);

Send debug msgs to hostDoesn’t halt the DSPDeterministic, low DSPcycle countMore efficient thantraditional printf()

Message LOG

RTDX: Real-Time Data Exchange

PC TMS320 DSP

JTAG

E M

U

R T

D X

USE

R C

OD

E

Third PartyDisplay

CCS

RTDX enables non-obtrusive two-way communicationbetween the host PC and the DSP (during IDLE)

Transfer speed dependent on JTAG bandwidth,connection type (parallel vs. XDS) and DSP activity level

Transfers made via RTDX calls in DSP application code

Display

UserTI3rd Party

DSP/BIOS


Device Drivers (IOM)

DSP BIOS Consists Of:


Real-time schedulerPreemptive thread mgmtkernel

Real-time I/O (Drivers)Allows two-way communication between threads or between threads and hardware

Access Hardware Directly or Use a Device Driver?

Directly Accessing Hardware

App writes to hardware directly using the the specific target’s BSL functionsEvery application needs to be customized to hardware:You must change each instance of DSK6416_xxx to another function call every time you port the codePortability suffers

void audioLoopBack() {DSK6416_AIC23_CodecHandle hCodec;short buf[64];int N;

DSK6416_init();

/* Start the codec */hCodec = DSK6416_AIC23_openCodec(0, &config);

while () {for (N = 0; N < 64; N++) {

while (!DSK6416_AIC23_read(hCodec, buf[N]));while (!DSK6416_AIC23_write(hCodec, buf[N]));

} }

}

AppCodec McBSP

DSK6416_AIC23_

DSP/BIOS


Abstracting Hardware with Drivers

Device Drivers standardize the interface between the Application and the H/WApplication programmer only has to know PIP or SIO (no matter what H/W is connected)The H/W can be changed without changing the Application (only need to change IOM included in project)Therefore, Drivers (SIO/PIP with IOM) insulate the Application from the hardware’s details

IOM AppSWI or

TSKSIOor PIP

Codec McBSP

DSP/BIOS I/O Models (background information)

BIOS I/O Models

DSP/BIOS providedClass Drivers

Mini-Driver(IOM)

DSP/BIOSThread Types

SIO

TSK or SWI

PIP

SWI

Any mini-driver (IOM) can be used with any DSP/BIOS I/O model

Application Programmer chooses the preferred class driverInterface is consistent regardless of which device (mini-driver) connectedSoftware interface doesn’t change, even if you change the IOM device

DSP/BIOS


Pipe I/O Model (PIP)

Using DSP/BIOS PIP Drivervoid audioLoopBack() {

// get the full buffer from the receive PIPPIP_get(&pipRx);

// get the empty buffer from the transmit PIPPIP_alloc(&pipTx);

// Put the transmit buffer; Free the receive bufferPIP_put(&pipTx);PIP_free(&pipRx);

Think of PIP (pipe) as a buffer manager with built-in signaling:The ‘reader’ gets signaled when data is availableThe ‘writer’ gets signaled when the buffer is emptied

Use it from SWI ↔ SWI or between SWI ↔ hardwareA common interface for all C5000 & C6000 DSP’s

Bottom Line: Application Code never changes even if you change H/W

Stream I/O Model (SIO)

Using SIO Drivers// Run forever looping-back buffers

for (;;){

// Reclaim full buffer from the input streamSIO_reclaim(inStream, (Ptr *)&inbuf, NULL))

// Reclaim empty buffer from output stream and reissueSIO_reclaim(outStream, (Ptr *)&outbuf, NULL)SIO_issue(outStream, inbuf, nmadus, NULL)

// Issue an empty buffer to the input streamSIO_issue(inStream, inbuf, SIO_bufsize(inStream), NULL)

}

SIO (Stream I/O) is another DSP/BIOS device driver methodologyThink of issuing and reclaiming buffers from a streamBottom Line: Application Code doesn’t change even if hardware does

SIO (Stream I/O) is another DSP/BIOS device driver methodologyThink of issuing and reclaiming buffers from a streamBottom Line: Application Code doesn’t change even if hardware does

Some further notes about SIO: • SIO (Stream I/O) is another DSP/BIOS device driver methodology • Handles queuing of buffers to/from devices • “Issue” a buffer to a stream

• Issue full buffer to a transmit stream • Or, empty going to a receive stream

• Conversely, “reclaim” a stream buffer • Full from a receive stream • Empty from a transmit stream

DSP/BIOS


And here’s a little larger code sample we couldn’t fit in the slide. / Prime the stream buf0 = (Ptr)MEM_calloc(0, 64, BUFALIGN); … buf3 = (Ptr)MEM_calloc(0, 64, BUFALIGN); // Issue the two empty buffers to the input stream */ SIO_issue(inStream, buf0, SIO_bufsize(inStream), NULL); SIO_issue(inStream, buf1, SIO_bufsize(inStream), NULL); // Issue the two empty buffers to the output stream */ SIO_issue(outStream, buf2, SIO_bufsize(outStream), NULL); SIO_issue(outStream, buf3, SIO_bufsize(outStream), NULL); // Run forever looping-back buffers for (;;){ // Reclaim full buffer from the input stream SIO_reclaim(inStream, (Ptr *)&inbuf, NULL)) // Reclaim empty buffer from output stream and reissue SIO_reclaim(outStream, (Ptr *)&outbuf, NULL) SIO_issue(outStream, inbuf, nmadus, NULL) // Issue an empty buffer to the input stream SIO_issue(inStream, inbuf, SIO_bufsize(inStream), NULL) }

Please refer to the code examples that ship with the DSK for a full, working example using this code.

DSP/BIOS


A closer look at IOM

And here’s a closer look at the functions and data structures that make up an IOM driver.

Mini-Driver Interface (IOM)Maximum Reuse and Portability

One I/O mini-driver (IOM) interface to support all TI Class drivers.

IOM Interface Consists Of:

Functions:init functionIOM_mdBindDevIOM_mdUnBindDevIOM_mdControlChanIOM_mdCreateChanIOM_mdDeleteChanIOM_mdSubmitChaninterrupt routine (isr)

Data Structures:BIOS Device Table

IOM function tableDev param’sGlobal Data Pointer (device inst. obj.)

Channel ParamsChannel Instance Obj.IOM_Packet (aka IOP)

Driver Developement Kit (DDK)

Driver Developer Kit (DDK) Support

3rd Party SolutionAIC23

6416DSK

Beta AIC23

Beta AIC23BetaBetaDM642

EVM

6416 VT1420

PCM30026416TEB

AIC236713DSK

(External)AD535ExternalExternal6711DSK

UtopiaS/WUART

H/WUARTMcASPMcBSPEMACPCI

Video Capture / Display

Platform*

DDK v1.0DDK v1.1DDK v1.2 (3Q03)

DDK v1.0DDK v1.1DDK v1.2 (3Q03)Provided Royalty Free

Requires CCS v2.2 or greaterSearch for “DDK” on the TI website to download

* We have only included C6000 systems in this table

DSP/BIOS


Software Foundation Layers As you can see, the software libraries and models discussed over the past two chapters build upon each other:

TI Software Foundation Model

Chip Support Layer TI CSL

Board Support Layer DSK’s BSL

DSP/BIOS Communications

Layer

SIO / PIP

IOM

TMS320 DSP Algorithm Standard (XDAIS)



Introduction

Buying AlgorithmsWhy is it hard to integrate someone else’s algo?1. Don’t know how fast it runs …

… or how much memory it uses.2. How can I adapt the algorithm to meet my needs?3. Will the function names conflict with other code in the system?4. Will it use memory or peripherals needed by other algo’s?5. How can I run the same algo on more than one channel at a

time? (How can I prevent variables from conflicting?)6. How many interfaces (API’s) do I have to learn?

Traditional SolutionWhen I buy an algorithm, “I need the source code (and lots of development time) or I can’t guarantee it will work.”But, purchasing source code costs a lot of money!

ALGORITHMPRODUCERS

Write once, deploy widely

ApplicationAlgorithm

Off-the-shelf DSP content

Ease of integration

Purchase once, use widely

SYSTEMINTEGRATORS

TMS320™ DSP AlgorithmStandard

Specification(“XDAIS”)

Rules & Guidelines Applied to Algorithm Software Modules

Programming RulesStandard Interface Defined by TIAlgorithm PackagingAlgorithm Performance

TEXASINSTRUMENTS

TI TMS320 DSP Algorithm Standard



Overview of the XDAIS RulesGeneral “Good Citizen” Software Coding Rules

C callable & ReentrantNaming conventions enforced to avoid symbol clashes No direct peripheral interface or memory allocationRelocatable data and code in both static and dynamic systemsNo thread scheduling nor any awareness of controlling appPure data transducer; cannot alter the DSP environment

Standard Algorithm Interface defined by TIDefines a memory management protocol between application and algorithm for all compliant algorithm modules

Packaging RulesAll algorithms packaged and delivered in a consistent format

Documentation RulesAlgorithms must provide basic memory and performance information to enable “apples to apples” comparisons and to aid system designers with algorithm integration

XDAIS (background info) Let’s look at six problems XDAIS solves – step by step

XDAIS Solution (1)1. Don’t know how fast it runs … or how much memory it uses.

Strict rules on vendor-provided documentation (PDF file).



XDAIS Solution (2)2. How can I adapt the algorithm to meet my needs?

Vendor supplies “params” structure to allow user to describe any user-changable algorithm parameters.

For Example, a filter called IFIR might have:

typedef struct IFIR_Params {Int size;XDAS_Int16 firLen;XDAS_Int16 blockSize;XDAS_Int16 * coeffPtr;

} IFIR_Params;

typedef struct IFIR_Params {Int size;XDAS_Int16 firLen;XDAS_Int16 blockSize;XDAS_Int16 * coeffPtr;

} IFIR_Params;

XDAIS Solution (3)3. Will the function names conflict with other code in the system?

Algorithm must be C callable and re-entrantStrict rules on function naming virtually eliminate conflicts.

fir_company123_min.l64

AlgorithmModule Name

VendorName Variant

L: libraryh: header62: C62x/C67x64: C64x

fir_company123_max.h62

XDAIS Solution (4)4. Will it use memory or peripherals needed by other algo’s?

Application controls all peripherals and memoryAlgorithms cannot access peripherals directlyAlgorithms cannot allocate their own memoryPre-defined XDAIS functions provide a common method for algorithms to request resources:

Algorithm Application(framework)

MemoryDuring algo startup,it ‘requests’ any

memory it requires

Application grants memory via *address

*ptr*ptr

malloc()



This type of dynamic instantiation sounds great, but what if I want to allocate my memory statically? No problem, XDAIS algorithms can be designed to work both ways. And there’s even a utility that will interrogate an algorithm and create a C file containing all the required memory elements of an algorithm. That is, we’ll even help you with your static instantiation.

Supports Static & Dynamic Instances

*Note: Static case can also use “algActivate” if algo uses “scratch” memory

DynamicStatic

algFreeDelete

ExecuteFilteralgActivateFilteralgDeactivate

algInitCreate

algNumAllocalgAllocalgInit

Framework(algorithm lifecycle)

Here’s a more detailed look at the process of creating an instantiation of an algorithm. (Sorry we don’t have time to go through this example in class.)

Instance Creation - start

Params

ApplicationFramework Algorithm

1. Here’s the way I want you to perform…

*params = malloc(x);params=PARAMS;

algNumAlloc()

2. How many blocks of memory will you need to do this for me?

3. I’ll need “N” blocks of memory to do what you’ve specified…

N4. I’ll make a place where

you can tell me about your memory needs…

*memTab = malloc(5*N)MemTab



MemTab

Instance Creation - finish

Params

ApplicationFramework Algorithm

algAlloc()5. Tell me about your

memory requirements…

7.I’ll go get the memory you need…

6. My needs, given these parameters, are this, for each of the N blocks of memory

8. Prepare an instance to run!

algInit()9. Copy Params and

memory bases into my instance object…

InstObjParam1Param2

…Base1Base2

…N

sizealignment

typespace*base

for(i=0;i<=N;i++)base=malloc(size);

instObj1

instObj2

Each algorithm gets it’s own ‘storage’ location called an instance object.

XDAIS Solution (5)

IFIR algorithm: Instance 1

*fxns → Pointer to algo functions

*a → Pointer to coefficients

*x → Pointer to new data buffer

5. If I want to run the same algo on more than one channel …How can I prevent variables from conflicting with each other?

IFIR algorithm: Instance 2

*fxns*a*x

XDAIS Solution (6)6. How many interfaces (API’s) do I have to learn?

Only one … XDAIS!And, TI provides a tool that essentially writes the XDAIS interface, though you still need to add your magic.



And finally, here’s a little diagram showing most of the XDAIS algorithm interface.

firHandle->fxns=&FIR_TTO_IFIR;firHandle->fxns->ialg.algInit((IALG_Handle)firHandle, memTab,NULL,(IALG_Params *)&firParams);firHandle->fxns->filter(firHandle,processSrc,processDst);

XDAIS Summary

Key:User

VendorModuleXDAIS

...…

FIR_TTO_initObj…

FIR_TTO_filter…

IFIR_Fxnsalg ...alg ...algInitalg …filter…

instance

fxnshandle

Program Memory

memTab......

params

Thousands of XDAIS Compliant Algorithms

3rd Party XDIAS Compliant Algo’sMake or buy…

> 650 companies in 3rd party network

> 1000 algorithms from > 100 unique 3rd parties

Tools of the Trade

Reference Frameworks


Reference Frameworks IOM and XDAIS: Common Interfaces

With standardized interfaces to Algorithms and H/W, system software (i.e. framework) can also be standardized

System

H/W(Peripherals) Algorithm

XDAIS

IOM Data

InitMem. Mgmt.

SystemSoftware

A “standard” framework can be used as a starting point for many different Applications

Currently, three generic frameworks are availableAlso, application specific frameworks available (or coming) for specific applications (audio, video, etc.)


Implements DSPLink (DSP↔GPP)tbd25KW11KW3.5KWTotal Memory Footprint (less algos)

HWI, SWI, TSKHWI, SWI, TSKHWI, SWIHWISupports

None Currently

C5000C6000

C5000C6000C5000Processor Family Supported

Implements Control FunctionalityThread Preemption and Blocking

multimultimultisingleSingle/Multi Rate OperationAbsolute Minimum Footprint

1 to 1001 to 1001 to 10+1 to 3Recommended # of XDAIS Algos1 to 1001 to 1001 to 10+1 to 3Recommended # of Channels

Dynamic Memory AllocationStatic Memory ManagementDynamic Object CreationStatic Configuration

RF6RF5RF3RF1Design Parameter

Planned, but not yet available

CompactFlexible

ConnectedExtensive



SWI Audio 1

RF3 Block Diagram (out of the box)

Split SWI Join SWIIn OutPIP

IOM IOM

SWI Audio 0

FIR Vol

FIR Vol

Control Thread(swiControl)

Memory Host (GEL)clkControl

IOM Drivers for input/outputTwo processing threads with generic algorithmsSplit/Join threads used to simulate stereo codec. (On C6416/C6713 DSKs, how could we save cycles on split/join?)

PIP

The Reference Frameworks available today provide a SWI thread which creates the stereo audio used by the audio processing threads. This was necessary for the early DSKs since they only supported mono audio. In the case of mono audio input, the Split thread just duplicated the audio to both channels. Today, with stereo codec’s the Split thread sorts the two incoming channels into two different ‘channels’.

How could you make the above system more efficient? How about re-writing the IOM driver so that it uses the EDMA to perform the channel sorting. The IOM interface supports multi-channels, thus you should be able to directly connect it to both of the Audio Processing PIP’s.

RF3 Demo


RF3 Demo Here are the steps the facilitator will go through during the in-class demo. These were included to allow you to go back through the demo at your own pace, and to explore further any additional aspects of RF3 that you find interesting.

Note: This demo assumes that your Code Composer Studio installation is setup just like we did it back in Lab 1 and that the files that we provided you are installed on the computer that you are using. If either of these are NOT true, then you may have some difficulty with the following steps.

Opening the Project 1. We have provided the files needed for RF3. We have installed them in the default install

directory for the Reference Frameworks to avoid any problems with relative directory names during build. So, you'll need to go to a different location than you did for the other labs in the workshop.

Use the following command to open the RF3 project for the 6416 DSK which is located at:

C:\c60001day\referenceframeworks\apps\rf3\dsk6416, or

C:\c60001day\referenceframeworks\apps\rf3\dsk6713

Project → Open…

2. Once you have opened the project, the Project View window should look something like this:

RF3 Demo


Inspect the .cdb file Most of RF3 is configured via the Configuration Tool. Since this file has a lot of the cool stuff provided by RF3, we're going to take a look at it first.

3. Open the apps.cdb file by double-clicking on it in the Project View.

Hardware Portability One of the best characteristics of RF3 (and the other reference frameworks for that matter) is that they can easily be ported to a new hardware platform. Getting useful applications up and running on a new hardware design used to be a difficult task. RF3 is built using IOM drivers. All of the hardware specific code is encapsulated in the driver. Let's take a look at how this is done.

4. Inside the .cdb file, navigate to the udevCodec object which is located in the User-Defined Devices folder under Device Drivers. The Device Drivers folder is in the Input/Output folder. It looks something like this:

Most of the hardware specific information is contained in this one object. So, where is the

other stuff? Here is a list of the few places that are hardware specific: • The library that actually contains the code that the udevCodec object refers to is

referenced in the linker command file: link.cmd. • There is a C file, dsk6416_devParams.c (or dsk6713_devParams.c), that contains the

parameters for how to setup the hardware controlled by the driver. − One of these parameters is the hardware interrupt that will be used by the driver to

synchronize with the CPU.

RF3 Demo


5. As we just mentioned, most of the hardware specific information needed to talk to the codec for RF3's audio is contained in this object. Open the properties of the object by right-clicking on it and choosing properties to see this information:

Since most of the hardware specific information is contained in this one object, it is the main

place that needs to change in order to talk to new hardware.

6. Close the udevCodec Properties box by clicking "Cancel".

I/O Flexibility The IOM driver interfaces to a DSP/BIOS PIP. A PIP is a simple buffer manager with synchronization capabilities. RF3 uses PIPs to flow data from hardware (an IOM driver) to software processing engines called threads. To see all of the PIPs and how they connect things together refer back to the diagram at the beginning of the lab.

7. Let's take a look at how a PIP connects a driver to a thread by looking at the properties of the receive PIP. This is the PIP that connects the input device driver (audio source) to the receive/split thread.

Navigate to the PIP – Buffered PIP Manager which is inside the Input/Output folder in the .cdb file.

8. Open the properties of the pipRx PIP by right-clicking on it and choosing properties.

Obviously, the C6713 DSK version is similar but uses symbols that begin with:

_DSK6713…

RF3 Demo


9. Click on the "Notify Functions" tab. You should see something that looks like this:

This interface makes it easy to change who gets notified when a PIP needs to be written to or

needs to be read. The thread structures that RF3 uses also make it easy to change which PIP a thread is talking to. All of these capabilities work together to make the RFs great places to start a design because they are powerful and easy to adapt to different needs.

10. Click "Cancel" to close the properties box.

11. Feel free to look at the other PIPs in the application if you'd like. Make sure to refer back to the block diagram at the beginning of this discussion to see how things fit into the big picture.

Processing Threads Flexible I/O and drivers are important, but come on, the whole reason for their being is to feed data to functions for processing. RF3 uses DSP/BIOS Software Interrupts (SWIs) to run processing functions. SWIs are very similar to hardware interrupts (HWIs), but they are controlled by software through API calls by the program. For example, the SWI_andnHook() function in the PIP properties that we looked at earlier is a BIOS API call that notifies a SWI that one of the conditions that it needs to run has been met. When all of the conditions have been met, the SWI is readied by the scheduler and it runs when it is the highest priority thread that needs servicing.

12. Let's take a look at the SWIs in RF3. Navigate to the "SWI – Software Interrupt Manager" that is located in the Scheduling folder in the .cdb file.

Notifies the driver when an empty buffer is available.

Notifies the thread when a full buffer is available.

RF3 Demo


13. You should see the following SWI objects:

Name Purpose

swiAudioProc0 Runs volume and filter for channel 0

swiAudioProc1 Runs volume and filter for channel 1

swiControl Runs control thread periodically (more info. later)

swiRxSplit Splits incoming data flow into two channel flows

swiTxJoin Combines two channels into outgoing data flow

Don't forget to refer back to the block diagram and see how everything fits together.

14. Let's take a closer look at the swiRxSplit thread to see what function it calls when it runs. Open the properties of swiRxSplit by right-clicking on it and selecting properties. You should see something like this:

Here are some details on the different properties:

Name Purpose

comment Allows user to comment the object in the .cdb file

function Function that is called by the SWI

priority Priority that the SWI executes at

mailbox Used with APIs to signal the SWI (more info. later)

arg0, arg1 Arguments to function (i.e. _thrRxSplitRun(arg0,arg1) )

RF3 Demo


15. When you're done examining the SWI object, click "Cancel" to close the window.

16. Take a moment to find all of the threads that are listed in the .cdb file in the block diagram.

Taking Control RF3 has a built in control function to change the execution of the processing algorithms at run-time. It uses this thread to modify the volume that each of the channels is played at. It can easily be modified to do just about anything else that you might want to do to control your application.

17. The control function is executed by swiControl. Open and examine the properties of swiControl.

18. When should the application tell swiControl to run? Normally, a control thread would run when a user changed something. For example, turning up the volume on your MP3 player. Well, the DSK only has a few inputs and they're not really tied to the application. So, RF3 simulates user activity by calling the control thread on a periodic basis. RF3 calls swiControl from a Timer HWI routine that BIOS sets up.

Navigate to the "CLK – Clock Manager" in the Scheduling folder.

Sidebar: SWI Mailboxes

Each bit in the swiRxSplit mailbox represents a pre-condition. The SWI should only run when there is a full buffer to split and two empty buffers to fill. Three preconditions with a bit each needs three bits, or 0x7.

The SWI_andnHook() function is a BIOS API call that can only be called from within BIOS (that's why we add Hook) and it essentially clears a bit in the mailbox when it runs. When all the bits are zero, the SWI is automatically scheduled to run.

swiRxSplit

111

pipRx0 notifyWriter:SWI_andnHook(swiRxSplit, 2)

pipRx notifyReader:SWI_andnHook(swiRxSplit, 1)

pipRx1 notifyWriter:SWI_andnHook(swiRxSplit, 3)

mailbox

RF3 Demo


19. You should see a clkControl object. Open up its properties to examine them. You should see something like this:

The thrControlIsr() function reads the control values into a control structure then posts

swiControl to apply the changes.

20. Click Cancel to close the clkControl Properties window.

Analyzing Priority Since we've got all of these threads running around processing data and providing control, the question might come up about priority. So, let's take a look at how priorities are assigned in RF3.

21. DSP/BIOS makes it really easy to compare SWI priorities.

Click on the SWI – Software Interrupt Manager. You should see something like this:

From this picture of the .cdb file we can see that all of the threads are currently set to priority

level 1. It turns out that RF3 doesn't really need any of the threads to run at different priorities. However, if your application did need to use priority, it is easy to make the changes here by dragging and dropping the SWI objects to the desired priority level.

RF3 Demo


Getting Feedback RF3 uses a variety of DSP/BIOS Real-time Analysis Tools to provide feedback about the application. The DSP/BIOS LOG module is used to send general information about the state of the application (things like trace information and dynamic memory or heap activity) back to the user. The BIOS STS (Statistics) module is used to calculate timing information. All of this is done without ever halting the DSP Target application.

22. You can see the objects for either of these modules in the Configuration Tool under Instrumentation.

Take a moment to look at these objects and we'll show you how they're used here in a bit.

Build and Run the Application To reduce their size and speed downloads, the RFs are not shipped built. There are make files provided to build everything if you choose to use them. Since we don't need to build them all, we'll build the RF3 that we've been looking at by itself using Code Composer Studio.

23. Build the RF3 application, app.pjt.

Project → Build or click on

24. If you have CCS configured properly (or at least the way we had you do it back in lab 1), the application should automatically load and go to main().

25. Make sure your DSK is set up properly for audio. Plug an audio source (CD Player, computer sound card, etc.) into the line in on the DSK. You can use either speakers or headphones for the audio output. Plug speakers into the line out. Plug headphones into the headphone out.

26. Make sure there is audio playing at the source.

27. Run the application.

Debug → Run or press F5 or click on

28. You should hear audio playing. If not, double-check all of your connections.

RF3 Demo


Use Real-time Analysis Tools DSP/BIOS automatically collects a lot of data about your application as it runs. RF3 extends this capability to send a wealth of information about the target application to the host. In this section we'll use special tools inside CCS to view and examine this information.

CPU Load Graph DSP/BIOS automatically calculates the load your application puts on the processor. This information provides a nice quick snapshot of how your application is running.

29. Open the CPU Load Graph.

DSP/BIOS → CPU Load Graph or click on

You should see something like this:

As you can now see, the RF3 application (including algorithms) is only taking up a very

small amount of the CPU's time.

Message Log The DSP/BIOS Message Log provides printf() like capability at a much lower cost (memory and MIPS) to the target application. RF3 provides a module called UTL that powerfully extends the basic LOG module.

30. To see the output of the BIOS LOG, open a Message Log.

DSP/BIOS → Message Log or click on

RF3 Demo


31. Examine the output of the Message Log:

Statistics The DSP/BIOS STS (Statistics) Module provides an easy way to get timing information about the threads in your application. For example, in real-time systems, designers are usually concerned with the maximum execution time of a thread. If a thread's maximum execution time ever exceeds its deadline, then you know you have a problem.

32. Open the DSP/BIOS Statistics View.

DSP/BIOS → Statistics View or click on

Amount of memory needed by XDAIS Volume algorithm

Heap Allocations

RF3 Demo


You should see a window that looks like this:

This window gives you a lot more detail regarding the execution times of your threads.

33. This window can be modified in several ways. Right-click on the window and choose properties. Inside this window you can enable and disable the statistics for each thread, change the unit that the timing information is displayed in (instructions, microseconds, and milliseconds), etc.

Try changing the swiRxSplit thread so that it displays in Microseconds.

Viewing the Execution Graph The Execution Graph is a graphical view of how your threads are executing. It is based on events that happen in the scheduler. Events are things like a SWI being posted, a SWI starting to run, a SWI finishing, etc. This graph is not time based, but the Time scale at the bottom can help associate events with time.

34. Open the Execution Graph.

DSP/BIOS → Execution Graph or click on

35. The tray at the bottom where all of these tools are being opened is probably getting a little full. Also, the Execution Graph needs a lot of screen real estate.

To make it easier to see and work with, float the Execution Graph in the main window.

Right-Click on the Execution Graph, choose "Float in Main Window"

RF3 Demo


36. You should now see a window that looks something like this:

Each column in the graph indicates that an event happened. The blue indicates that a thread is

running. The white boxes represent that a thread is waiting for its turn to run. The teal green or dark lines indicate that the graph doesn't know what state a thread is in (running, waiting, or not doing anything). The reason for the green lines relates directly to the vertical red line. The red line indicates that the circular buffer that was being used to accumulate the information on the target wrapped around and overwrote some data. This indicates that there is a discontinuity in the data being displayed. Since the graph is essentially starting over, it doesn't know what state a thread is in until its state changes. The horizontal time line at the bottom has a little tick in it when the timer interrupt fires. This line can be used to relate the event based data to time.

The threads are usually listed by priority, but since we only have one priority they are listed in the same order that we found them back in step 21. You could change this order in the Configuration Tool just like you changed priority.

Playing with GEL The Control Thread in RF3 reads memory values and uses them to change how the algorithms execute. We can use a CCS GEL file to change these memory locations and control the application.

37. Load the provided app.gel file which is located in the same directory as your project.

File → Load Gel…

38. The code in this file adds three command sliders to CCS. We can access these sliders from the GEL menu. Open each of the sliders using the following commands:

GEL → Application Control → Set_active_channel

GEL → Application Control → Set_channel_0_gain

GEL → Application Control → Set_channel_1_gain

39. Use the sliders to change the gain of the channels and set the active channel. Try turning one of the channels down, then playing with the other one and vice-versa. These sliders represent real volume controls that you might have in your own system.

Flashing RF3


Flashing RF3 Once you have an application up and running, most people want to see it work without using CCS to control it. In order to do this, we need to burn the application to the flash that is located on the DSK. This sounds like a pretty hefty task, but once again we have tools that make the job a lot easier. In order to speed things along, we have provided another project that contains a slightly modified RF3 application to make it easier to flash.

Switching Projects 40. Close the project we have been working with so far.

Project → Close

Note: If you get a message asking you if you want to save the project file, it shouldn't be necessary since we weren't supposed to make any changes to it.

41. Close any open windows, otherwise you may get an error when Flashburn opens.

Window → Close All

42. Close the GEL sliders by clicking on the little X in the upper right-hand corner of each one of them.

43. Open the new project app.pjt located in:

C:\c60001day\referenceframeworks\apps\rf3\dsk6416_boot – or –

C:\c60001day\referenceframeworks\apps\rf3\dsk6713_boot

Project → Open…

Create the Flash Image TI provides a separate tool, hex6x.exe, to create the image that can be burned into the flash.

44. You can run hex6x as a post-build step from within CCS. We have already added it for you. To see what we did:

Project → Build Options…

Hint

Flashing RF3


45. Click on the General tab in the window that pops up.

You should now see something like this:

We have added a command to call hex6x using CCS's Final build steps option. This option

tells CCS to call our command every time it does a full build. CCS also has Initial build steps option for those commands that need to run before CCS builds a project.

46. When you're through looking everything over, close the box by clicking on Cancel.

47. To have CCS build the project and call hex6x to generate the flash image, we need to do a Rebuild All.

Project → Rebuild All or click on

48. Wait for CCS to finish building the project and creating the hex image.

C:\ti\c6000\cgtools\bin\hex6x C:\c60001day\referenceframeworks\apps\rf3\dsk

Flashing RF3


Use Flashburn to Burn the Image TI simplifies burning the flash on the DSK with a utility called Flashburn.

49. Open Flashburn.

Tools → Flashburn

50. We have already created a configuration file for you that has all of the information that Flashburn needs to do its job. Open this file inside of Flashburn.

File → Open

The file is named rf3_dsk6416.cdd (or rf3_dsk6713.cdd) and it is located at:

C:\c60001day\referenceframeworks\apps\rf3\dsk6416_boot\Debug – or –

C:\c60001day\referenceframeworks\apps\rf3\dsk6713_boot\Debug

You should now see a window that looks like this:

Note: Flashburn should automatically connect to the target when you open the .cdd file. If it does not, you need to use CCS to run the CPU. When you do this, Flashburn should connect to the target and you should see this icon in Flashburn:

Again, the ‘dsk6416’ references would be changed to ‘dsk6713’ depending upon which ‘C6000 DSK you’re using.

Flashing RF3


51. Use Flashburn to erase the flash.

Program → Erase Flash or click on

52. Wait until the blue progress indicator bar goes away.

53. Now that the flash is erased, we can burn our hex file.

Program → Program Flash or click on

54. Wait until the blue progress indicator bar goes away.

55. Close Flashburn.

56. Now, let's see if it worked. Since the program is now in flash, we don't need CCS to load it anymore. Close CCS.

57. Disconnect the USB emulation cable from the DSK.

58. Hold your breath and press the white reset button on the DSK. If everything is working properly, you should now have music coming out of the DSK. If not, check to make sure that you have music playing.

59. Congratulations! You just flashed RF3 to the DSK.

Flashing POST You probably don't want to leave your DSK running RF3. Here are the steps to program the flash with the post routine.

60. Reconnect your USB emulation cable.

61. Open Code Composer Studio.

62. Open Flashburn.

Tools → Flashburn

63. Use Flashburn to open the post.cdd located at: c:\ti\examples\dsk6416\bsl\post\ – or – c:\ti\examples\dsk6713\bsl\post\

File → Open…

64. Make sure that Flashburn is connected. If not, you may need to run the processor.

65. Erase the flash.

Program → Erase Flash or click on

66. Wait on the blue progress bar to complete and go away.

Flashing RF3


67. Burn the flash.

Program → Program Flash or click on

68. Wait on the blue progress bar to complete and go away.

69. Close Flashburn.

70. Close CCS.

71. Push the white reset button on the DSK. The LEDs should flash to indicate the progress of the POST routine as it runs through its tests, then flash and remain on. You should also hear a tone if the speakers/headphones are still connected.

72. Your DSK is now good as new.

Lab/Demo Debrief


Lab/Demo Debrief eXpressDSP Demo Debrief

1. Reference Frameworks are a great way to get started with a design

IOM Drivers make it easy to port to new hardwareDSP/BIOS tools for scheduling and analysis make them easy to adapt and observeXDAIS provides an organized way to change/add algorithms

2. Flashburn gets the application into FLASH

Did you notice during the demo how few places in the RF3 application made direct reference to a specific hardware platform.

Did you notice during the demo how few places in the RF3 application made direct reference to a specific hardware platform.

eXpressDSP Summary eXpressDSP Summary

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C6000 One-Day Workshop - C6000 Optimization 4 - 1

C6000 Optimization

Introduction The importance of the C language has grown significantly over the past few years. TI has responded by creating a compiler that produces extremely efficient processor code, which is so speed efficient you may not need to program in assembly.

After getting your C code running, you may want to optimize it to get the best performance possible. In this chapter we discuss three major optimizations you can take, and then point out where you can go to discover more techniques.

Outline Outline

Build OptionsUse Optimized LibrariesEnable CacheWhere To Go for More Information

Optimization Build Options

4 - 2 C6000 One-Day Workshop - C6000 Optimization

Chapter Topics C6000 Optimization .................................................................................................................................. 4-1

Optimization Build Options .................................................................................................................... 4-3 Use Optimized Libraries ......................................................................................................................... 4-7 C6000 Double-Level Cache ...................................................................................................................4-10

Why Cache?.......................................................................................................................................4-10 Details of C67x & C64x Internal Memory ........................................................................................4-12 Configuring External Memory as Cacheable (MAR)........................................................................4-16

Where To Go For More Information .....................................................................................................4-18 LAB 4: Using C......................................................................................................................................4-19

Optimized C.......................................................................................................................................4-27 Using ASM Libraries.........................................................................................................................4-30 Lab 4 Results .....................................................................................................................................4-32

Lab 4a: Memory and Cache...................................................................................................................4-33 Everything Off-chip...........................................................................................................................4-33 Use Some Cache (L1)........................................................................................................................4-38 Use All the Cache..............................................................................................................................4-41 Cache Re-use .....................................................................................................................................4-44 Lab 4a Results ...................................................................................................................................4-45

Optional Topics......................................................................................................................................4-46 Cache Data Coherency ......................................................................................................................4-46 Advanced Optimizations (Brief List) ................................................................................................4-48



Optimization Build Options Compiler Build Options

Nearly one-hundred compiler options available to tune your code's performance, size, etc.To our earlier table, we added optimize options

Options Description

-mv6700 Generate ‘C67x code (‘C62x is default)-mv6400 Generate 'C64x code-fr <dir> Directory for object/output files

-q Quiet mode (display less info while compiling)-g Enables src-level symbolic debugging-s Interlist C statements into assembly listing

-o3 Invoke optimizer (-o0, -o1, -o2/-o, -o3)-gp Enable function-level profiling-k Keep asm files, but don't interlist

debug

optimize

Debug and Optimize options conflict with each other, therefore they should be not be used together

As you probably learned in college programming courses, you should probably follow a two step process when creating code:

• Write your code and debug its logical correctness (without optimization). • Next, optimize your code and verify it still performs as expected.

As demonstrated above, certain options are ideal for debugging, but others work best to create highly optimized code. When you create a new project, CCS creates two sets of build options – called Configurations: one called Debug, the other Release (you might think of as Optimize). Configurations will be explored next.

Note: Like any compiler or toolset, learning the various options requires a bit of experimentation, but it pays off in the tremendous performance gains that can be achieved by the compiler. To this end, this workshop will explore these options further in an upcoming chapter.



Build Option Configurations To help make it easy to use many compiler options, TI provides two recommended sets of options (configurations) in each new project you create:

Debug -g -q -fr"c:\modem\Debug" -d"_DEBUG" -mv6700

Release -q -o3 -fr"c:\modem\Release" -mv6700

The main difference is that the Release (optimized) configuration invokes the optimizer with –o3.

Two Default Configurations

For new projects, CCS automatically creates two build configurations:

Debug (unoptimized)Release (optimized)

Use the drop-down to quickly select build config.

-g -q -fr"c:\modem\Debug" -d"_DEBUG" -mv6700

-q -o3 -fr"c:\modem\Release" -mv6700

*Note: We recommend you add the two options –gp –k to make ‘Release’ more useful.

We recommend you add the –gp and –k options to the Release configuration as this makes it easier to evaluate the optimized performance. In the upcoming lab exercise, you will get a chance to do this.

Note: The examples shown hear are for a C67x DSP, hence the –mv6700 option.



Use the Project→Configurations… menu to create or delete a Build Configuration.

Two Default Configurations

For new projects, CCS automatically creates two build configurations:

Debug (unoptimized)Release (optimized)

Use the drop-down to quickly select build config.

Add/Remove build config'swith Project Configurationsdialog (on project menus)

Edit a configuration:1. Set it active2. Modify build options

(shown next)3. Save project

-g -q -fr"c:\modem\Debug" -d"_DEBUG" -mv6700

-q -o3 -fr"c:\modem\Release" -mv6700

To edit a configuration, first make it active (via Project Configurations dialog or toolbar drop-down).



We are often asked, “Why Use –fr?”

When changing configurations, using -fr prevents the object (and .out) files from being overwritten. While not required, it allows you to preserve all variations of your projects output.

Why use -fr?When changing configurations, the -fr option prevents files from being overwrittenWhile not required, it allows you to preserve all variations of your project’s output files

c60001dayc60001daylabs

lab3Debug

lab3.outlab3.obj

Debug

lab3.outlab3.obj

Use Optimized Libraries


Use Optimized Libraries TI provides several libraries of optimized code to help build a DSP system. The following slides provide some information on some of these libraries and how to use them.

DSPLIBOptimized DSP Function Library for C programmers using C62x/C67x and C64x devicesThese routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines, you can achieve execution speeds considerably faster than equivalent code written in standard ANSI C language. And these ready-to-use functions can significantly shorten your development time.The DSP library features:

C-callableHand-coded assembly-optimizedTested against C model and existing run-time-support functions

DSP_q15toflDSP_iirDSP_minerrorDSP_fir_symDSP_fltoq15DSP_fir_r8DSP_blk_moveDSP_fir_r4DSP_blk_eswap64DSP_fir_genDSP_blk_eswap32DSP_fir_cplxDSP_blk_eswap16Filters & convolutionDSP_bexpDSP_ifft32x32

MiscellaneousDSP_ifft16x32DSP_mat_transDSP_fft32x32sDSP_mat_mulDSP_fft32x32

MatrixDSP_fft16x32DSP_w_vecDSP_fft16x16tDSP_vecsumsqDSP_fft16x16rDSP_recip16DSP_fftDSP_neg32DSP_r4fftDSP_mul32DSP_radix 2DSP_minvalDSP_bitrev_cplxDSP_maxidxFFTDSP_maxvalDSP_autocorDSP_dotprodCorrelationDSP_dotp_sqrDSP_firlms2

MathAdaptive filtering

IMGLIBOptimized Image Function Libraryfor C programmers using C62x/C67x and C64x devicesThe Image library features:

C-callableC and linear assembly src codeTested against C model

IMG_thr_le2thr IMG_thr_le2min IMG_thr_gt2thr IMG_thr_gt2max IMG_sobelIMG_perimeterIMG_histogramIMG_erode_binIMG_dilate_binIMG_boundary

Image AnalysisIMG_ycbcr422_rgb565 IMG_yc_demux_le16 IMG_yc_demux_be16 IMG_pix_satIMG_pix_expandIMG_median_3x3 IMG_errdif_binIMG_corr_genIMG_corr_3x3IMG_conv_3x3

Picture Filtering / Format Conversions

IMG_wave_vertIMG_wave_horzIMG_sad_16x16 IMG_sad_8x8 IMG_quantizeIMG_mpeg2_vld_inter IMG_mpeg2_vld_intra IMG_mad_16x16 IMG_mad_8x8 IMG_idct_8x8_12q4 IMG_idct_8x8 IMG_fdct_8x8

Compression / Decompression



FastRTS (C67x)Optimized floating-point math function library for C programmers using TMS320C67x devicesIncludes all floating-point math routines currently in existing C6000 run-time-support libraries

sinsinfrsqrtrsqrtfreciprecipfpowpowflog10log10flog2log2floglogfexp10exp10fexp2exp2fexpexpfcoscosfatan2atan2fatanatanf

Double PrecisionSingle PrecisionThe FastRTS library features:C-callableHand-coded assembly-optimizedTested against C model and existing run-time-support functions

FastRTS must be installed per directions in its Users Guide (SPRU100a.PDF)

FastRTS (C62x/C64x)Optimized floating-point math function library for C programmers enhances floating-point performance on C62x and C64x fixed-point devices

The FastRTS library features:C-callableHand-coded assembly-optimizedTested against C model and existing run-time-support functions

FastRTS must be installed per directions in its Users Guide (SPRU653.PDF)

_subd_subfreciprecipf_mpyd_mpyf_fltuld_fltulf_fltud_fltuf_fltlid_fltlif_fltid_fltif_fixdul_fixful_fixdu_fixfu_fixdli_fixfli_fixdi_fixfi

_cvtfd_divd_divf_cvtdf_addd_addf

OthersDouble Precision

Single Precision



Now that you know about the libraries, here's where to find them and some information on how they are organized. Each library also has documentation that goes along with it.

Location of Libraries(in CCS v2.2)

DSP and IMG Libraries provided as source archive, and Little Endian C6000 obj library

Folder Structure:lib - library files (.lib) and source code (.src)include - contains the library header filessupport - miscellaneous supporting codebin - supporting Windows executables

CCS Doc’s folder contains: SPRU565A.pdf - DSP API User GuideSPRU023A.pdf - Imaging API User GuideSPRU100A.pdf – FastRTS Math API UG

Application Notes: SPRA885.pdf - DSPLIB App noteSPRA886.pdf- IMGLIB App note

C6000 Double-Level Cache



Why Cache? In order to understand why the C6000 family of DSPs uses cache, let's consider a common problem. Take, for example, the last time you went to a crowded event like the symphony, a sporting event, or the ballet, any kind of event where a lot of people want to get to one place at the same time. How do you handle parking? You can only have so many parking spots close to the event. Since there are only so many of them, they demand a high price. They offer close, fast access to the event, but they are expensive and limited.

Your other option is the parking garage. It has plenty of spaces and it's not very expensive, but it is a ten minute walk and you are all dressed up and running late. It's probably even raining. Don't you wish you had another choice for parking?

Parking Dilemma

ConcertHall

Distant Parking-Ramp

10 minute walk

Close Parking0 minute walk10 spaces$100/space

10 minute walk1000 spaces$5/space

Parking Choices:0 minute walk @ $100 for close-in parking

10 minute walk @ $5 for distant parkingor …

Valet parking: 0 minute walk @ only $6.00

You do! A valet service gives the same access as the close parking for just a little more cost than the parking garage. So, you arrive on time (and dry) and you still have money left over to buy some goodies.



Cache is the valet service of DSPs. Memory that is close to the processor and fast can only be so big. You can attach plenty of external memory, but it is slower. Cache helps solve this problem by keeping what you need close to the processor. It makes the close parking spaces look like the big parking garage around the corner.

Why Cache?

CPU

BulkMemoryCache

MemorySlowerLargerCheaper

Memory Choices:Small, fast memoryLarge, slow memory

or … Use Cache:Combines advantages of bothLike valet, data movement is automatic

FastSmallWorks like Big, Fast Memory

One of the often overlooked advantages of cache is that it is automatic. Data that is requested by the CPU is moved automatically from slower memories to faster memories where it can be accessed quickly.



Details of C67x & C64x Internal Memory

Overall Layout and Levels of Memory The memory architecture of a C6x1x device with its two-level cache is often referred to as memory hierarchy. The highest level in the hierarchy, level 1 or L1, is the fastest, smallest memory. Requests from the CPU are sent to this level first. The second level is the larger on-chip memory, L2. Requests that can't be satisfied by the first two levels are sent off-chip, which is kinda like level 3.

SDRAM(16MB)

Daughter-CardDaughter-CardCE2

CE3

CE0

Flash(512KB)

CE1

Roomfor

Expansion

Level 3

CPU

ProgramCache

DataCache

Levels of Memory

EMIFL2

InternalSRAM

Level 2

We often refer to a system’s memory in hierarchical levelsHigher levels (L1) are closer to the CPU

L1

It's important to understand these hierarchical levels in order to comprehend how requests flow from the CPU to the caches and memories.

The daughtercard interface on the DSK allows you to add more memory, as well as other devices, to your board. Check the dspvillage.com web site and search for daughtercard to find out what is available for purchase.



C6713 Internal Memory Here is some specific information about the C6713 internal memory architecture that is on some of the DSKs you may be using. As you can see, you get information from the L1 memories with no delay. If you have to go to L2 to get the information, there is some delay, but you can get additional information for no extra cost. For example, if you have to go to L2 to get a fetch packet (a group of 8 instructions), it will take 5 cycles but you will also get the next fetch packet.

C6713 Internal MemoryLevel 1 Caches

Single-cycle accessAlways enabledL2 accessed on miss

Level 2 MemoryUnified: Prog or DataL2 → L1D delivers32-bytes in 4 cyclesL2 → L1P delivers 16 instr’s in 5 cyclesConfigure L2 as cache or addressable RAM

CPU

L1Program

(4KB)

L1Data(4KB)

L2Program& Data

(256K Bytes)8/16/32/64

(C6711/12: L2 memory is 64K bytes)

Here are some more details about the C6713 internal memories.

C6713 Internal Memory - DetailsLevel 1 Program

• Always cache• 1 way cache

(Direct-Mapped)• Zero wait-state• Line size: 512 bits

(or 16 instr)Level 1 Data

• Always cache• 2 way cache• Zero wait-state• Line size: 256 bits

Level 2• Unified (prog or data)• RAM or cache• 1-4 way cache• 32 data bytes in 4 cycles• 16 instr. in 5 cycles• Line Size: 1024 bits

(or 128 bytes)

CPU

L1Program

(4KB)

L1Data(4KB)

L2

UnifiedProgram& Data

(256KB)

256

8/16/32/64

128

256

(C6711/12: L2 memory is 64K bytes)



C67x L2 Memory A nice feature of the C6000 L2 memories is that they can be configured as internal SRAM or cache ways. This allows designers to customize the memory architecture to fit their needs.

C67x L2 Memory Configuration

Four 16KB blocks – Configure each as cache or addressable RAMEach additional cache block provides another cache wayL2 is unified memory – can hold program or data

C6713 Still has 4 configurable 16KB RAM/cache blocks, the remaining 192KB is always RAM

Hardwaredefault

or or

RAM 3

RAM 0

RAM 1

RAM 2oror

RAM 1

RAM 0

RAM 2

Way 1

RAM 1

RAM 0

Way 2

Way 1

Way 3

RAM 0

Way 2

Way 1

Way 3

Way 4

Way 2

Way 1

The Configuration Tool makes setting up the cache the way you want as easy as choosing an option in a drop-down box.

Configuring C6713 L2 Cache



C64x Internal Memory The C64x internal memory architecture is similar to that of the C6713, but each level is larger.

C64x Internal Memory

CPU

L1Program

(16KB)

L1Data

(16KB)

L2Program& Data

(1M Bytes)8/16/32/64

L1 Program CacheDirect Mapped (1 way)Single cycle accessSize = 16K BytesLinesize = 8 instr.

L1 Data Cache2-Way CacheSingle cycle accessSize = 16K BytesLinesize = 64 bytes

Level 2 MemoryC6414/15/16 = 1M ByteC6411/DM642 = 256K Byte

The C64x L2 memory is also configurable. It always has 4 cache ways, but you can change the size of the ways from 0K bytes (all SRAM) to larger sizes up to 64K bytes in 4 ways (256K cache, 728K SRAM).

C64x L2 MemoryConfiguration

When cache is enabled, it’s always 4-WayThis differs from C671x

LinesizeLinesize= 128 bytesSame linesize as C671x

PerformanceL2 → L1P

1-8 CyclesL2 → L1D

L2 SRAM hit: 6 cyclesL2 Cache hit: 8 cyclesPipelined: 2 cycles

L2 Ways are Configurable in Size

L2 Ways are Configurable in Size

0 32K 64K 128K 256K



Configuring External Memory as Cacheable (MAR) What do you do if you have an address in memory that you don't want to be cached? Why would you want to do this? Would you want to cache the value stored in a FIFO, a register in a FPGA, or a parallel A/D converter. If you did, then the value might only be read once, and this is probably not what you want.

The Memory Attribute Registers allow you to control which addresses in the memory map are cached and which are not cached. So, if you have a FIFO in your system, you can place it in an address region that uses a separate MAR bit and turn off that MAR bit. Then, you could turn on the MAR bits for the other memories in your system that you do want to cache.

Memory Attribute Regs (MAR)

CE0

CE2

CE3

0 = Not cached1 = Cached

MAR4 0

MAR5 1

MAR6 1

MAR7 1

Reserved

Use MAR registers to enable/disable caching of external rangesUseful when external data is modified outside the scope of the CPUYou can specify MAR values in Config Tool

C671x:16 MAR’s4 per CE spaceEach handles 16MB

C64x:Each handles 16MB256 MAR’s16 per CE space(on current C64x, some are rsvd)

The processor reset value for the MAR bits is zero. This means that when the processor wakes up, all of the external memory is uncacheable. What do you think this will do to the performance of your system if you are using cache (and you should)? Let's just say you probably won't be pleased. So, one of the first things that you need to do is turn on the MAR bits for the memory regions that you need to cache.



The Configuration Tool makes this easy. You can use a mask in the Configuration Tool to setup up the MAR bits that you want to enable and it will be done for you.

Setting MARs in CDB

MAR bit values:0 = Not cached1 = Cached

MAR bit values:0 = Not cached1 = Cached

MAR15

…MAR3MAR2MAR1MAR0

00000000

…00000000000000000000000000000001

If your code is running a lot slower than you thought it would, you might want to check the MAR bit settings. These bits are set to zero at reset and the default configuration files usually leave them that way. So, if you want cache enabled in your system, you need to turn these bits on.

Where To Go For More Information


Where To Go For More Information We just can't cover everything that you might want to know about these important subjects in a 1-day workshop. Here is a good list of other places that you can go for more information.

Optimizing C PerformanceAttend the 4-day C6000 Optimization Workshophttp://www.ti.com/sc/training

Review the Compiler TutorialSee tutorials in CCS online help, orhttp://www.ti.com/sc/c6000compiler

Read:C6000 Programmer’s Guide (SPRU198)

Cache Memory User’s Guide (SPRU656)

C6000 Optimizing C Compiler Users Guide (SPRU187)

Look through the many application notes at:http://www.dspvillage.com

• All the options are detailed in TMS320C6000 Optimizing C Compiler User's Guide. It’s highly

recommended that you take time to read through the entire manual. OK, we know that reference manuals can be boring (and this one isn’t any different) but the information you gain will be worth it.

• Also recommended is the TMS320C6000 Programmers Guide. It contains code optimization details for C, Linear Assembly, and standard assembly programming.

• The TMS320C6000 Compiler Tutorial is an invaluable reference. You can find this excellent resource at the TI website: http://www.ti.com/sc/c6000compiler, or built into Code Composer Studio tutorials.

• The Cache Memory User's Guide is an excellent resource for everyone that needs to know more about cache and how to use it in a DSP system. It includes examples on how to make your code go faster in a cache based architecture.

• Finally, there are several great application notes out on our web site. These notes go into detail about specific subjects to help solve common problems.

LAB 4: Using C


LAB 4: Using C Lab 4

Build project with Image Correlation functionCompare performance between:

1. Without Optimization2. With Compiler’s Optimizer3. Using IMGLIB Function4. With and Without Cache

This lab has several goals: • Build a project using C source files. • Benchmark/profile C code. • Contrast results for both sets suggested compiler options:

− Debug build configuration − Release (Optimized) build configuration

• Call optimized Assembly routine from a library • Examine the effects of cache on this optimized application

LAB 4: Using C


Image Correlation We're going to use an image correlation algorithm in the lab. Here's some more information on this algorithm for those of us that haven't had much exposure to it.

Lab 4 - 3x3 Correlation

T

128

64

3x3 Maskof 8-bit pixels

(8-bit pixels)

“Search” Image for Mask

Search image for pixel location of “mask”Step through entire image processing each 3x3 pixel blockBasically, image correlation involves summing the values of 3x3 matrix multiply between mask and each 3x3 block in the image. The result of each summation is written to an array. The best match is the largest value in the array.

Here's an example of how image correlation is used in the lab.


T

128

64No Match

LAB 4: Using C


T


128

64PartialCorrelation

T


128

64BetterFit

T


128

64Match!

LAB 4: Using C


Create the Lab4 project 1. Create a new project called LAB4.PJT in the C:\c60001day\labs\lab4 subdirectory.

Project → New…

You’ll encounter the Project Creation dialog. Fill in the Project Name and Location as shown:

You can also use the … button to specify the correct path.

2. Verify the newly created project is open in CCS by clicking on the + sign next to the Projects folder in the Project View window.

You may want to expand the lab4.pjt icon to observe the project contents. (Of course, it

should be empty at this time.)

67 If using the C6713 DSK, the target should read, “TMS320C67XX”

LAB 4: Using C


Create a CDB file 3. Create a new CDB file (File → New → DSP/BIOS Configuration…).

4. Select the appropriate CDB template for your system.

Select the dsk6416.cdb or dsk6713.cdb template 5. While there are many objects displayed in the CDB file, we don’t need to change any of them at

this time. The defaults will work fine.

6. Save your CDB file as LAB4.CDB in C:\c60001day\labs\lab4 directory.

File → Save As…

7. Add the following files from C:\c60001day\labs\lab4 to your project:

LAB4.C LAB4.CDB LAB4cfg.CMD

When these files have been added, the project should look like:

LAB 4: Using C


Modify the “Debug” Configuration 8. For easy debugging, use the Debug configuration; this should be the default.

Verify that Debug is in the Project Configurations drop-down box

9. Before building, though, we need to add a symbol definition to the Debug configuration.

In this lab we plan to use the hardware timer to benchmark our performance. (This is just one of many ways to do this within CCS). We will use the Chip Support Library (CSL) discussed back in Chapter 2 to setup and use the timer. CSL requires that the chip type is defined in your project so the proper code can be extracted from the library. Use the following three steps to modify your project configuration:

Project → Build Options

Select the Preprocessor category on the left-hand side.

Add CHIP_6416 to the Define Symbols text box. It should now look like this:

Basically, the –d“ ” option is like adding a project-wide: #define CHIP_6416 1

67 If using the C6713 DSK, the symbol should be:

CHIP_6713

LAB 4: Using C


10. Turn on the large memory model.

Add -ml3 (small –ML3) to the build options by typing it in the box at the top of the build options.

You can always add options by simply typing them into the text box, if you already know them.

11. Click OK to apply the changes that you have made and close the Build Options dialog.

Building the program (.OUT) 12. Build the program.

Project → Build

13. Load the program if this did not happen automatically.

Run the Code Now that the program has been written, compiled, and loaded, it’s time to determine its logical correctness.

14. Based on the CCS options we set in Lab 1, after loading the program CCS should have automatically run your code until it reached main.

If this did not happen, go ahead on perform it using Debug → Go Main.

15. Feel free to take a moment to inspect the code. You'll notice that we are using the CSL functions that we discussed earlier in this workshop to calculate how long it takes to run our image correlation example. We are using printf()'s to output these results so that we know how our code is performing.

16. Run the code to see the output of the printf()'s.

Debug → Run or click on

LAB 4: Using C


17. The output prints to the Stdout window in Code Composer Studio. Here is what the output should look like. Note, though that the cycle counts shown are for the C6416 DSK. If you are using the C6713 DSK, your cycle numbers will be different.

• Number of data: number of pixels that were calculated. • Number of cycles: number of CPU cycles it took to do the correlation. • The next line tells us where the template image is at in the original image. • The highest correlation found should match the template location if everything worked

correctly.

18. Write down the number of cycles needed for this unoptimized C code in the table on page 32.

19. If CCS is still running, please halt it.

20. If you'd like to see the image that you just searched, Code Composer can show it to you with its graphing capability. In order to save you time, we have saved the graph in a workpace. If you'd like to see the image, just load the workspace:

File → Workspace → Load Workspace…

Choose the appropriate Workspace in C:\c60001day\labs\lab4.

Use the pink data cursor to make sure that the template match is where the correlation algorithm said it was.

Note: You can right-click on the image and choose properties if you'd like to see how this was set up. We simply used View → Graph → Image and filled in the values that you see in the properties box.

LAB 4: Using C


Optimized C Now that we've seen how long it takes to execute the unoptimized C, let's take a look at how fast this code runs when the optimizer is turned on.

Change the Release Configuration Code Composer Studio ships with two default configurations: Debug and Release. We've seen what Debug does, so let's use the Release configuration to turn on the C optimizer and see how fast it can make this piece of code.

21. Change the build configuration to Release by selecting it in the drop-down as shown:

22. We need to make a couple of simple changes to the configuration before we can use it. You'll probably recognize these changes since they are the same one that we made earlier. Open the project build options.

Project → Build Options…

LAB 4: Using C


23. Add the following two options to the build options for the release configuration just like you did earlier. Either use the text box at the top or the GUI at the bottom to add these options:

-d"CHIP_6416" and –ml3 (for the C6416 DSK) -d"CHIP_6713" and –ml3 (for the C6713 DSK)

Your options should now look like this:

Note: The biggest difference between Release and Debug is that Release turns on the Optimizing C Compiler with the –o3 option and turns off symbolic debugging by removing the –g option.

6416

6713

LAB 4: Using C


Build and Run the code 24. Build your code.

Project → Build 25. If your program doesn't load automatically, then load the program.

File → Load Program…

Note: You will probably not see main() come up like it has in the past. Since the source level debug option (-g) has been turned off, CCS cannot open source files like the one that contains main().

26. Run the program.

If everything is working correctly, you should see a print out similar to the one that you saw in the first part of this lab. If you're having trouble, ask you facilitator for help.

27. Record the new results for the optimized C code in the table on page 32.

Were these results better or worse than you expected them to be?

_________________________________________________________________________

LAB 4: Using C


Using ASM Libraries The jump in performance that the correlation routine gets by turning on the C optimizer is pretty impressive and may be all the performance that you need to meet your real-time deadlines. Sometimes all people need to get the necessary performance from the C6000 is to turn-on the optimizer – and we've just seen how easy this is to do.

If you're happy with the performance that you get from the C compiler then you can stop there. However, if you have a really time critical routine that you just need to squeeze every cycle out of, you may want to an assembly language (ASM) routine. To this end, we’ll learn how to use one of the many optimized routines that TI provides. The Image Library (or IMGLIB), provided by TI, has a correlation routine optimized in ASM that we’ll compare to our C code.

Referencing the library function 28. The first step to calling the code from IMGLIB is to change the function that we are calling.

− The function that we want to call in the library is called: IMG_corr_3x3. − The C function that we’re replacing is called: corr_3x3.

So, all you need to do is find all places where corr_3x3 is used in the code and change it to IMG_corr_3x3.

You should only need to do two replacements:

29. Now that we have replaced the C function calls with IMGLIB function calls, let's go ahead and comment out the actual corr_3x3 C function. This way, if we've missed any changing any references to it, we should get a compiler error.

LAB 4: Using C


30. The next thing we need to do in order to call the function in the library is to include a header file. Find the comments at the beginning of lab4.c that talk about including the header files for the Image Library and add the following line of code:

#include "img_corr_3x3.h" 31. We also need to let CCS know where it can find the above header file. We can do this by

adding the following to our build options under Project → Build Options….

-i"C:\ti\c6400\imglib\include" (for the C6416 DSK)

-i"C:\ti\c6200\imglib\include" (for the C6713 DSK)

32. The last step to calling the ASM routine is to actually add the library to your project.

Project → Add Files to Project… 33. In the following dialog box, navigate to the correct folder and the appropriate library file

to your project.

C:\ti\c6400\imglib\lib\img64x.lib" (for the C6416 DSK)

C:\ti\c6200\imglib\lib\img62x.lib" (for the C6713 DSK) Yes, it may appear odd that we are using the C62x library for the C6713, but since C67x

devices can run C62x object code, this works out fine.

Hint: You may have to changes the "Files of type" drop-down box at the bottom of the Add Files dialog to see the library files.

Rebuild and Run the Code 34. Now that you've made all of the changes necessary to use the library code, go ahead and

rebuild everything.

Project → Build or click on . 35. If your program doesn't automatically load, go ahead and load it.

File → Load Program… 36. When you're ready, run the code to see how fast it executes (and to make sure that it is

accurate).

37. Record your results in the table on page 32.

LAB 4: Using C


Lab 4 Results Here's a summary of the results that we've obtained from lab 4. These are the results with all code and data located in the internal memory of the C6000. In Lab 4a, we'll explore the effects that memory organization and cache can have on this system.

Lab Step Build Configuration Cycles

Lab 4 Step 18 Debug

Lab 4 Step 27

Release

Lab 4 Step 37

IMGLIB

If you have time left, please move on to lab 4a.

Lab 4a: Memory and Cache


Lab 4a: Memory and Cache In this lab, we'll take up where we left off with the IMGLIB example. We're going to explore how to move stuff around in memory and enable the cache to see how these things affect performance.

Everything Off-chip Let's start off by moving everything (code and data) from on-chip memory where it is now, to off-chip memory. We're also going to leave the cache turned off for now to see what the absolute worst case performance of this code might be.

1. We're going to use the Configuration Tool to change the memory configuration. So, open the lab4.cdb file.

2. The .cdb file is broken down into different categories to make it easy to set up. We need to use the Memory Manager which is located in the System folder.

3. You can see the three different kinds of memory that we have available to us on the DSK by clicking on the plus sign next to the Memory Manager. You should see ISRAM, FLASH, and SDRAM for the 6416 DSK, and CACHE_L2, IRAM, and SDRAM for the 6713 DSK.



4. We need to change the properties of the SDRAM so that it can store code and data. Currently, it is only setup to store data. Open the SDRAM properties by right-clicking on it and choosing properties.

5. You should see the box below. Change the "space" option from data only to code/data. When complete, the dialog should look like one of the following:

When you're done, click OK.

6416 only



6. Now we can move everything from ISRAM (or IRAM) to SDRAM. Open the properties of the Memory Manager itself by right-clicking on it and selecting properties.

7. You should now see a window with five tabs. We don't need to do anything with the General tab, so go ahead and select the next tab, BIOS Data.

We want to move everything on this tab from ISRAM (or IRAM)to SDRAM by clicking on each one of the drop-down boxes. When you get finished with the BIOS Data tab, the dialog should look like this:



8. Click on the BIOS Code tab and make the same changes. When you are done with this tab, the window should look like this:

9. We also need to make the same change in the Compiler Sections tab. Select this tab and move everything to SDRAM. Here's what you'll be left with:



10. When you create a DSKC6713 CDB file, the cache is enabled automatically (whereas it is disabled by default on the DSKC6416 CDB file.) Therefore, to get an accurate “no cache” comparison, we need to turn off the cache by making all external memory Non-Cacheable. (C6416 users can ignore these two steps). • Open the Config Tool makes this easy.

• Find and open the Global Settings under the System by right-clicking on it and selecting

properties.

11. Modify the C6713 MAR bit settings to make external memory non-cacheable: • Select the 621x/671x tab. • Make the dialog box look like this:

Rebuild and Run the Code 12. Now that everything has been moved off-chip, we can rebuild the code and run it to see what

the effect was. Rebuild the code first.

13. If your program doesn't automatically load, go ahead and load it.

14. When you're ready, run the code.

15. Record the results of running everything from off-chip memory in the table on page 45.

6713 ONLY



Use Some Cache (L1) When we moved everything off-chip our code slowed down considerably. So, how do we speed it back up? Well, we could just move it back on-chip, but what if we don't have space for everything? That's where cache comes in. It helps keep the stuff that the CPU needs close at hand, just like a valet brings your car close to you.

16. In order to use the L1 caches to help us speed our code up, we need to tell the C6000 that the addresses that our code and data are using are cacheable. We do this by enabling the Memory Attribute Register (MAR) bits. (We discussed the MAR bits on page 4-16.)

17. Again, the Config Tool makes this easy. Find the Global Settings under the System.

18. Open the Global Settings properties by right-clicking on it and selecting properties.



19. Modify the C6416 MAR bit settings: • Select the 641x tab. • Check the check box that says "641x – Configure L2 Memory Settings".

• We need to turn on the MAR bits for the EMIFA, CE0 memory space. Do this by changing the appropriate text box from 0x0000 to 0xffff. It should now look like this:

6416 ONLY



20. Modify the C6713 MAR bit settings: • Select the 621x/671x tab. • Check the check box that says "621x/671x – Configure L2 Memory Settings". • Let’s turn on all the MAR bits for the EMIF. Do this by changing the appropriate text box

from 0x0000 to 0xffff. It should now look like this:

21. When you've made the changes, click OK.

Rebuild and Run the Code 22. Now that the L1 caches have been enabled, we can rebuild the code and run it to see what the

effect was. Rebuild the code.


File → Load Program… 24. When you're ready, run the code.

25. Record the results of running everything with L1 cache in the table on page 45.

6713 ONLY



Use All the Cache So far, we've only turned on the L1 caches. If we want the full benefit of the cache, we need to enable both L1 and L2. 26. So, how do we turn on the L2 cache? You guessed it, we use the configuration tool.

27. Open the properties of the Global Settings just like we did before.

28. For the C6416 DSK only: • Select the 641x tab. • Change the "641x L2 Mode – CCFG (L2MODE)" drop-down box

− From "4-way cache (0K)" − To "4-way cache (256K)". It should look something like this:

• Click OK when you are done.

Note: This setting is a little confusing. When most people see "4-way cache", they might actually think that the cache is on. Well, it is true, but the one that has cache ways that are 0K in length don't do much cacheing!

6416 ONLY



29. Save the changes that you have made to the .cdb file by making sure that it is selected and choosing File → Save.

30. You should see the following box appear:

The problem is that we took some of the internal memory away when we turned on the L2 cache. The CACHE_L2 memory segment was added to account for this change. We need to remove 256KB from the ISRAM section to allow for the cache. Click OK in the box so we can go fix the problem.

31. Right-click on the ISRAM memory segment and choose properties.

32. Change the "len:" property from 0x00100000 to 0x0000c000. This simply removes the 256KB that is being used for L2 cache from the memory, since it is now cache.

33. For the C6713 DSK: • Select the 621x/671x tab. • Change the "641x L2 Mode – CCFG (L2MODE)" drop-down box from "4-way cache

(0K)" to "4-way cache (256K)". It should look something like this:

• Click OK when you are done.

34. Save the changes that you have made to the .cdb file by making sure that it is selected and choosing File → Save.

6713 ONLY

Still 6416 ONLY



Rebuild and Run the Code 35. Now that the L1 and L2 caches have been enabled, we can rebuild the code and run it to see

what the effect was. Rebuild the code.



38. Record the results of running everything with L1 and L2 cache in the table on page 45.



Cache Re-use Cache memories perform best when the information that they are cacheing is used many times. So far, we've only looked at cache in the worst possible scenario, when the data is only used once. What if we're going to use the code/data again and again, then the cache can really start to help us. To see this, let's call the image correlation twice on the same image and see if the performance improves any on the second call.

39. Open lab4.c.

40. Scroll down to the code where we actually time the image correlation algorithm with the timer. The code should look something like this:

41. Copy the line of code that calls IMG_corr_3x3() and paste it above the line that starts with start (isn't that redundant?). This way, the algorithm get's called and everything gets brought into cache, then we call it again to see what the real benefit of cache would be.

Rebuild and Run the Code 42. Now that the L1 and L2 caches have been enabled and stuff is sitting in cache, we can rebuild

the code and run it to see what the effect was. Rebuild the code.



45. Record the results of running everything with L1 and L2 cache in the table on page 45.

Copy IMG_corr_3x3

line to here



Lab 4a Results Here's a summary of the results that we've obtained from lab 4a.

Lab Step Memory Configuration Cycles

Lab 4a Step 15 All Off-chip

Lab 4a Step 25

L1 Cache On

Lab 4a Step 38

L1 and L2 Cache On

Lab 4a Step 45

Everything Already in Cache

End of Lab4a Exercise Please inform your facilitator that you have finished. Thank You.

Optional Topics


Optional Topics

Cache Data Coherency

CPU Reading External Memory

CPU

L2External

L1D EDMA

Buffer (located in external memory) written to by the EDMA

RcvBufRcvBuf:

CPU Reading External Memory

CPU

L2External

L1DRcvBufRcvBuf RcvBuf

EDMARcvBuf:

CPU reads the buffer for processingCPU read causes a cache miss in L1D and L2 (Assuming L2 cache is on)RcvBuf is added to both caches

Space is allocated in each cacheRcvBuf data is copied to both caches

Optional Topics


“Read” Data Coherency

CPU

L2External

L1DRcvBuf RcvBuf

EDMARcvBuf

RcvBuf:

EDMA writes new data to bufferWhen the CPU reads RcvBuf again, what will happen?CPU gets old data!

Solutions

ExternalEDMA

RcvBufRcvBuf:

CPU

L2L1DRcvBuf RcvBufInvalidate (remove)

RcvBuf from cache before receiving new dataCSL provides cache invalidate routines

2

1“Read” Data Coherency - Solutions

CPU

L2External

L1DRcvBuf RcvBuf

EDMARcvBuf:Locate buffer in L2

No coherency issues between L1↔L2

CPU

L2L1D

Whenever L1 or L2 are read, the other is checked to make sure there isn’t newer data

Whenever L1 or L2 are read, the other is checked to make sure there isn’t newer data

Optional Topics


Advanced Optimizations (Brief List)

Advanced Optimizations(Other than the techniques discussed here)

Let EDMA move data (or code) on-chip before neededData is on-chip when it’s neededEDMA gets better transfer performance than CPU due to it’s ability to perform burst transfersMinimize back-to-back Reads and Writes to/from off-chip memory

Compiler Intrinsic functionsProgram Level Optimization: -pm –op2 -o3Various Compiler Pragma’s:

#pragma UNROLL(# of times to unroll);#pragma MUST_ITERATE(min, max, %);#pragma DATA_ALIGN(variable, 2n alignment);#pragma DATA_MEM_BANK(var, 0 or 2 or 4 or 6);

Layout system and tune code for best cache usage

C6416/C6713 DSK One-Day Workshop - Wrap Up 5 - 1

Wrap Up

Introduction What do you need to put around your DSP? Most microprocessors usually require some support chips – power management, clock drivers, bus interface, and so on. DSP systems usually contain some additional devices – such as sensors, data acquisition, and such – because they receive, modify, and output real-world signals.

Finally, pull out your DSP Selection Guide and C6000 Product Update sheet to follow along with the last part of the workshop summarizing the C6000 devices, tools, and support

Outline Chapter Outline

What Goes Around a DSP?Linear ProductsLogic Products

C6000 SummaryHardware ToolsSoftware ToolsWhat’s Next?

What goes around a DSP?

5 - 2 C6416/C6713 DSK One-Day Workshop - Wrap Up




Chapter Topics Wrap Up..................................................................................................................................................... 5-1

What goes around a DSP?...................................................................................................................... 5-4 Linear.................................................................................................................................................. 5-4 Logic................................................................................................................................................... 5-8

C6000 Summary.....................................................................................................................................5-12 Hardware Tools .....................................................................................................................................5-13 Software Tools .......................................................................................................................................5-17 What’s Next?..........................................................................................................................................5-18 Before Leaving … ..................................................................................................................................5-22




Linear

Surround DSP with TI Products

DSPDSP

Data Converters • Analog-to-Digital Converters (ADC)

• Analog input to digital output • Output is typically interfaced directly to DSP

• Digital-to-Analog Converters (DAC) • Digital input to analog output • Input interfaces directly to DSP

• CODEC • Data converter system • Combination of ADC and DAC in single package

Power Management • Power Modules – complete power solutions • Linear Regulators – regulated power for analog and digital • DC-DC controllers – efficient power isolation • Battery Management – for portable applications • Charge Pumps & Boost Converters – portable applications • Supervisory Circuits – to monitor processor supply voltages and control reset conditions • Power Distribution – controlling power to system components for high efficiency • References – for data converter circuits



Analog Circuits – Considerations

ADC

DATATRANSMISSION

Anothersystem/

subsystem/etc.

Data Trans

DAC

OP-AMPs• Supply Voltage available?• Bandwidth required? (kHz or MHz)• What is the input signal?• What is the output driving?• # of channels needed?• Most Important Spec(s)?

Data Converter/AIC/Codec• Resolution? (bits… & ask for ENOB!) • Speed? (KSPS or MSPS for high speed,

KHz or MHz for precision ADCs, uS (settling time) for precision DACs)

• # of channels needed?• What is it interfacing to?

(uC/uP/DSP/FPGA/ASIC)

Interface• Speed? (k or M bits per second)• Distance?• Standard?• SERDES? –or- Topology needed? (point to point, multidrop, multipoint)

Power• Do you build your own power solutions, use

modules, or both? • What Input Voltage(s) & the source of these

voltages (Wall, battery, AC/DC, etc.) • What Output Voltage(s), and Output

Current(s) do you need?• How would you prioritize size, efficiency,

and cost?• What are the most important parameters in

the design? (efficiency, form factor, ripple voltage, tolerance, etc.)

Data Conversion

Digital(MSP430/DSP/uP/

FPGA/ASIC)

Signal-Conditioning

STANDARDSRS232RS422RS485LVDS1394/FirewireUSBPCICANSONETGigabit EthernetGTL, BTL, etc.

ClockingSolution

Clocks• Input frequencies?• Output frequencies desired & number

of copies necessary• Supply voltages available/required?• Special needs? (low jitter/jitter cleaner?

low part to part skew? etc.)

POWERManagement

A Real-TimeDSP-BasedSystem

Control and User Interface

What isReal-TimeSignal Processing?

A Typical Real-Time DSP System

Compressed audioor digital data

Power

RFFrontEnd

ADC

DAC

WeatherStocks

MusicTraffic

PowerAmp

Real-TimeSignal

Processing Engine

Digital Radio

. . . 01101010

01011010 . . .

ClockCircuits Interface

Circuits



5-6K Analog Interface – DSP Daughter-Card

• Compatible with current

C5000 and C6000 series DSK’s − C5416, C5510, C6416,

C6711, C6713 • Interface card has connectors

for flexible demos/prototyping: − 2 Signal Conditioning − 2 Serial − 1 Parallel Site

• Allows trial of hardware and debugging of software

• GPIO access through test points

• Flexible Clocking / Interrupts

Analog Cards

Single-width Serial-Interface Card

Double-wide Serial-Interface Card

5-6K Interface CardPlug in analog modules for:Plug in analog modules for:

•• Data ConvertersData Converters•• Signal ConditioningSignal Conditioning•• Power ManagementPower Management

http://focus.ti.com/docs/tool/toolfolder.jhtml?PartNumber=5-6KINTERFACE





Logic

1.8 V Logic

LVC

ALVC

2.5 V Logic

LVLVC

ALVC

LV

AC

ALB

LVC

LVT

AHC

ALVC

3.3 V Logic CBT

AHCAHCT

HC/HCT

AC/ACT

BCT

F

ALS

AS

TTL LS

S

ABT

LV

5+ V Logic

CD4000 FCT

Harris now TI

ETL

BTLGTL

HSTLSSTL

Specialty

1.5 V Logic 1.2 V Logic

Welcome to the World of TI LogicCypress now TI

TVC

AVC

AUC AUC

AVC

ALVT

ALVTALVT

AVC

CBTLV

AUC

0.8 V LogicAUC

GTLP

SSTV

CBTLV

ABT

ACHC/HCT

LVT74F64

24

128

5 10 15 20Speed - max tpd (ns)

BCT

CBT

I OL

Driv

e (m

A)

AC/ACT

AHC/AHCTAHC

ALVTALVT

5 V3.3 V2.5 V1.8 V

ALBAVCAVC

100

ABT Advanced BiCMOS TechnologyAC/T Advanced CMOSAHC/T Advanced High Speed CMOSALB Advanced LV BiCMOSALVC Advanced Low Voltage CMOSALVT Adv LV BiCMOS TechnologyAVC Advanced Very-LV CMOSAUC Advanced Ultra-LV CMOSBCT BiCMOS TechnologyCBT Cross Bar TechnologyCBTLV CBT Low Voltage Technology74F 74F Bipolar TechnologyFCT Fast CMOS TechnologyGTLP Gunning Transceiver Logic PlusHC/T High Speed CMOSLV Low Voltage HCMOSLVC Low Voltage CMOSLVT Low Voltage BiCMOS Technology

GTLP

GTLP

LVLV

FCTALVCALVC

1.2 V

0.8 V

AUCAUC

LVCLVC TTLLSALS

CD4K

50

Logic Families



TI Logic Supports Voltage Migration

AC* :7.0 nsAHC* :6.5 nsABT* :4.0 nsLV245 : 6.5 ns

LV245 :10 nsLVC4245 :6.3 nsLVCC3245 :6.0 ns LVCC4245 :7.0 nsALVC164245 :5.8 ns

LV245 :15 nsLVC* :4.8 nsLVCC3245 :9.4 nsAVC* :2.5 ns

LV245 : 15 nsLVC* : 4.5 nsALVC* : 3.7 nsALVT* : 3.5 nsAVC* : 2.0 nsAUC* : 2.5ns5V

3.3V

2.5V

1.8V

Vcc

LVC* : 7.1 nsALVC245 : 6.0ns nsAVC* : 4.0 nsAUC* : 2.0ns

LVC* :4.8 nsAVC* :4.0 ns * 16245 functions

AHC* :10 nsLV245 :10 nsLVT* :3.3 nsLVC* :4.0 nsALVC* :3.0 nsALVT* :2.4 nsALB* :2.0 nsAVC * :2.5 ns

5V - 2.5VLV,LVC,LVCC3245,ALVT

5V - 1.8VLVC

3.3V - 1.8VLVC,AVC

Additional Interface Capabilities

0.8V

AUC* : 5.0 ns

Little LogicExampleThe Principle Easy Naming from TI

SN74 Standard prefix74 = Commercial

LVC Product FamilyAHC, AHCT, LVC, CBT, AUC

1G 1G - Single Gate2G – Dual Gate3G – Triple Gate

00 Logic Function

YEA Package TypeYEA = NanoStarYZA = NanoFreeDCK = SC-70DBV = SOT-23DCU = US-8DCT = SM-8

R Tape & Reel

00 YEA R1GSN74 LVC

SN74AHC1G00DCKRSN74AHCT1G00DBVR

1 32

5 4

SN74AHC2G00DCTR SN74AHCT2G00DCUR

SN74LVC3G04DCTR SN74LVC3G04DCUR

Single Gate

Dual Gate

Triple Gate

Voltages -- AHC=5V, LVC=3V, AUC=1.8V



Features1.8V optimized performanceVCC Specified @ 2.5V, 1.8, 1.5, 1.20.8V typicalBalanced Drive3.6V I/O ToleranceBushold (II(HOLD))IOFF Spec for Partial Power-downESD protectionLow noiseSecond Source agreementsLittle Logic, Widebus, Octal

Advanced Packaging

NanoStar - YEASOT 23 - DBV (Microgate)SC-70 - DCK (PicoGate)TSSOP - PW & DGGTVSOP - DGVLFBGA - GKE & GKFVFBGA - GQL

The World’s First 1.8V LogicNEW FAMILYAUC

2.0 ns-8/8 mA1.8 VSN74AUC16244

2.5 ns-8/8 mA1.8 VSN74AUC1G00

TPD(MAX)DriveVCCDevice

HIGH SPEED

HIGH DRIVE

LOW NOISE

LOW POWER

PRIMARY CONCERN

ABT, 74F

ABT, 74F

ABT, AC/ACT

ABT, 74F

ABT, 74F

ABT

ABT, AHC

ABT, 74F

AHC, ABT

ABT, AHC

ABT

AHC, ABT

SECONDARY CONCERN 5V 3V 2.5VHIGH DRIVE

LOW NOISE

LOW POWER

HIGH SPEED

LOW NOISE

LOW POWER

HIGH SPEED

HIGH DRIVE

LOW POWER

HIGH SPEED

HIGH DRIVE

LOW NOISE

ALVT, LVT, ALVC

ALVC, LVT, LVC

ALVC, LVT, LVC

ALVT, LVT, ALVC

LVT

LVT

ALVC,LVT,LVC,LV

LVT

ALVC,LVT,LVC, LV,AHC

LVT, ALVC

ALVC,ALVT,LVT,LVC

ALVC,LVT,LVC.LV

AVC, ALVC, ALVT

AVC

AVC

AUC

AUC

AUC

1.8V

AVC, ALVC, ALVT

AVC

AVC

AUC

AUC

AUC

AVC

AVC

AVC

AUC

AUC

AUC

AVC

AVC

AVC

AUC

AUC

AUC

CHOOSING LOGIC



Host Interface

Host Bus

100100... 011001...

TIFIFOTMS320

DSP

TIFIFO

MEMORY

TIFIFO

TI FIFO’s

C6000 Summary


C6000 Summary TMS320C6000

Easy to UseBest C engine to dateEfficient C Compiler and Assembly OptimizerDSP & Image Libraries include hand-optimized codeeXpressDSP Toolset eases system design

SuperComputer Performance1.38 ns instruction rate: 720x8 MIPS (1GHz sampled)2880 16-bit MMACs (5760 8-bit MMACs) at 720 MHzPipelined instruction set (maximizes MIPS)Eight Execution Unit RISC Topology Highly orthogonal RISC 32-bit instruction setDouble-precision floating-point math in hardware

Fix and Float in the Same FamilyC62x – Fixed PointC64x – 2nd Generation Fixed PointC67x – Floating Point

C6000 Roadmap

Highest

Performance

Object Code Software CompatibilityFloating PointFloating Point

Multi-coreMulti-core C64x™ DSP1.1 GHz

C64x™ DSP1.1 GHz

C6201

C6701

C6202C6203

C6211C6711

C6204

1st Generation

C6713C6713

C6205

C6712

C6412C6412 DM642DM642

2nd Generation

C6415C6415

C6416C6416

C6411C6411

C6414C6414

Hardware Tools


Hardware Tools C6416 / C6713 DSK Contents

DSK Board

* DSK version of CCS requires DSK to be connected or CCS cannot startup

DSK Code Composer Studio CD ROM* DSK Technical Reference

Guide

Low-Cost Video I/F Demo Platform

Low-cost video interface demo shows how to connect an inexpensive 'C6000 DSP to a video decoder through a low-cost FPGA.

Low-cost video interface demo shows how to connect an inexpensive 'C6000 DSP to a video decoder through a low-cost FPGA.

(TI Kit# 6444886)

Hardware Tools


Tools of the Trade XDS560

eXtended Development System (XDS)Industry Standard Connections

PCI plugs into PCJTAG plugs into DSP target board

Download code up to 500Kbytes/secAdvanced Event Triggering for simple and complex breakpointsReal Time Data Exchange (RTDX) cantransfer data at 2Mbytes/sec

National Instruments LabVIEW

LabVIEW

LabVIEW DSP Test Integration Toolkit

Code Composer

StudioRTDX

LabVIEW Graphical Development For Debug and Diagnostics of DSP software

Automate Code Composer Studio

Communicate directly to DSP through RTDX

Integrate wide variety of I/O for DSP testing Share real time DSP data with RTDXAutomate routine Code Composer Studio functions from LabVIEW

Tools of the Trade

Hardware Tools


Hyperception’s VAB Tools of the Trade

Easy to use graphical ToolHierarchical:

Can write code graphically (down to ASM level instr.)One worksheet can become block in another worksheet

Block/Component Wizard:You can create an optimized VAB bldg blockCreate XDAIS algorithms

If desired, wrap PC interface into standalone EXEOutputs:

Directly to DSPBurn program to Flash with single-clickCreate an .OUT fileCreate Relocatable Object file (i.e. library) to use in CCS

MATLAB® CCS Plug-in

Capabilities:DSP program control, memory access, and real time data transfer with RTDX™ MATLAB automates testing and provides advanced analysisFunction call support enables hardware-in-loop simulation and debuggingC28x™ / C5000™ / C6000™ supportSupports XDS560™ and XDS510™Integrated with MATLAB design environment for a complete design solution

Tools of the Trade

Hardware Tools


Altera FPGA Daughter CardTools of the Trade

FPGA development system fits standard DSK daughter card socketsContains Altera FPGA software including power SOPC builder (shown above)

After designing and burning FPGA, DSP can talk to FPGA via memory-mapped addresses (SOPC creates C header file)

For more info: http://www.altera.com/products/devkits/altera/kit-dsp_stratix.html

Summary of all Hardware Tools

Hardware Tools

http://dspvillage.ti.com/docs/catalog/devtools/dsptoolslist.jhtml?familyId=132&toolTypeId=6&toolTypeFlagId=2&templateId=5154&path=templatedata/cm/toolswchrt/data/c6000_devbds

For a full list of tools available from TI and its 3rd Parties, please check:

Software Tools


Software Tools eXpress DSP

Hos

t Too

ls

Targ

et S

oftw

are

Largest DSP Third Party NetworkMake or buy…

> 650 companies in 3rd party network

> 1000 algorithms from > 100 unique 3rd parties

Tools of the Trade

What’s Next?


What’s Next? Optimizing C Performance

Attend a four-day workshop (see next slide)

Review the Compiler TutorialSee tutorials in CCS online help, orhttp://www.ti.com/sc/c6000compiler

Read:C6000 Programmer’s Guide (SPRU198)

Cache Memory User’s Guide (SPRU656)

C6000 Optimizing C Compiler Users Guide (SPRU187)

Look through the many application notes at:http://www.dspvillage.com

http://www.ti.com/sc/training

DSP Workshops Available from TIAttend another workshop:

4-day C2000 Workshops4-day C5000 Integration Workshops4-day C6000 Integration Workshop4-day C6000 Optimization Workshop4-day DSP/BIOS Workshop4-day OMAP Software Workshop1-day versions of these workshops1-day Reference Frameworks and XDAIS

Sign up at:

What’s Next?


C6000 Workshop ComparisonAlgorithm Coding and OptimizationSystem Integration (data I/O, peripherals, real-scheduling, etc.)

OP6000IW6000Audience

Using Peripherals (EDMA, McBSP, EMIF, HPI, XBUS)CPU Architecture & Pipeline DetailsC6000 Hardware

CSL, Hex6x, Absolute Lister, Flashburn, BSLCompiler Optimizer, Assembly Optimizer, Profiler, PBCTools

Software Pipelining LoopsDSP/BIOS, Real-Time Analysis, Reference FrameworksCreating a Standalone System (Boot), Programming DSK Flash

Calling Assembly From C, Programming in Linear AsmC Performance Techniques, Adv. C Runtime EnvironmentCoding & System Topics

Getting Started with TI DSP

Where To Go For More Informationwww.ti.com is your starting point

Install Code Composer Studio Free Evaluation Tools (FET) from the Essential Guide to DSP CDCheck out the DSP Selection Guide, it’s your consolidated resource for all pertinent information

dspvillage.ti.com•Getting Started•Discussion Groups•DSP Knowledge Base•Third Party Network•eXpressDSP Guided Tour

analog.ti.com•Design Resources•Technical Documents•Solution/Selection Guides

Sign up for Training• 1 day or 4 day workshops• 1 day DSK workshops• C2000, C5000, C6000 • DSP/BIOS• eXpressDSP

Applications SolutionsFind complete solutions for your application including: DSP, Analog, Boards Target Software, Development tools, third party support

What’s Next?


For More Information . . .

Phone: 800-477-8924 or 972-644-5580Email: [email protected]

Information and support for all TI Semiconductor products/toolsSubmit suggestions and errata for tools, silicon and documents

USA - Product Information Center ( PIC )

Website: http://www.ti.comhttp://www.dspvillage.com

FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm Device information my.ti.comApplication notes News and eventsTechnical documentation Training

Enroll in Technical Training: http://www.ti.com/sc/training

Internet

Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm

Phone: Language NumberBelgium (English) +32 (0) 27 45 55 32France +33 (0) 1 30 70 11 64Germany +49 (0) 8161 80 33 11Israel (English) 1800 949 0107 (free phone)Italy 800 79 11 37 (free phone)Netherlands (English) +31 (0) 546 87 95 45Spain +34 902 35 40 28Sweden (English) +46 (0) 8587 555 22United Kingdom +44 (0) 1604 66 33 99Finland (English) +358(0) 9 25 17 39 48

Fax: All Languages +49 (0) 8161 80 2045Email: [email protected]

Literature, Sample Requests and Analog EVM OrderingInformation, Technical and Design support for all Catalog TISemiconductor products/toolsSubmit suggestions and errata for tools, silicon and documents

European Product Information Center (EPIC)

What’s Next?


Looking for Literature on DSP?

“DSP Primer (Primer Series)”by C. Britton Rorabaugh; ISBN 0-0705-4004-7

“A DSP Primer : With Applications to Digital Audioand Computer Music”by Ken Steiglitz; ISBN 0-8053-1684-1

“DSP First : A Multimedia Approach”James H. McClellan, Ronald W. Schafer, Mark A. Yoder;ISBN 0-1324-3171-8

“A Simple Approach to Digital Signal Processing”by Craig Marven and Gillian Ewers; ISBN 0-4711-5243-9

Looking for Literature on ‘C6000 DSP?

“Digital Signal Processing Implementation using the TMS320C6000TM DSP Platform”

by Naim Dahnoun; ISBN 0201-61916-4

“C6x-Based Digital Signal Processing”by Nasser Kehtarnavaz and Burc Simsek;ISBN 0-13-088310-7

“ DSP Applications Using C and the TMS320C6x DSK”by Rulph Chassaing;ISBN 0471207543

Before Leaving …


Before Leaving … Let’s Go Home …

Thank’s for your valuable time todayPlease fill out an evaluation and let us know how we could improve this classIf you purchased a DSK:

Make sure you pack up (or receive) your DSK before leavingIf available, you may keep the earbud headphones and audio patch cable

Workshop lab and solutions files will be available via CDROM or the Internet. Please check with your instructor.

C6000 Workshops Comparison Table

Legend

Topic Discussed ü Topic Only Discussed Briefly ü- Includes A Hands-On Lab Exercise ü+ Not Discussed

Target Attendee IW6000 OP6000

System Integration (data input/output, peripherals, real-scheduling, etc.) ü Algorithm Development and Optimization ü

C6000 Hardware IW6000 OP6000

CPU CPU Architecture Details ü CPU Pipeline Details ü Peripherals C6000 Peripherals Overview ü ü Using CSL (Chip Support Library) to program peripherals ü+ DMA/EDMA (Direct Memory Access ) ü+ ü- Serial Port (McBSP) ü+ External Memory Interface (EMIF) ü+ Host Port Interface (HPI) ü+ XBUS ü- Memory Basic Memory Management ü+ ü+ Advanced Memory Management ü+ ü- Using Overlays ü+ Multiple Heaps Via DSP/BIOS ü+ C6000 Cache ü+ ü Cache Optimization ü

IW6000 = C6000 Integration Workshop

OP6000 = C6000 Optimization Workshop

Development Tools IW6000 OP6000

Code Composer Studio ü+ ü+ DSP/BIOS Configuration Tool ü+ ü+ C6711 DSP Starter Kit (DSK) ü+ ü- C6000 Simulator ü+ Compiler Options for Optimization ü- ü+ Assembly Optimizer ü+ Profile Based Compiler (PBC) ü+ Absolute Lister ü- Hex6x Utility ü+ FlashBurn ü+ C6711 Board Support Library (BSL) ü+

Coding IW6000 OP6000

Building Code Composer Studio Projects ü+ ü+ Compiler Build Options ü- ü+ Running C programs ü+ ü+ C Coding Efficiency Techniques ü+ Writing / Optimizing Assembly ü+ Linear Assembly Coding ü+ Calling Assembly from C ü+ Software Pipelining Techniques ü+ Numerical Issues with Fixed Point Processors ü C Runtime Environment (stack pointer, global pointer, etc.) ü C Optimization (pragmas and other techniques) ü+

System Topics IW6000 OP6000

DSP/BIOS Real-Time Scheduler ü+ DSP/BIOS Real-Time Analysis (LOG, STS) ü+ Reference Frameworks ü Double-Buffers For Data Input/Output ü+ Creating A Bootable Standalone System (Boot Without Emulator) ü+ Programming Flash Memory ü+ Interrupt Basics ü+ ü Advanced Interrupt Topics ü Interruptibility of High-Performance C Code ü XDAIS ( eXpressDSP Algorithm Standard) Introduction ü+

Who Should Attend The C6000 Optimization Workshop (OP6000) is primarily for software engineers writing code and algorithms for the C6000 family. It will also be useful for system designers evaluating the C6000’s CPU architecture.

The C6000 Integration Workshop (IW6000) may better suit your needs if you are tasked with building a system around the C6000. In this case you may need to know about: system design, using the C6000 peripherals to move data on/off-chip, scheduling real-time code, and design your DSP’s boot-up procedure.

The C6000 Integration Workshop (IW6000) is not a prerequisite to this workshop, though if you are looking for a broad introduction to all aspects of building a C6000 based system, the Integration Workshop might be a better choice. On the other hand, if you are evaluating the C6000 CPU architecture or want to learn how to write better C and assembly code for the C6000, this workshop (OP6000) would be the best choice. (Please refer to the C6000 Workshop Comparison for differences between the two workshops.)

Bottom Line:

w If you're main goal is to understand the C6000 architecture and write optimized software for it, then the C6000 Optimization Workshop (OP6000) is the best one to attend. Peripherals and other system foundation software (DSP/BIOS, XDAIS, CSL) are only peripherally mentioned. Many software engineers are tasked with getting their algorithms to run ... and run as fast as possible. This course is well designed to handle these issues.

w On the other hand, if you need to figure out how to get an entire system working -- from programming the peripherals to get data in/out all the way to burning the Flash memory with your final program -- the C6000 Integration Workshop (IW6000) is the ticket. Along the way you'll be introduced to (and use in lab exercises) many of the TI Software Foundation tools (DSP/BIOS, XDAIS, CSL, BSL, and Reference Frameworks). This is probably the single best course for an engineer/programmer that is new to the C6000 DSP and needs to get a whole system running, as opposed to just optimizing one or two algorithms.

w Of course, some engineers will need to handle both of these jobs. Get everything running and optimize their software algorithms. In that case, you may want to take both workshops.

TMS320C6000 DSP Platform Update

Revised: July 28, 2003

www.dspvillage.com Page 1 of 4

Product Info / Tech Support / Literature: North America [email protected] or (972) 644-5580 Europe [email protected]

Texas Instruments Website: http://www.ti.com or http://www.dspvillage.com DSP Knowledge Base: http://www-k.ext.ti.com/sc/technical-support/knowledgebase.htm C6000 SILICON BUDGETARY PRICING, SPECIFICATIONS & AVAILABILITY ♦ Pricing reflects year 2003 SUGGESTED RESALE and is subject to change. Please consult your preferred TI distributor for formal quotation requests. ♦ Prototype and production availability dates do not include product lead-times and are subject to change. Standard production lead-times are 10-12 weeks. TMS320C62x Fixed-Point Digital Signal Processors

Device C6201 C6202 C6202B C6203B C6204 C6205 C6211B MIPS 1600 2000/1600 2400/2000 2400/2000 1600 1600 1336/1200 MHz 200 250/200 300/250 300/250 200 200 167/150

Internal Memory

Prog:64KB (1) Data:64KB






L1 Prog:4KB (2) L1 Data:4KB (2) L2 P/D:64KB (2)

External Memory (EMIF) (6)

32-bit 52MB (4 CE)

32-bit 52MB (4 CE)

32-bit 52MB (4 CE)

32-bit 52MB (4 CE)

32-bit 52MB (4 CE)

32-bit 52MB (4 CE)

32-bit 512MB (4 CE)

Peripheral Port (8) 16-bit HPI 32-bit XBUS 32-bit XBUS 32-bit XBUS 32-bit XBUS 32-bit PCI 16-bit HPI

DMA (Channels)

Standard (3) (4+1)

Standard (3) (4+1)

Standard (3) (4+1)

Standard (3) (4+1)

Standard (3) (4+1)

Standard (3) (4+1)

Enhanced (4) (16+1+1)

McBSP 2 3 3 3 2 2 2 Timer /

Counters 2 2 2 2 2 2 2

Core Voltage 1.8V 1.8V 1.5V 1.5V 1.5V 1.5V 1.8V I/O Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

Package(s) (9) GJC or GJL GJL or GLS GNY or GNZ GNY or GNZ GHK or GLW GHK GFN TMS - prod NOW NOW NOW NOW NOW NOW NOW

TMS 1,000u $82.70 $110.08 / $94.03

$67.14 / $55.95

$71.62 / $60.43 $9.95 / $20.92

$10.74 $26.93 / $21.54

TMS320C67x and TMS320VC33 Floating-Point Digital Signal Processors Device C6701 C6711B C6711C C6712 C6712C C6713 VC33 (5)

MFLOPS (MIPS) 1000/900 900/600 1200 600 900 1350/900 150 / 120 MHz 167/150 150/100 200 100 150 225/200 75 / 60

Internal Memory

Prog: 64KB(1) Data: 64KB

L1 Prog: 4KB(2) L1 Data: 4KB(2) L2 P/D: 64KB(2)




L1 Prog: 4KB L1 Data: 4KB

L2 P/D: 256KB

P: 256B cache

P/D: 136KB External Memory (EMIF)(6)

32-bit 52MB (4 CE)

32-bit 512MB (4 CE)

32-bit 512MB (4 CE)

16-bit 512MB (4 CE)

16-bit 512MB (4 CE)

32-bit 512MB (4 CE)

32-bit 16M x 32 (4

CE) Peripheral

Port(8) 16-bit HPI 16-bit HPI 16-bit HPI ---- ---- 16-bit HPI ----

DMA (Channels)

Standard(3)

(4+1) Enhanced(4)

(16+1+1) Enhanced(4)




(16+1+1) C3x DMA(1)

McBSP 2 2 2 2 2 2 (or McASP)* 1 (not McBSP) Timer/Counters 2 2 2 2 2 2 2

Core Voltage 1.9V / 1.8V 1.8V 1.2V 1.8V 1.2V 1.2V 1.8V I/O Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

Package(s) (9) GJC GFN GDP GFN GDP GDP/PYP PGE TMS - prod NOW NOW NOW (TMX) NOW NOW (TMX) NOW (TMX) NOW

TMS 1,000u $113.13/78.57 $30.77 / $21.54 $21.55 $19.87 $14.95 $28.99/$22.35 $13.38 / $11.15

* The C6713 DSP can be configured to have up to three serial ports in various McASP/McBSP combinations by not utilizing the HPI. Other configurable serial options include I²C and additional GPIO. There are 16 GPIO pins.


TMS320C64x Fixed-Point Digital Signal Processors

Device C6411 C6412 C6414 C6415 C6416 DM642 DM641 DM640

MIPS 2400 4000 / 4800 4000 / 4800 / 5760

4000 / 4800 / 5760

4000 / 4800 / 5760 4000 / 4800 4000 / 4800 3200

MHz 300 500 / 600 500 / 600 / 720 500 / 600 / 720 500 / 600 / 720 500 / 600 500 / 600 400

Internal Memory

L1 Prog: 16KB L1 Data: 16KB L2 P/D: 256KB


L1 Prog: 16KB L1 Data: 16KB L2 P/D: 1MB






External Memory (EMIF)

32-bit, 256MB (4CE)

64-bit, 1024MB 64-bit, 1GB (4 CE) and

16-bit, 256MB (4 CE)

64-bit, 1GB (4 CE) and

16-bit, 256MB (4 CE)

64-bit, 1GB (4 CE) and

16-bit, 256MB (4 CE)

64-bit, 1024MB 32-bit, 256MB

32-bit, 256MB

Peripheral Port (8)

16/32-bit HPI or 32-bit 33MHz PCI


or 16-bit HPI +

EMAC

16/32-bit HPI 16/32-bit HPI or 32-bit 33MHz

PCI



or 16-bit HPI +

EMAC

16-bit HPI or 10/100Mbit EMAC

10/100 Mbit EMAC

DMA (Channels)

Enhanced (64)

Enhanced (64)

Enhanced (64)

Enhanced (64)

Enhanced (64)

Enhanced (64)

Enhanced (64)

Enhanced (64)

McBSP 2 Standard

2 Standard 3 standard 3 standard - or -

2 standard + Utopia 2

3 standard - or - 2 standard +

Utopia 2

3 20-bit Video Ports (VP) or 1

20-bit VP + 2 10-bit VP + 2 McBSP + 1 8-bit McASP

2 8-bit Video Ports + 2 McBSP + 1 4-

bit McASP

1 8-bit Video Port + 2 McBSP + 1 4-

bit McASP

H/W Accelerators ----

----

---- ----

Viterbi Decoder(VCP) Turbo Decoder

(TCP)

---- ---- ----

Timer/ Counters 2(7) 3 3 3 3 3 3 3

GPIO 16 16 16 16 16 16 8 8

Core Voltage 1.2V 1.2 (500MHz) 1.4 (600 MHz)

1.2V (500MHz) 1.4V (600MHz)

1.2V (500MHz) 1.4V (600MHz)

1.2V (500MHz) 1.4V (600MHz)

1.2 (500MHz) 1.4 (600 MHz)

1.2 (500MHz) 1.4 (600 MHz)

1.2 (400MHz)

I/O Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Package(s) (9) GLZ GDK/GNZ GLZ GLZ GLZ GDK/GNZ GDK/GNZ GDK/GNZ

Part Number TMS320C6411GLZ

TMX320C6412GDK

TMS320C6414GLZ

TMS320C6415GLZ

TMS320C6416GLZ

TMX320DM642 TMX320DM641 TMX320DM640

TMX / TMS NOW NOW / 4Q03 NOW NOW NOW NOW/ 4Q03 4Q03 / 1Q04 4Q03 / 1Q04 TMS 1,000u $42.21 $56.07 (TMX) $87.43/$107.84 $96.18/$131.16 $105.89/$145.73 $63.08 (TMX) $45.82 (TMX) $28.00 (TMX)

Notes: (1) C6201/C6204/C6205/C6701 internal program memory can be configured as cache or addressable RAM.

C6202/C6203 allows 512Kb to be programmed as cache or addressable RAM, the balance is always addressable RAM. (2) L1 data cache and L1 program cache are always configurable as cache memory. L2 is configurable between SRAM and cache

memory. (3) DMA has 4 fully configurable channels, plus one dedicated to host for HPI transfers. (4) C6211/C6711/C6712 Enhanced DMA (EDMA) has 16 fully configurable channels. Additionally, there is an independent single-

channel quick DMA (QDMA) and a channel dedicated to the host for HPI transfers. (5) VC33 is an upgrade TI’s ‘C3x family. While not a ‘C6000 device, it is part of TI’s floating-point family. (6) Each Chip Enable (CE) allows the user to assign a specific memory space. (7) A third timer is on-chip but not pinned-out. (8) Host Port Interface (HPI) is slave-only async host access.

Expansion Bus (XBUS) is master/slave async or sync interface; operates in host or FIFO/Memory modes. (9) These devices are Pin-for-Pin compatible: (Note, be aware of voltage differences.)

♦ (GJC) C6201/C6701 (GJL, GNZ) C6202/C6203, (GLS, GNY, GLW) C6202/C6203/C6204 ♦ (GFN) C6211/C6711/C6712 (GLZ) C6411/C6414/C6415/C6416 ♦ (GDP) C6713/C6711C/C6712C (GDK, GNZ) C6412/DM642/DM641/DM640

Packages: GGP = 35mm x 35mm, 1.27mm ball pitch 352-pin BGA GJC = 35mm x 35mm, 1.27mm ball pitch, 352-pin BGA GFN = 27mm x 27mm, 1.27mm ball pitch 256-pin BGA GJL = 27mm x 27mm, 1.0mm ball pitch 352-pin BGA GLS = 18mm x 18mm, 0.8mm ball pitch 384-pin BGA GHK = 16mm x 16mm, 288-pin µStar BGA PGE = 20mm x 20mm, 0.5mm pitch, 144-pin TQFP GLW = 18mm x 18mm, 340-pin BGA PYP = 28mm x 28mm, 0.5mm pitch, 208-pin PQFP GLZ = 23mm x 23mm, 0.8mm ball pitch, 532-pin BGA GNY = Same as GLS GNZ = Same as GJL GDP = 27mm x 27mm, 1.27mm ball pitch, 272-pin BGA GDK = 23mm x 23mm, 0.8mm ball pitch, 548-pin BGA


C6000 DEVELOPMENT TOOLS ♦ Please note that all C6000 tools support all C6000 family members (C62x, C67x, and C64x DSP CPUs) unless otherwise noted. ♦ All tools support Windows 98/2000/NT and Windows XP. C6000 HARDWARE DEVELOPMENT TOOLS

Development Tool Part Number Includes Price

DM642 EVM TMDXEVM642 TMDXEVM642-OE

DM642 EVM Baseboard, CCS v2.20.18 patch (CCS 2.0 required), Quick Start Guide, Technical Reference $1995

DM64x DMDK TMDXDMK642 TMDXDMK642-OE

DM642 EVM Baseboard, CCS v2.20 (for DM64x only), XDS560 PCI, NTSC or PAL Camera $6495

C6713 DSK TMDSDSK6713 TMDSDSK6713-0E

C6713 DSK, DSK CCS v2.2 including fast simulators.*1 $395

C6711 DSK TMDS320006711 TMDS320006711E

C6711 DSK, DSK Code Composer v2.1 *¹ Planned EOL--Being replaced by C6713 DSK

$395

C6000 TCP/IP NDK TMDX320036711 TMDX320036711E

C6000 TCP/IP Network Developer’s Kit (NDK) *² Not being updated to ccs v2.2 Planned EOL. $995

C6711 IDK TMDX320026711 TMDX320026711E

C6711 Imaging Developer’s Kit (IDK) *³ Not being updated to ccs v2.2 Planned EOL. $4500

C6416 DSK TMDSDSK6416 TMDSDSK6416-OE

C6416 DSK, DSK Code Composer Studio v2.2 including fast simulators and trace header*1

$395

C6416 NVDK TMDX3PNV6416SE TMDX3PNV6416S

C6416 Network and Video Development Kit Board Only * $4495

C6416 NVDK Bundle NVDKCCS NVDKCCSE

C6416 Network and Video Development Kit with CCS & Spectrum Digital 510PP+ *³ $5995

C6701 EVM Bundle TMDS3260D6701 C6701 EVM with Code Composer Studio ³ $3495 C6701 EVM Board TMDS3260C6701 C6701 EVM Board Only $1995

XDS510PP-Plus JTAG Emulator

TMDSEMUPP TMDSEMUPP-OE

Emulator with Parallel Port connection, JTAG cable $1500

XDS510 USB based emulator for Windows

TMDSEMUUSB TMDSEMUUSB-0E Emulator with USB connection, JTAG Cable $1995

XDS560 JTAG Emulator TMDXEMU560 PCI-bus JTAG Scan-Based Emulator $3995

C6416 TEB TMDX3260C6416 TMDX3260C6416E

C6416 Test Evaluation Board Only * Planned EOL for this product replaced by 6416 DSK $1995

C6416 TEB Bundle TMDX3260E6416 TMDX3260E6416E

C6416 Test Evaluation Board bundled with CCS & Spectrum Digital 510PP+ *³ Planned EOL for this product replaced by 6416 DSK

$3995

Additional hardware development tools are provided by TI’s large assortment of Third Parties. See the 3rd Party resource link below. * ”E” is European version ¹ CCS only works with the DSK. Does not include simulation and has 256K word program space memory limitation. ² CCS only works with the DSK. Does not include simulation however there is no memory limitation. ³ Full version of CCS.

C6000 SOFTWARE DEVELOPMENT TOOLS Code Composer Studio (CCS) is an integrated development environment (IDE) consisting of the Code Generation Tools (C compiler, assembler and linker), Debugger, Simulator, XDS-510 JTAG emulator drivers, Real-Time Data Exchange (RTDX) extensions, and the DSP/BIOS run-time environment.

Tool Description Part Number Components Price C6000 Code Composer Studio V2.2 (Windows 98/NT/2000) includes first year of annual subscription

TMDSCCS6000-1 IDE, Code Gen Tools, Debugger, Simulator, DSP/BIOS and RTDX, DSK, EVM and XDS-510 drivers

$3595

C6000 Code Composer Studio Annual S/W Subscription

TMDSSUB6000

Product Upgrades, Updates and Special Utilities

$599

* Specific upgrades to Code Composer Studio available to users with a current registration for previous versions of TI software development tools TOOL LINKS ♦ Chip Support Library (TI Home > DSP Village Home > Software > Peripheral Drivers > Chip Support Libraries) ♦ DSP Library, Image/Video Processing Library, FastRTS Library (TI Home > DSP Village Home > Software > Signal Processing Libraries > C6000 Libraries)


C6000 TECHNICAL DOCUMENTATION All released technical documentation & application notes can be found by referencing one of the following web sites: http://www.ti.com/sc/docs/general/dsp/docsrch.htm or http://dspvillage.ti.com GENERAL NUMBER REVISED LOCATION TMS320C6000 Technical Brief SPRU197d 02/1999 http://www-s.ti.com/sc/psheets/spru197d/spru197d.pdf TMS320C64x Technical Overview SPRU395b 01/2001 http://www-s.ti.com/sc/psheets/spru395b/spru395b.pdf TMS320C6711C Migration Document SPRA837 08/2002 http://www-s.ti.com/sc/psheets/spra837/spra837.pdf TMS320C6000 HARDWARE GUIDES NUMBER REVISED LOCATION C6000 CPU and Instruction Set Reference Guide SPRU189f 11/2000 http://www-s.ti.com/sc/psheets/spru189f/spru189f.pdf Update for TMS320C6000 CPU Guide (SPRU189F) SPRZ168b 08/2001 http://www-s.ti.com/sc/psheets/sprz168b/sprz168b.pdf C6000 Peripherals Reference Guide SPRU190d 02/2001 http://www-s.ti.com/sc/psheets/spru190d/spru190d.pdf C62x/C64x FastRTS Library Programmer’s Reference SPRU653 02/3002 http://focus.ti.com/lit/ug/spru653/spru653.pdf C6000 Instruction Set Simulator Technical Overview SPRU600a 12/2002 http://focus.ti.com/lit/ug/spru600a/spru600a.pdf C6000 DSP Multichannel Audio Serial Port (McASP) SPRU041b 05/2003 http://focus.ti.com/lit/ug/spru041b/spru041b/pdf C6000 DSP I2C Module Reference Guide SPRU175a 10/2002 http://foucs.ti.com/lit/ug/spru175a/spru175a.pdf C6000 Phase-Locked Loop (PLL) Controller SPRU233a 04/2003 http://focus.ti.com/lit/ug/spru233a/spru233a.pdf TMS320C6000 TOOLS GUIDES NUMBER REVISED LOCATION C6000 Programmer’s Guide SPRU198g 08/2002 http://www-s.ti.com/sc/psheets/spru198g/spru198g.pdf C6000 Optimizing C Compiler UG SPRU187i 04/2001 http://www-s.ti.com/sc/psheets/spru187i/spru187i.pdf C6000 Assembly Language Tools UG SPRU186i 04/2001 http://www-s.ti.com/sc/psheets/spru186i/spru186i.pdf Code Composer Studio User’s Guide SPRU328b 02/2000 http://www-s.ti.com/sc/psheets/spru328b/spru328b.pdf C6000 Code Composer Studio Tutorial SPRU301c 02/2000 http://www-s.ti.com/sc/psheets/spru301c/spru301c.pdf C6000 DSP/BIOS User’s Guide SPRU303b 05/2000 http://www-s.ti.com/sc/psheets/spru303b/spru303b.pdf TMS320C6000 DSP/BIOS App Programming I/F (API) SPRU403d 12/2001 http://www-s.ti.com/sc/psheets/spru403d/spru403d.pdf TMS320 DSP Standard Algorithm Developer's Guide SPRU424b 01/2002 http://www-s.ti.com/sc/psheets/spru424b/spru424b.pdf TMS320 DSP Algorithm Standard API Reference SPRU360b 03/2002 http://www-s.ti.com/sc/psheets/spru360b/spru360b.pdf C Source Debuggers UG for SPARCstations SPRU224 01/1997 http://www-s.ti.com/sc/psheets/spru224/spru224.pdf Chip Support Library API User’s Guide SPRU401d 04/2002 http://www-s.ti.com/sc/psheets/spru401d/spru401d.pdf TMS320C6000 DATA SHEETS (*) NUMBER REVISED LOCATION C6201 Data Sheet SPRS051g 11/2000 http://www-s.ti.com/sc/ds/tms320c6201.pdf C6202 Data Sheet SPRS104c 08/2002 http://www-s.ti.com/sc/ds/tms320c6202.pdf C6203B Data Sheet SPRS086g 08/2002 http://www-s.ti.com/sc/ds/tms320c6203b.pdf C6204 Data Sheet SPRS152a 06/2001 http://www-s.ti.com/sc/ds/tms320c6204.pdf C6205 Data Sheet SPRS106c 06/2001 http://www-s.ti.com/sc/ds/tms320c6205.pdf C6211/C6211B Data Sheet SPRS073f 09/2001 http://www-s.ti.com/sc/ds/tms320c6211.pdf C6701 Data Sheet SPRS067e 05/2000 http://www-s.ti.com/sc/ds/tms320c6701.pdf C6711/C6711B/C6711C Data Sheet SPRS088c 10/2002 http://www-s.ti.com/sc/ds/tms320c6711.pdf C6712/C6712C Data Sheet SPRS148a 10/2002 http://www-s.ti.com/sc/ds/tms320c6712.pdf C6713 Data Sheet SPRS186 12/2001 http://www-s.ti.com/sc/ds/tms320c6713.pdf C6411 Data Sheet SPRS196 03/2002 http://www-s.ti.com/sc/ds/tms320c6411.pdf C6414 Data Sheet SPRS134c 09/2001 http://www-s.ti.com/sc/ds/tms320c6414.pdf C6415 Data Sheet SPRS146c 09/2001 http://www-s.ti.com/sc/ds/tms320c6415.pdf C6416 Data Sheet SPRS164c 09/2001 http://www-s.ti.com/sc/ds/tms320c6416.pdf DM642 Data Sheet SPRS200a 04/2003 http://www-s.ti.com/sc/ds/tms320dm642.pdf VC33 Data Sheet SPRS087b 07/2002 http://www-s.ti.com/sc/ds/tms320vc33.pdf (*) For Military C6000 information and data sheets, please visit: http://www.ti.com/sc/docs/products/military/processr/index.htm

TI DSP Training Information Please visit the training webpage for a full details and schedules: http://focus.ti.com/docs/training/traininghomepage.jhtml

Workshops Length

C6416/C6713 One-Day Workshop 1 day C6000 Integration Workshop (IW6000) 4 days C6000 Optimization Workshop (OP6000) 4 days DSP/BIOS Design Workshop 4 days

ONLINE TRAINING ♦ TI Monthly DSP Customer Technology Webcasts:

http://www.ti.com/sc/webcasts ♦ Tech Online University:

http://www.ti.com/sc/docs/training/techonline.htm ♦ Network Video Developer’s Kit (NVDK):

http://ti-training.com/courses/coursedescription.asp?iCSID=1250

ADDITIONAL ONLINE RESOURCES ♦ FTP Site: ftp://ftp.ti.com/mirrors/tms320bbs ♦ TI & ME Online Sample Requests https://www-a.ti.com/apps/ti_me/ti_me.asp ♦ Software Upgrades & Registration / Hardware Repair & Upgrades (972) 293-5050 / (281) 274-2285 ♦ C6000 Platform Benchmarks: http://www.ti.com/sc/docs/products/dsp/c6000/benchmarks/index.htm ♦ Data Converters and Power Solutions http://www.ti.com/sc/docs/msp/dsps.htm

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