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TI MSP430 FRAM Introduction

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FRAM in Ultra-low Power 1 FRAM in Ultra-low Power MSP430 Microcontrollers Ultra-Low Power | Non-volatile | Easy-to-Use
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Page 1: TI MSP430 FRAM Introduction

FRAM in Ultra -low Power

1

FRAM in Ultra -low Power MSP430 Microcontrollers

Ultra-Low Power | Non-volatile | Easy-to-Use

Page 2: TI MSP430 FRAM Introduction

FRAM – Technology Attributes

• Non-Volatile – retains data without power

• Fast Write / Update – RAM like performance. Up to ~ 50ns/byte access times today (> 1000x faster than Flash/EEPROM)

Photo: forums.wow-europe.com

2

• Low Power - Needs 1.5V to write compared to >10-14V for Flash/EEPROM � no charge pump

• Superior Data Reliability - ‘Write Guarantee’ in case of power loss and > 100 Trillion read/write cycles

Automotive F-RAM Memory

Page 3: TI MSP430 FRAM Introduction

FRAM- The best of all worlds!

Not affected byEEPROM

BestULP

Operation!

Unified / NVMemory!

Not affected bymagnetic fields!

EEPROMsubstitution!

100 trillionultra-fast read/write cycles!

Lowest Energyat high

temperature!

Page 4: TI MSP430 FRAM Introduction

FRAM: Proven, Reliable• Endurance

– Proven data retention to 10 years @ 85°C

• Less vulnerable to attacks– Fast access/write times

• Radiation Resistance– Terrestrial Soft Error Rate (SER) – Terrestrial Soft Error Rate (SER)

is below detection limits

• Immune to Magnetic Fields– FRAM does not contain iron!

TI has shipped over 30 MU of FRAM already!

Volume production ongoing over last 10 years (Ramtron)

www.ti.com/framFor more info on

TI’s FRAM technology

Page 5: TI MSP430 FRAM Introduction

Target Applications

• Energy harvesting, especially Wireless

– Low Power & Fast Memory Access, especially Writes

• Data logging, remote sensor applications

– High Write endurance, Fast writes

• Battery powered consumer/mobile Electronics • Battery powered consumer/mobile Electronics

– Low power

• Battery Backed SRAM Replacement

– Non- Volatility, High Write Endurance, Low power, Fast Writes

• Digital rights management

– High Write Endurance – need >10M write cycles

Page 6: TI MSP430 FRAM Introduction

FRAM for Wireless Updates

Challenge FRAM solution

Over the air updates

Home automation

Consumes up to 1 month battery life for a single update

Uses < 1/4 day battery life

Safety & security

Write guarantee in case of power loss

Bit level access

Metering

Block level erase & program

Need redundant (mirror) memory blocks

Page 7: TI MSP430 FRAM Introduction

FRAM for Sensor Data logging

Challenge FRAM solution

Sensor Data logging

Power consumption limits locations, increases maintenance

Energy harvesting enables more sensors in more locations

Continuous and reliable Asset

Tracking Sports &

Continuous monitoring

Continuous and reliable monitoring , storage and RF transmission

Limited data update/write speed

Selective monitoring

Tracking Sports & Fitness

Seismicmonitoring

Flow meters

Page 8: TI MSP430 FRAM Introduction

All-in -one: FRAM MCU delivers max benefitsFRAM SRAM EEPROM Flash

Non-volatile Retains data without power

Write speeds

Average active Power [µA/MHz]

Yes Yes YesNo

10ms 2secs<10ms 1 sec

50mA+<60<110 230

8

Power [µA/MHz]

Write endurance

DynamicBit-wise programmable

Unified memoryFlexible code and data partitioning

50mA+<60<110 230

10,000100,000Unlimited100

Trillion+

YesYes NoNo

Yes NoNoNo

Data is representative of embedded memory performance within device

Page 9: TI MSP430 FRAM Introduction

Power & Clocking

MSP430FR57xx Microcontroller

Memory16KB / 8KB / 4KB FRAM(with segment protections

for code/data)

Debug

Real-time JTAG

Boot Strap Loader

Embedded Emulation

• Power on Reset• Brownout Reset• Low Power

Vreg(1.5V)• XT1, VLO• DCO • Real Time Clock

Timers

16-bit RISCMCU

Up to 24 MHz

Peripherals

• Performance• Up to 24MHz

• Power Numbers• Active Mode: 103 µA/MHz @

8MHz • RTC mode (LPM3.5): ~1.5 µA• Standby Mode (LPM3): 6.4 µA• Shutdown Mode (LPM4.5): ~0.3

SRAM .5/1KB

MSP430™ |FR58xx/59xx Next Gen FRAM

9

DMA (3ch)

32 x 32 Multiplier

Serial Interface

ADC10 (up to 12ch)

Analog

Timers

Timer0_A3

Timer1_B3

Watch Dog Timer

PortsUp to 3 1x8 + 1 1x3 I/O Ports

w/ interrupt/ wake-up

CRC16

Universal Serial Comm. Interfaces • 2 UARTs or SPI • 1 I2C or SPI

Timer2_A3

Comparator / REF

Timer3_B3

Timer4_B3

Peripherals• Shutdown Mode (LPM4.5): ~0.3

µA• Flexible Unified Memory

• 16/8/4 KB FRAM versions with program code / data memory partitioning

• Package• 24/40-Pin QFN, 28, 38-Pin

TSSOP• Temp Range -40ºC to 85ºC• MSP430FR5739 $2.15 at 1kU

Page 10: TI MSP430 FRAM Introduction

FR57xx Architecture & Core Peripherals

10

Page 11: TI MSP430 FRAM Introduction

MSP430xv2 Orthogonal CPU•No changes from the F5xx CPU!

•C-compiler friendly

•Memory address access up to 1MB

•CPU registers 20-bit wide

•Address-word instructions

•Direct 20-bit CPU register access

11/30/2011 11

•Direct 20-bit CPU register access

•Atomic (memory-to-memory) instructions

•Instruction compatible w/previous CPU

•Cycle count optimization for certain instructions

Page 12: TI MSP430 FRAM Introduction

Operating Modes

• Active Mode – <110 µA/MHz!– CPU active– Fast Peripherals Enabled– 32 kHz Peripherals Enabled - RTC

• LPM0 – 170 µA– CPU disabled, Fast Peripherals Enabled – Fast Wake up – 32 kHz Peripherals Enabled – RTC

• LPM3 – 6.4 µA– CPU disabled, Fast Peripherals Disabled– Slow wake up

11/30/2011 12

– Slow wake up – 32 kHz Peripherals Enabled

• RTC, Watchdog & SVS protection

• LPM4 – 5.9 µA– All clocks disabled– Wake on interrupt

• LPM3.5 – 1.5 µA– Regulator & all clocks disabled – Complete FRAM retention– BOR on nRST/NMI or Port I/O or RTC

• LPM4.5 – 0.32 µA

Page 13: TI MSP430 FRAM Introduction

Supply Voltage Supervision (SVS)

• Supply voltage supervision highly simplified compared to F5xx family

• Individually enabled for high (supply)/ low (core) sides

• Hard-coded threshold levels

• Device reset tracks with SVSH

13

• SVSH – Enabled in all modes, cannot be disabled– Disabled in LPM4.5

• SVSL – Enabled in active, LPM0, cannot be disabled– Can be disabled in LPM1,2 (default enabled)– Disabled in LPM3,4,x.5

PMM Action at Device Power-up

Page 14: TI MSP430 FRAM Introduction

• Five independent clock sources– Low Freq

• LFXT1 32768 Hz crystal• VLO 10 kHz

– High Freq• XT1 4 – 24 MHz crystal• XT2 4 – 24 MHz crystal• DCO Specific CAL range

• Default DCO = 8MHz

Clock System (CS)

ACLK

• Default DCO = 8MHz– MCLK = DCO/8 = 1MHz

• ACLK / SMCLK / MCLK tree is fully orthogonal

• MODOSC provided to modules– ADC10

• Failsafe– XT1LF: VLO – XT1HF or XT2: MODOSC

MCLK

SMCLK

Page 15: TI MSP430 FRAM Introduction

Demos:

- Write speed comparison- Power consumption details

15

- Power consumption details

Page 16: TI MSP430 FRAM Introduction

USB Connection Debugging and Programming Interface

NTC Thermistor

LED0 – LED8

SBW and MSP430 Application UART

MSP-EXP430FR5739 Experimenter’s Board

16

AccelerometerLED0 – LED8

MSP430FR5739 device

User Input Switches S1,S2

Reset switch

Connection to EXP-MSP430F5438

Connection to CCxx daughter cards

Page 17: TI MSP430 FRAM Introduction

Write speed comparison

PC Debug data

17

FRAM Write speed Emulated flash Write speedLED Tracking

Page 18: TI MSP430 FRAM Introduction

And the power number is…

Demo A: Observations (simple while (1); loop in man .c)

• Measure power across VCC jumper of the eZFet

• MCLK = DCO = 8MHz; Meter reads <600µA or ~75µA/MHz

Observations:

• Single word opcode (JMP$) � Code execution is completely within the

18

• Single word opcode (JMP$) � Code execution is completely within the cache (SRAM)

• Hence the low active power!

Connect meter across Vcc

Use USB for Power

Page 19: TI MSP430 FRAM Introduction

A More Realistic Scenario

Demo B

• Function Active_mode_test() = combination of RAM, FRAM access + different addressing modes

• Closer to typical application use-case

• Use this function to measure ‘real world’ active power

• Comment out the while(1); loop

19

• Comment out the while(1); loop

• Include ACTIVE_MODE_TEST() function call

• Rebuild Project

• Download & execute the code, terminate debug session

Note: Remember to reconnect the jumper to program the target or leave the meter ON

Page 20: TI MSP430 FRAM Introduction

Source Code Snapshot

20

Ensure that this function call is included

Page 21: TI MSP430 FRAM Introduction

And now we measure…

Demo B: Observations

• MCLK = DCO = 8MHz

• Meter reads <800µA or 100µA/MHz

Observations:

• As # of cache misses increase, active power increases

21

• As # of cache misses increase, active power increases

• Cache hit/miss ratio is completely application dependent

• Tighter, shorter loops = fewer cache misses

Page 22: TI MSP430 FRAM Introduction

FR57xx Peripheral Additions & Enhancements

22

Enhancements

Page 23: TI MSP430 FRAM Introduction

ADC10_B

Feature Enhancements

• Significant power savings– 150µA Vs 1.2mA on F2xx

• Up to 200ksps

• REF – unique module– 1.5V, 2V and 2.5V

23

– 1.5V, 2V and 2.5V

• DTC replaced by DMA

• Up to 12 external input channels

• Window Comparator – Hi, low and middle interrupts

Page 24: TI MSP430 FRAM Introduction

RTC_B and Comp_D

RTC_B

• Calendar mode only

• LFXT1 32768Hz required

• Advanced interrupt capability –alarms, OF fault, RTCREADY and RTCEV

COMP_D

• Interrupt driven for low power

• Uses the REF module like ADC10_B

• Up to 15 external input channels

• Software selectable RC filter

24

RTCEV

• Selectable BCD format

• Calibration

• Multiple Alarms

• Operation in LPM3.5

• Selectable reference voltage generator

• Voltage Hysteresis generator

Page 25: TI MSP430 FRAM Introduction

JTAG and BSL

JTAG• Security can be achieved by:

• Fuse is in software

1) JTAG lock and unlock - Access granted only if tool chain

supplies correct password

BSL• Similar to F5xx BSL but

• Code in Boot ROM – cannot be modified

• Peripheral Interface: HW UART

• BSL Entry and signature same as

25

2) JTAG fuse blow- Access only via BSL if password is

know- JTAG can be re-enabled via BSL

3) JTAG fuse blow + BSL disable- No further access to device is

possible

• BSL Entry and signature same as F5xx

Page 26: TI MSP430 FRAM Introduction

eUSCI_A: UART

• Architecture is maintained mostly compatible with USCI_A

• Register mapping from USCI to eUSCI available in migration document

• New features include– UCTXCPTIE interrupt similar to TXEPT flag in USART– Enhanced baud rate calculator: Increased flexibility with modulation pattern

settings

26

settings– UCSTTIE interrupt for start bit detection– Increased flexibility with deglitch filter

Page 27: TI MSP430 FRAM Introduction

eUSCI_A: SPI

• Architecture is maintained mostly compatible with USCI_A

• Register mapping from USCI to eUSCI available in migration document

• Supports higher baud rates– The USCI-SPI supported upto 4MHz max. bit rate – The goal for the eUSCI is to support upto 10MHz

• Modified 4-pin SPI mode

27

• Modified 4-pin SPI mode – Can now be used as a ‘true’ chip select in master mode

Page 28: TI MSP430 FRAM Introduction

eUSCI_B: I2C

Many new features have been added:

• Multiple slave addresses

• Clock low timeout for SMBus compatibility

• Byte counter

• Automatic stop assertion

28

• Automatic stop assertion

• Preload for master/slave transmitter

• Address bit masking

• Selectable deglitch timing

• ACK/NACK selectable in software

Page 29: TI MSP430 FRAM Introduction

Using FRAM on the FR57xx

29

Using FRAM on the FR57xx

Page 30: TI MSP430 FRAM Introduction

Unified Memory

One device supporting multiple options “slide the bar as needed”

Multiple device variants may be required

Before FRAM With FRAM

16kB Flash (Program)

2kB SRAM 16kB Universal FRAM

30

• Easier, simpler inventory management

• Lower cost of issuance / ownership

• Faster time to market for memory modificationsTo get more SRAM you may have

to buy more FLASH ROM

1kB EEPROM

Often an additional

chipis needed

14kB Flash2kB

SRAM

24kB Flash5kB

SRAM

Data vs. program memorypartitioned as needed

Page 31: TI MSP430 FRAM Introduction

Memory Protection Unit (MPU)

• FRAM is so easy to write to…

• Both code and non-volatile data need protection

• MPU protects against accidental writes [read, write and execute only permissions]

• Features include:

31

• Features include:– Configuration of main memory in three variable sized segments– Independent access rights for each segment – MPU registers are password protected

Page 32: TI MSP430 FRAM Introduction

Calculating Segment Boundaries

• Size of segment determined by setting the MPUSB register (Segment Borders)

• Total # of bits = 5

• For 16K device– Segment Granularity =16*1024 / 32 = 512 bytes

32

Page 33: TI MSP430 FRAM Introduction

Creating Segments in 4 Easy Steps

Segment 1 = 0xC200 to 0xCDFF

Segment 2 = 0xCE00 to 0xD7FF

Segment 3 = 0xD800 to 0xFFFF

Step 1: Decide segment boundaries

Step 2: Look up User’s Guide Table for MPUSBx value s

33

Step 2: Look up User’s Guide Table for MPUSBx value s

MPUSBx[4:0] Page_start Address

0x01 0xC200

….. 0xCxxx

0x07 0xCE00

… 0xCxxx

0x0C 0xD800

B1

B2

Page 34: TI MSP430 FRAM Introduction

Differentiating with the FR57xx

34

Page 35: TI MSP430 FRAM Introduction

Continuous ultra -low -power data logging

Write Endurance10,000 cycles

> 100,000,000,000,000 cycles

Trillions

Supports more than 150,000 years of continuous data logging (vs. less than 7 minutes with Flash)

Page 36: TI MSP430 FRAM Introduction

FRAM | Industry-Leading Speeds

• 1000x faster than flash

• RAM-like performance– ~50ns Access time

• No pre-erase required for writes

2

MBps

2500

Write Speed

2200

Power Consumption (µA)

writes

• No additional power is needed for FRAM writes – CPU not held– Interrupt enabled during

writes

MBps

12

kBps0

500

1000

1500

2000

FRAM Flash

720

Flash/EEPROM FRAM

Page 37: TI MSP430 FRAM Introduction

FR57xx in the Energy Plane

A small up-front payment inwake-up time!

For a hugeenergy pay-backin active mode!

fact

or: 1

00x

-25

0x

Flash Write

pow

er

Energy

factor: 100x - 1000x

fact

or: 1

00x

LPM3

Active

Flash Write

FRAM Write

Wake-up event time

Page 38: TI MSP430 FRAM Introduction

FRAM - Realtime Data Logging!

• Superior Realtime performance due to fast write!

• External events• Incoming interrupts

I1 I2 I3 I4

Flash Write for I1

• Weak interruptperformance

„Stuck in Flash“

FRAM Writes for I1, I2, I3, I4

„Stuck in Flash“

• Strong interruptperformance

• Quick Low energyFRAM update

Page 39: TI MSP430 FRAM Introduction

• Use Case Example: EEPROM Vs MSP430FR5739

• Many systems require a backup procedure on power fail

• FRAM IP has built-in circuitry to complete the current 4 word write• Supported by internal FRAM LDO & cap

• In-system backup is an order of magnitude faster with FRAM

FRAM = Increased flexibility

39+ Source: EE Times Europe, An Engineer’s Guide to FRAM by Duncan Bennett

Write comparison during power fail events+

Page 40: TI MSP430 FRAM Introduction

Tools & Resources

40

Page 41: TI MSP430 FRAM Introduction

Getting Started with MSP430FR5739

• MSP430FR5739 Target Board

• Development board with 40-pin RHA socket (MSP-TS430RHA40A)

• All pins brought out to pin headers for easy access

• Programming via JTAG, Spy-bi-wire or

41

• Programming via JTAG, Spy-bi-wire or BSL

• $99

Page 42: TI MSP430 FRAM Introduction

Getting Started with MSP430FR5739

• MSP-EXP430FR5739 FRAM Experimenter’s Board

• $29

• On Board Emulation

• Features– 3 axis accelerometer– NTC Thermister– 8 Display LED’s

42

– Footprint for additional through-hole LDR sensor– 2 User input Switches

• User Experience– Preloaded with out-of-box demo code– 4 Modes to test FRAM features:

• Mode 1 - Max FRAM write speed• Mode 2 - Flash write speed emulation • Mode 3 – FRAM writes using sampled

accelerometer data• Mode 4 – FRAM writes using sampled

Thermistor data

Page 43: TI MSP430 FRAM Introduction

Getting Started with MSP430FR5739

• www.ti.com/fram

• Product Page from www.msp430.com

• Upcoming Collateral: – Maximizing FRAM Write Speed– FR57xx Migration Guide– FR-EXP Tool User’s Guide

43

– FR-EXP Tool User’s Guide – FRAM Reliability Application Report– Code Examples – Embedded Developers Guide to FRAM– FRAM for Dummies by V.C. Kumar


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