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Time-Memory Scheduling and Code Generation ofReal-Time Embedded Software
Chuen-Hau Gau and Pao-Ann Hsiung
National Chung Cheng University
Chiayi, Taiwan, R.O.C.
8th International Conference on Real-Time Computing Systems and Applications, March 18-20, 2002, Tokyo, Japan
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Outline
Introduction
Previous Work
Real-Time Embedded Software Synthesis
ATM VPN Server Example
Conclusions
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Introduction
Embedded systems abound in human daily life We interact with embedded systems in
our homes, at offices, at labs, on transportations, in communications, …
Due to this interaction with humans, most embedded systems are also REAL-TIME systems
And, software accounts for more than 70% functionalities in a real-time embedded system
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What is an embedded system?
Installed in a larger system
Dedicated task
Small Memory Space (200~400 KB)
Low Processing Power (100~200 MHz)
Unstable Environment (mobile, …)
Reactive
Real-Time
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Embedded System Examples
medical instrumentshome appliancesoffice equipments
space crafts research lab equipments
factory automation
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Design Issues and Solution
2. Real-Time Constraints
1. Bounded Memory Execution
Proposed Solution
Time Memory Scheduling (TMS)
Code Generation
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Previous Work
Formal Software Synthesis
Safe Petri-Nets (PN) Quasi-Static Scheduling (QSS) [Lin: DATE’98, DAC’98]
Free-Choice PN Net Decomposition + QSS [Sgroi: DAC’99]
Codesign FSM POLIS [Balarin: ICCD’99]
Non-timed multi-rate PN Reachability graph[Cortadella et al: DAC’00]
Time Free-Choice PN QSS + RTS or FIBS [Hsiung: CODES’01, FORTE’01]
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Real-Time Embedded Software (RTES) Model Real-Time Embedded Software is specified
as a set of Colored Time Petri Nets (CTPN)
Allows explicit modeling of Timing Constraints
Memory Usages
No free-choice restriction!
Larger domain of real-time embedded applications!
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Colored Time Petri Nets
t2
t0
t3
t5
t1
t4
p0
p1
p2
p4
p3
[2, 5]
[1, ]
[1, 5]
[3, 6]
[7, 7]
[1, 2]
{(1, red), (1,green), (1,blue)}
{(2, black), (1, red)}
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Colored Time Petri Nets
A CTPN is a 6-tuple (P,T, C, ,M0,) such that: P is a finite set of places, T is a finite set of transitions, P T , P T
= , C is a set of colors associated with each token : (P T ) (T P ) 2NC, a set of weighted
arcs such that each arc is associated with a set of integer-color pairs,
M0: P 2NC, the initial marking, (t ) = (, ), t T, : Earliest Firing Time,
: Latest Firing Time.
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CTPN Marking
A marking is a vector
M = <NC1, NC2, …, NC|P|>
where NCi is a set of integer-color pairs representing the non-negative number of colored tokens in place pi.
2 attributes are associated with each M: (1) a time-stamp (M) (2) a memory-usage (M)
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Valid Firing (System Execution) A transition t is said to be enabled at time in a markin
g M with time-stamp (M) if: (1) (pk, t) NCk, (pk, t) , k {1, …,|P|},
(2) (M) (t)
The firing of a transition t at time in a marking M with time-stamp (M) is called a valid firing if: Transition Deadline:
(t) (M) (t)
Memory Constraint: (M') max
where M' is the marking obtained by firing t in M and max is the maximum amount of memory available.
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RTES Synthesis Problem
Target Problem
Real-Time Embedded Software Synthesis
Given: a set of CTPN S = {Ai | i = 1,2,…,n}, an upper-bound max on memory space, and a set of real-time constraints: CTPN periods, deadlines
software code is to be generated such that
1. it can be executed on a single processor,
2. it uses memory less than or equal to max, and
3. it satisfies all EFT, LFT, and real-time constraints.
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RTES Synthesis Algorithm
Choice Set:
H = {t2, t3, t4}
t2
t3
t4
p1
[2, 5]
[7, 7]
[1, 2]
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RTES Synthesis Algorithm
Exclusion Set
H = {t2, t3, t4}
Merging of all
non-disjoint
choice sets
t2
t3
t4
p0
p1
p2
[2, 5]
[7, 7]
[1, 2]
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RTES Synthesis Algorithm
Time-Memory Scheduling
A schedule (sequence of firing transitions) is valid if the following are satisfied: Transition deadline
CTPN deadline
Memory bound
Incomplete exclusion sets are deleted (because corresponding code will be illegal)
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RTES Synthesis Algorithm
Transition Deadline Satisfaction
Assume transition t:
enabled at marking M with time-stamp (M)
fired at marking M with time-stamp (M),
then it must satisfy
(M) - (M) + (t) (t)transition deadline
transition execution time
token age
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RTES Synthesis Algorithm
CTPN Deadline Satisfaction
Assume transition t:
fired at marking M
(M) + (t) d
CTPN deadline for current task
transition execution time
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RTES Synthesis Algorithm
Memory Bound Satisfaction
Assume transition t:
fires and CTPN reaches marking M
(M) max
memory bound
memory usage
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RTES Synthesis Algorithmwhile( |Tree| != 0 ){ if( Entire Tree Marked ) CodeGen();
if( Current Node Is Spawned ){ Current Node :: Delete Incomplete Exsets
if Current Node :: Has Marked Child Current Node :: Delete Other Child, Mark, Go Parentif(Child := SELECT() == null) Current Node :: Delete Current and Go Parentelse Current Node :: Go Child }
else{ if(Current Node Is A CompleteSchedule)
Current Node :: Mark and Go Parentelse Current Node :: Spawn }
}
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RTES Synthesis Algorithm
Memory Estimation
Global Memory: G(R), R: tree
Local Memory: maxtM (L(t)), t: transition,
M: marking Buffer Memory:
Total Memory: )()(maxmaxmax MtRS BLMtRM
GSR
Pi NCcnCB
i
cnM1 ),(
)(
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Code Generation
A real-time process for each independent task, i.e., each reachability tree
# tasks is minimal (= # independent tasks)
Main Program
Processi
Task 1 Task 2 Task k…
Source Transitions in TFCPN
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Code Generation Algorithm
Extract( CNode ) {if( CNode is leaf ) // no child{ Code += getCode(CNode);
Code += “return;”;}else if( CNode is branching ) // multi-child{ Code += getBranchCode(CNode);
for each child node CNode.ciExtract(CNode.ci);
}else // one child{ Code += getCode(CNode);
Extract(CNode.child) }return(Code);
}
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ATM VPN Server
ATM switching nodes interconnect LANs via an ATM backbone.
An ATM server:
temporarily stores input cells from VCCs (Virtual Channel Connections), and
forward VCC cells to the VPCs (Virtual Path Connections) by identifying cell headers.
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CASE STUDY: AN ATM VIRTUAL CASE STUDY: AN ATM VIRTUAL PRIVATE NETWORK SERVERPRIVATE NETWORK SERVER
CLASSIFIERCLASSIFIERCONGESTION CONGESTION
CONTROL CONTROL (MSD)(MSD)
SUPERVISORSUPERVISOR
WFQ WFQ SCHEDULERSCHEDULER
ATM INATM IN
(155 (155 Mbit/sMbit/s))
ATM OUTATM OUT
(155 (155 Mbit/sMbit/s))
DISCARDED DISCARDED CELLSCELLS
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Functionalities of ATM VPN
1. Message Selective Discarding (MSD):A message discarding technique that avoids buffer overflow by discarding selected incoming cells
2. Weighted Fair Queuing (WFQ):A bandwidth control policy for outgoing flows
Thus, there are TWO independent tasks!
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ATM VPN Server
Message SelectiveDiscarding
Cell ExtractCounter
WFQ scheduling
VCC cell
TICK
PUSH
INSERT
POP
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CTPN model of MSD in ATM
CID READ_STATE_VCC UPDATE_STATE_INIT
p1
p2
p3
p4
p5
p6
p7
p8
p10
MSD
PTI
TI
t1
READ_OUT_QUID
t2
t6
t9
p9
p11
p12
p15
p16
p19
p13
p14
p17
p18
p20
p22
p23
t3
t4
t5
READ_MAX_QLENGTH
CHECK_QLENGTH
t8
READ_THRESHOLD
CHECK_QLENGTH
t7
t11
UPDATE_STATE_REJ
t10
t12
PUSH
Qlength < thres ?
UPDATE_STATE_ACC
N
Y
Qlength <max ?
Y
N
p21
Qlength = 0 ?
*SCHEDULE_WFQ
COMPUTE_OUT_TIME
Y
N
p24 st=2
st=0
st=1
PTI = 1/3 ?
Y
N
[1, 16]
[10, 25]
[9, 9]
[6, 15]
[12, 37]
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CTPN models of WFQ, Extract
*SCHEDULE_WFQ READ_BW
READ_LAST
t13
t14
t15
LAST + BW>
GLOBAL_TIME ?
N
Yp25
p26
p27
p28p29 P30
INSERT_CELL
p34 p35
p33p32p31
p37
p36
p38 p39
POP
CHECK_QLENGTH
t19
COMPUTE_OUT_TIME
*SCHEDULE_WFQ
t17
t18
TICK
I=I+1
I=0
t16
READ_SORTERQlength=0?
Y
N
CELL_OUT_TIME<=GLOBAL_TIME?
Y
NI=N? N
Y
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Reachability Treefor MSD
Schedule Results: 49 markings 14 schedules 66 instructions 12 Kbytes
Memory
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Reachability Trees for WFQ and Extract
Schedule Results:
WFQ 9 markings 2 schedules
Extract 13 markings 4 schedules
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Scheduling Results
Both MSD and Extract call WFQ (2 schedules)
MSD Task
# schedules = 14 2 = 28
Extract Task
# schedules = 4 x 2 = 8
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Conclusions
A synthesis method for real-time embedded software was presented
No free-choice restriction on model
Explicit time and data modeling
Both real-time constraints and memory constraints are considered for scheduling
Minimal number of tasks in generated code
Can be used for prototyping platforms