Timing in Sequential circuits –

Stabilization time of a latch

R

S

Q

Q’

Assume that:thl,1 = tlh,1 = thl,2 = tlh,2 = 1 time unit

1

2

Timing in Sequential circuits –

Stabilization time of a latch

Time R S Qt Q’t Qt+1 Q’t+1

1 1 0 0 0 1 1

R

S

Q

Q’

Timing in Sequential circuits –

Stabilization time of a latch

Time R S Qt Q’t Qt+1 Q’t+1

1 1 0 0 0 1 1

2 1 0 1 1 0 1

R

S

Q

Q’

Timing in Sequential circuits –

Stabilization time of a latch

Time R S Qt Q’t Qt+1 Q’t+1

1 1 0 0 0 0 0

2 1 0 0 0 1 1

3 1 0 0 1 0 1

R

S

Q

Q’

Timing in Sequential circuits –

Stabilization time of a latch

Time R S Qt Q’t Qt+1 Q’t+1

1 0 1 0 1 1 0

R

S

Q

Q’

It takes time unit for the latch to stabilize

clock controlled latch

R

S

Q

Q’

CP

Cycle time

1-cycle time

0-cycle time

The Instability problem

Combinatorial circuit

Memory

CP thl of 1

1

Memory is updatable

outputinput

Solution latch is sensitive to the change in clock

CP

Memory is updatable

Timing in Sequential circuits –

Master-Slave Flip Flop

R

S

Q

Q’

CP

R

S

Q

Q’

CP

CP

1 2

Timing in Sequential circuits –

Master-Slave Flip Flop

R

S

Q

Q’

CP

R

S

Q

Q’

CP

CP

1 2

CP

Updating the FF

Timing in Sequential circuits –

Master-Slave Flip Flop

R

S

Q

Q’

CP

R

S

Q

Q’

CP

CP

1 2

CP

Stabilization of latch 1 and latch 2

Timing in Sequential circuits –

Edge triggered D-Flip Flop

CP

D

Q

Q’

Timing in Sequential circuits –

Edge triggered D-Flip Flop

CP

D

Q

Q’

Timing in Sequential circuits –

Edge triggered D-Flip FlopR

S

Q

Q’

R

S

Q

Q’

CP

D

Timing in Sequential circuits –

Edge triggered D-Flip Flop

R

S

Q

Q’

R

S

Q

Q’

CP

D

=0

=0 1

1

10

10

Maintain value

Stabilization before change of clock

0

Timing in Sequential circuits –

Edge triggered D-Flip Flop

R

S

Q

Q’

R

S

Q

Q’

CP

D

=1

=0 1

0

10

11

Set value to 0

Stabilization after change of clock

1

Timing in Sequential circuits –

Edge triggered D-Flip Flop

R

S

Q

Q’

R

S

Q

Q’

CP

D

=1

=1 1

0

10

11

Set value to 0

1

Input changed Output remains

the same

Timing in Sequential circuits –

Definitions

tsetup – time before the change of

clock that the input must not change

thold – time after the change of

clock that the input must not change

Timing in Sequential circuits –

Definitions

CP

90%tpC-Q

tcC-Q

FF output

tpC-Q – The time it takes the output to reach its legal value from the relevant change of clock

tcC-Q – The time that the output does not change after the relevant change of clock

Timing in Sequential circuits –

Constraints on the timing of the circuit

Flip Flop 1 Flip Flop 2

What should be the constraints on the timing characteristics of FF 1 and 2 To ensure that the circuit works properly?

Timing in Sequential circuits –

Constraints on the timing of the circuit

Flip Flop 1 Flip Flop 2

What should be the constraints on the timing characteristics of FF 1 and 2 To ensure that the circuit works properly?

tcC-Q,1 > thold,2

Timing in Sequential circuits –

Analyzing a circuitX1

X2D - FF

Updating the variables in the negative edge (decrease from 1 to 0)FF locks in positive edge (increase from 0 to 1).

1. What is the minimal cycle time (what are the durations of each phase)?2. What is the maximal delay of the circuit output?3. What are the conditions on the timing properties of the clock such that the

circuit will work properly?

1

2

Timing in Sequential circuits –

What is the minimal cycle time (what are the durations of each phase)?

Solution IUpdate Variables

Lock FF

Timing in Sequential circuits –

What is the minimal cycle time (what are the durations of each phase)?

Solution I

tsetuptpd(1)

tpC-Q

Timing in Sequential circuits –

What is the minimal cycle time (what are the durations of each phase)?

Solution II

tsetup

tpd(1)tpC-Q

Timing in Sequential circuits –

What is the maximal delay of the circuit output?

Solution:

tpd =

X1

X2D - FF

1

2

Timing in Sequential circuits –

What is the maximal delay of the circuit output?

Solution:

tpd = tpd(2)

X1

X2D - FF

1

2

The relevant clock change.The FF is already updatedhere

Timing in Sequential circuits –

What are the conditions on the timing properties of the clock such that the circuit will work properly?

Solution: X1

X2D - FF

Timing in Sequential circuits –

What are the conditions on the timing properties of the clock such that the circuit will work properly?

Solution: X1

X2D - FF

thold < tcd(1) + tcC-Q