Tiva C Series TM4C1290NCPDT Microcontroller Data Sheet ... · 1.3.10 PackagingandTemperature ......

Tiva TM4C1290NCPDT Microcontroller

DATA SHEET

Copyr ight 2007-2014Texas Instruments Incorporated

DS-TM4C1290NCPDT-15863.2743SPMS429B

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

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June 18, 20142Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 40About This Document .................................................................................................................... 43Audience .............................................................................................................................................. 43About This Manual ................................................................................................................................ 43Related Documents ............................................................................................................................... 43Documentation Conventions .................................................................................................................. 44

1 Architectural Overview .......................................................................................... 461.1 Tiva C Series Overview .............................................................................................. 461.2 TM4C1290NCPDT Microcontroller Overview .................................................................. 471.3 TM4C1290NCPDT Microcontroller Features ................................................................... 501.3.1 ARM Cortex-M4F Processor Core .................................................................................. 501.3.2 On-Chip Memory ........................................................................................................... 521.3.3 External Peripheral Interface ......................................................................................... 541.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 561.3.5 Serial Communications Peripherals ................................................................................ 561.3.6 System Integration ........................................................................................................ 611.3.7 Advanced Motion Control ............................................................................................... 681.3.8 Analog .......................................................................................................................... 701.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 711.3.10 Packaging and Temperature .......................................................................................... 721.4 TM4C1290NCPDT Microcontroller Hardware Details ....................................................... 721.5 Kits .............................................................................................................................. 721.6 Support Information ....................................................................................................... 73

2 The Cortex-M4F Processor ................................................................................... 742.1 Block Diagram .............................................................................................................. 752.2 Overview ...................................................................................................................... 762.2.1 System-Level Interface .................................................................................................. 762.2.2 Integrated Configurable Debug ...................................................................................... 762.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 772.2.4 Cortex-M4F System Component Details ......................................................................... 772.3 Programming Model ...................................................................................................... 782.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 782.3.2 Stacks .......................................................................................................................... 792.3.3 Register Map ................................................................................................................ 792.3.4 Register Descriptions .................................................................................................... 812.3.5 Exceptions and Interrupts .............................................................................................. 972.3.6 Data Types ................................................................................................................... 972.4 Memory Model .............................................................................................................. 972.4.1 Memory Regions, Types and Attributes ......................................................................... 1002.4.2 Memory System Ordering of Memory Accesses ............................................................ 1012.4.3 Behavior of Memory Accesses ..................................................................................... 1012.4.4 Software Ordering of Memory Accesses ....................................................................... 1012.4.5 Bit-Banding ................................................................................................................. 1032.4.6 Data Storage .............................................................................................................. 1052.4.7 Synchronization Primitives ........................................................................................... 106

3June 18, 2014Texas Instruments-Production Data


2.5 Exception Model ......................................................................................................... 1072.5.1 Exception States ......................................................................................................... 1082.5.2 Exception Types .......................................................................................................... 1082.5.3 Exception Handlers ..................................................................................................... 1132.5.4 Vector Table ................................................................................................................ 1132.5.5 Exception Priorities ...................................................................................................... 1142.5.6 Interrupt Priority Grouping ............................................................................................ 1142.5.7 Exception Entry and Return ......................................................................................... 1142.6 Fault Handling ............................................................................................................. 1172.6.1 Fault Types ................................................................................................................. 1182.6.2 Fault Escalation and Hard Faults .................................................................................. 1182.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1192.6.4 Lockup ....................................................................................................................... 1192.7 Power Management .................................................................................................... 1202.7.1 Entering Sleep Modes ................................................................................................. 1202.7.2 Wake Up from Sleep Mode .......................................................................................... 1202.8 Instruction Set Summary .............................................................................................. 121

3 Cortex-M4 Peripherals ......................................................................................... 1283.1 Functional Description ................................................................................................. 1283.1.1 System Timer (SysTick) ............................................................................................... 1293.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1303.1.3 System Control Block (SCB) ........................................................................................ 1313.1.4 Memory Protection Unit (MPU) ..................................................................................... 1313.1.5 Floating-Point Unit (FPU) ............................................................................................. 1363.2 Register Map .............................................................................................................. 1403.3 System Timer (SysTick) Register Descriptions .............................................................. 1433.4 NVIC Register Descriptions .......................................................................................... 1473.5 System Control Block (SCB) Register Descriptions ........................................................ 1573.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1863.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 195

4 JTAG Interface ...................................................................................................... 2014.1 Block Diagram ............................................................................................................ 2024.2 Signal Description ....................................................................................................... 2024.3 Functional Description ................................................................................................. 2034.3.1 JTAG Interface Pins ..................................................................................................... 2034.3.2 JTAG TAP Controller ................................................................................................... 2054.3.3 Shift Registers ............................................................................................................ 2064.3.4 Operational Considerations .......................................................................................... 2064.4 Initialization and Configuration ..................................................................................... 2094.5 Register Descriptions .................................................................................................. 2094.5.1 Instruction Register (IR) ............................................................................................... 2104.5.2 Data Registers ............................................................................................................ 211

5 System Control ..................................................................................................... 2145.1 Signal Description ....................................................................................................... 2145.2 Functional Description ................................................................................................. 2145.2.1 Device Identification .................................................................................................... 2145.2.2 Reset Control .............................................................................................................. 2155.2.3 Non-Maskable Interrupt ............................................................................................... 222


Table of Contents

5.2.4 Power Control ............................................................................................................. 2235.2.5 Clock Control .............................................................................................................. 2245.2.6 System Control ........................................................................................................... 2325.3 Initialization and Configuration ..................................................................................... 2395.4 Register Map .............................................................................................................. 2405.5 System Control Register Descriptions (System Control Offset) ....................................... 247

6 Processor Support and Exception Module ........................................................ 5006.1 Functional Description ................................................................................................. 5006.2 Register Map .............................................................................................................. 5006.3 Register Descriptions .................................................................................................. 500

7 Hibernation Module .............................................................................................. 5087.1 Block Diagram ............................................................................................................ 5107.2 Signal Description ....................................................................................................... 5107.3 Functional Description ................................................................................................. 5117.3.1 Register Access Timing ............................................................................................... 5127.3.2 Hibernation Clock Source ............................................................................................ 5127.3.3 System Implementation ............................................................................................... 5157.3.4 Battery Management ................................................................................................... 5167.3.5 Real-Time Clock .......................................................................................................... 5167.3.6 Tamper ....................................................................................................................... 5197.3.7 Battery-Backed Memory .............................................................................................. 5227.3.8 Power Control Using HIB ............................................................................................. 5227.3.9 Power Control Using VDD3ON Mode ........................................................................... 5237.3.10 Initiating Hibernate ...................................................................................................... 5237.3.11 Waking from Hibernate ................................................................................................ 5237.3.12 Arbitrary Power Removal ............................................................................................. 5247.3.13 Interrupts and Status ................................................................................................... 5257.4 Initialization and Configuration ..................................................................................... 5257.4.1 Initialization ................................................................................................................. 5257.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5267.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5267.4.4 External Wake-Up from Hibernation .............................................................................. 5277.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5287.4.6 Tamper Initialization ..................................................................................................... 5287.5 Register Map .............................................................................................................. 5287.6 Register Descriptions .................................................................................................. 530

8 Internal Memory ................................................................................................... 5778.1 Block Diagram ............................................................................................................ 5778.2 Functional Description ................................................................................................. 5798.2.1 SRAM ........................................................................................................................ 5798.2.2 ROM .......................................................................................................................... 5798.2.3 Flash Memory ............................................................................................................. 5818.2.4 EEPROM .................................................................................................................... 5928.2.5 Bus Matrix Memory Accesses ...................................................................................... 5988.3 Register Map .............................................................................................................. 5988.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6018.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6278.6 Memory Register Descriptions (System Control Offset) .................................................. 644



9 Micro Direct Memory Access (DMA) ................................................................ 6559.1 Block Diagram ............................................................................................................ 6569.2 Functional Description ................................................................................................. 6569.2.1 Channel Assignments .................................................................................................. 6579.2.2 Priority ........................................................................................................................ 6589.2.3 Arbitration Size ............................................................................................................ 6599.2.4 Request Types ............................................................................................................ 6599.2.5 Channel Configuration ................................................................................................. 6609.2.6 Transfer Modes ........................................................................................................... 6629.2.7 Transfer Size and Increment ........................................................................................ 6709.2.8 Peripheral Interface ..................................................................................................... 6709.2.9 Software Request ........................................................................................................ 6719.2.10 Interrupts and Errors .................................................................................................... 6719.3 Initialization and Configuration ..................................................................................... 6719.3.1 Module Initialization ..................................................................................................... 6719.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6729.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6739.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6759.3.5 Configuring Channel Assignments ................................................................................ 6789.4 Register Map .............................................................................................................. 6789.5 DMA Channel Control Structure ................................................................................. 6799.6 DMA Register Descriptions ........................................................................................ 686

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 71910.1 Signal Description ....................................................................................................... 72010.2 Pad Capabilities .......................................................................................................... 72310.3 Functional Description ................................................................................................. 72410.3.1 Data Control ............................................................................................................... 72610.3.2 Interrupt Control .......................................................................................................... 72810.3.3 Mode Control .............................................................................................................. 72910.3.4 Commit Control ........................................................................................................... 73010.3.5 Pad Control ................................................................................................................. 73010.3.6 Identification ............................................................................................................... 73110.4 Initialization and Configuration ..................................................................................... 73110.5 Register Map .............................................................................................................. 73310.6 Register Descriptions .................................................................................................. 736

11 External Peripheral Interface (EPI) ..................................................................... 79311.1 EPI Block Diagram ...................................................................................................... 79411.2 Signal Description ....................................................................................................... 79511.3 Functional Description ................................................................................................. 79611.3.1 Master Access to EPI .................................................................................................. 79711.3.2 Non-Blocking Reads .................................................................................................... 79711.3.3 DMA Operation ........................................................................................................... 79811.4 Initialization and Configuration ..................................................................................... 79911.4.1 EPI Interface Options .................................................................................................. 80011.4.2 SDRAM Mode ............................................................................................................. 80011.4.3 Host Bus Mode ........................................................................................................... 80411.4.4 General-Purpose Mode ............................................................................................... 82511.5 Register Map .............................................................................................................. 832


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11.6 Register Descriptions .................................................................................................. 834

12 Cyclical Redundancy Check (CRC) .................................................................... 92412.1 Functional Description ................................................................................................. 92412.1.1 CRC Support .............................................................................................................. 92412.2 Initialization and Configuration ..................................................................................... 92612.2.1 CRC Initialization and Configuration ............................................................................. 92612.3 Register Map .............................................................................................................. 92712.4 CRC Module Register Descriptions .............................................................................. 927

13 General-Purpose Timers ...................................................................................... 93313.1 Block Diagram ............................................................................................................ 93413.2 Signal Description ....................................................................................................... 93513.3 Functional Description ................................................................................................. 93613.3.1 GPTM Reset Conditions .............................................................................................. 93713.3.2 Timer Clock Source ..................................................................................................... 93713.3.3 Timer Modes ............................................................................................................... 93713.3.4 Wait-for-Trigger Mode .................................................................................................. 94613.3.5 Synchronizing GP Timer Blocks ................................................................................... 94713.3.6 DMA Operation ........................................................................................................... 94813.3.7 ADC Operation ............................................................................................................ 94813.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 94813.4 Initialization and Configuration ..................................................................................... 94913.4.1 One-Shot/Periodic Timer Mode .................................................................................... 94913.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 95013.4.3 Input Edge-Count Mode ............................................................................................... 95013.4.4 Input Edge Time Mode ................................................................................................. 95113.4.5 PWM Mode ................................................................................................................. 95113.5 Register Map .............................................................................................................. 95213.6 Register Descriptions .................................................................................................. 953

14 Watchdog Timers ............................................................................................... 100614.1 Block Diagram ........................................................................................................... 100714.2 Functional Description ............................................................................................... 100714.2.1 Register Access Timing ............................................................................................. 100814.3 Initialization and Configuration .................................................................................... 100814.4 Register Map ............................................................................................................ 100814.5 Register Descriptions ................................................................................................. 1009

15 Analog-to-Digital Converter (ADC) ................................................................... 103115.1 Block Diagram ........................................................................................................... 103215.2 Signal Description ..................................................................................................... 103315.3 Functional Description ............................................................................................... 103415.3.1 Sample Sequencers .................................................................................................. 103415.3.2 Module Control .......................................................................................................... 103515.3.3 Hardware Sample Averaging Circuit ........................................................................... 104015.3.4 Analog-to-Digital Converter ........................................................................................ 104115.3.5 Differential Sampling .................................................................................................. 104315.3.6 Internal Temperature Sensor ...................................................................................... 104515.3.7 Digital Comparator Unit .............................................................................................. 104615.4 Initialization and Configuration .................................................................................... 1050



15.4.1 Module Initialization ................................................................................................... 105015.4.2 Sample Sequencer Configuration ............................................................................... 105115.5 Register Map ............................................................................................................ 105115.6 Register Descriptions ................................................................................................. 1054

16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 113916.1 Block Diagram ........................................................................................................... 114016.2 Signal Description ..................................................................................................... 114016.3 Functional Description ............................................................................................... 114216.3.1 Transmit/Receive Logic .............................................................................................. 114216.3.2 Baud-Rate Generation ............................................................................................... 114316.3.3 Data Transmission ..................................................................................................... 114416.3.4 Serial IR (SIR) ........................................................................................................... 114416.3.5 ISO 7816 Support ...................................................................................................... 114516.3.6 Modem Handshake Support ....................................................................................... 114616.3.7 9-Bit UART Mode ...................................................................................................... 114716.3.8 FIFO Operation ......................................................................................................... 114716.3.9 Interrupts .................................................................................................................. 114816.3.10 Loopback Operation .................................................................................................. 114916.3.11 DMA Operation ......................................................................................................... 114916.4 Initialization and Configuration .................................................................................... 115016.5 Register Map ............................................................................................................ 115116.6 Register Descriptions ................................................................................................. 1152

17 Quad Synchronous Serial Interface (QSSI) ..................................................... 120417.1 Block Diagram ........................................................................................................... 120417.2 Signal Description ..................................................................................................... 120517.3 Functional Description ............................................................................................... 120717.3.1 Bit Rate Generation ................................................................................................... 120717.3.2 FIFO Operation ......................................................................................................... 120717.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 120817.3.4 SSInFSS Function ..................................................................................................... 120917.3.5 High Speed Clock Operation ...................................................................................... 121017.3.6 Interrupts .................................................................................................................. 121017.3.7 Frame Formats ......................................................................................................... 121117.3.8 DMA Operation ......................................................................................................... 121817.4 Initialization and Configuration .................................................................................... 121817.4.1 Enhanced Mode Configuration ................................................................................... 122017.5 Register Map ............................................................................................................ 122117.6 Register Descriptions ................................................................................................. 1222

18 Inter-Integrated Circuit (I2C) Interface .............................................................. 125318.1 Block Diagram ........................................................................................................... 125418.2 Signal Description ..................................................................................................... 125518.3 Functional Description ............................................................................................... 125618.3.1 I2C Bus Functional Overview ...................................................................................... 125618.3.2 Available Speed Modes ............................................................................................. 126218.3.3 Interrupts .................................................................................................................. 126418.3.4 Loopback Operation .................................................................................................. 126518.3.5 FIFO and DMA Operation ........................................................................................ 126518.3.6 Command Sequence Flow Charts .............................................................................. 1267


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18.4 Initialization and Configuration .................................................................................... 127518.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 127518.4.2 Configure the I2C Master to High Speed Mode ............................................................ 127618.5 Register Map ............................................................................................................ 127718.6 Register Descriptions (I2C Master) .............................................................................. 127918.7 Register Descriptions (I2C Slave) ............................................................................... 130818.8 Register Descriptions (I2C Status and Control) ............................................................ 1325

19 Controller Area Network (CAN) Module ........................................................... 133419.1 Block Diagram ........................................................................................................... 133519.2 Signal Description ..................................................................................................... 133519.3 Functional Description ............................................................................................... 133619.3.1 Initialization ............................................................................................................... 133719.3.2 Operation .................................................................................................................. 133719.3.3 Transmitting Message Objects ................................................................................... 133819.3.4 Configuring a Transmit Message Object ...................................................................... 133919.3.5 Updating a Transmit Message Object ......................................................................... 134019.3.6 Accepting Received Message Objects ........................................................................ 134019.3.7 Receiving a Data Frame ............................................................................................ 134119.3.8 Receiving a Remote Frame ........................................................................................ 134119.3.9 Receive/Transmit Priority ........................................................................................... 134119.3.10 Configuring a Receive Message Object ...................................................................... 134219.3.11 Handling of Received Message Objects ...................................................................... 134319.3.12 Handling of Interrupts ................................................................................................ 134519.3.13 Test Mode ................................................................................................................. 134619.3.14 Bit Timing Configuration Error Considerations ............................................................. 134819.3.15 Bit Time and Bit Rate ................................................................................................. 134819.3.16 Calculating the Bit Timing Parameters ........................................................................ 135019.4 Register Map ............................................................................................................ 135319.5 CAN Register Descriptions ......................................................................................... 1354

20 Universal Serial Bus (USB) Controller ............................................................. 138520.1 Block Diagram ........................................................................................................... 138620.2 Signal Description ..................................................................................................... 138620.3 Register Map ............................................................................................................ 1387

21 Analog Comparators .......................................................................................... 139421.1 Block Diagram ........................................................................................................... 139521.2 Signal Description ..................................................................................................... 139521.3 Functional Description ............................................................................................... 139621.3.1 Internal Reference Programming ................................................................................ 139721.4 Initialization and Configuration .................................................................................... 139921.5 Register Map ............................................................................................................ 140021.6 Register Descriptions ................................................................................................. 1400

22 Pulse Width Modulator (PWM) .......................................................................... 141022.1 Block Diagram ........................................................................................................... 141122.2 Signal Description ..................................................................................................... 141322.3 Functional Description ............................................................................................... 141322.3.1 Clock Configuration ................................................................................................... 141322.3.2 PWM Timer ............................................................................................................... 1413



22.3.3 PWM Comparators .................................................................................................... 141422.3.4 PWM Signal Generator .............................................................................................. 141522.3.5 Dead-Band Generator ............................................................................................... 141622.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 141622.3.7 Synchronization Methods .......................................................................................... 141722.3.8 Fault Conditions ........................................................................................................ 141822.3.9 Output Control Block .................................................................................................. 141922.4 Initialization and Configuration .................................................................................... 141922.5 Register Map ............................................................................................................ 142022.6 Register Descriptions ................................................................................................. 1423

23 Quadrature Encoder Interface (QEI) ................................................................. 148923.1 Block Diagram ........................................................................................................... 148923.2 Signal Description ..................................................................................................... 149123.3 Functional Description ............................................................................................... 149123.4 Initialization and Configuration .................................................................................... 149423.5 Register Map ............................................................................................................ 149423.6 Register Descriptions ................................................................................................. 1495

24 Pin Diagram ........................................................................................................ 151225 Signal Tables ...................................................................................................... 151325.1 Signals by Pin Number .............................................................................................. 151425.2 Signals by Signal Name ............................................................................................. 152625.3 Signals by Function, Except for GPIO ......................................................................... 153825.4 GPIO Pins and Alternate Functions ............................................................................ 155025.5 Possible Pin Assignments for Alternate Functions ....................................................... 155425.6 Connections for Unused Signals ................................................................................. 1559

26 Electrical Characteristics .................................................................................. 156126.1 Maximum Ratings ...................................................................................................... 156126.2 Operating Characteristics ........................................................................................... 156226.3 Recommended Operating Conditions ......................................................................... 156326.3.1 DC Operating Conditions ........................................................................................... 156326.3.2 Recommended GPIO Operating Characteristics .......................................................... 156326.4 Load Conditions ........................................................................................................ 156626.5 JTAG and Boundary Scan .......................................................................................... 156726.6 Power and Brown-Out ............................................................................................... 156926.6.1 VDDA Levels .............................................................................................................. 156926.6.2 VDD Levels ................................................................................................................ 157026.6.3 VDDC Levels .............................................................................................................. 157126.6.4 Response ................................................................................................................. 157226.7 Reset ........................................................................................................................ 157426.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 157726.9 Clocks ...................................................................................................................... 157826.9.1 PLL Specifications ..................................................................................................... 157826.9.2 PIOSC Specifications ................................................................................................ 158026.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 158026.9.4 Hibernation Clock Source Specifications ..................................................................... 158026.9.5 Main Oscillator Specifications ..................................................................................... 158126.9.6 System Clock Specification with ADC Operation .......................................................... 1585


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26.9.7 System Clock Specification with USB Operation .......................................................... 158526.10 Sleep Modes ............................................................................................................. 158626.11 Hibernation Module ................................................................................................... 158826.12 Flash Memory ........................................................................................................... 159026.13 EEPROM .................................................................................................................. 159126.14 Input/Output Pin Characteristics ................................................................................. 159226.14.1 Types of I/O Pins and ESD Protection ......................................................................... 159426.15 External Peripheral Interface (EPI) .............................................................................. 159626.16 Analog-to-Digital Converter (ADC) .............................................................................. 160426.17 Synchronous Serial Interface (SSI) ............................................................................. 161026.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 161326.19 Universal Serial Bus (USB) Controller ......................................................................... 161426.20 Analog Comparator ................................................................................................... 161626.21 Pulse-Width Modulator (PWM) ................................................................................... 161826.22 Current Consumption ................................................................................................ 1619

A Package Information .......................................................................................... 1623A.1 Orderable Devices ..................................................................................................... 1623A.2 Device Nomenclature ................................................................................................ 1623A.3 Device Markings ........................................................................................................ 1623A.4 Packaging Diagram ................................................................................................... 1625



List of FiguresFigure 1-1. Tiva TM4C1290NCPDT Microcontroller High-Level Block Diagram ....................... 49Figure 2-1. CPU Block Diagram ............................................................................................. 76Figure 2-2. TPIU Block Diagram ............................................................................................ 77Figure 2-3. Cortex-M4F Register Set ...................................................................................... 80Figure 2-4. Bit-Band Mapping .............................................................................................. 105Figure 2-5. Data Storage ..................................................................................................... 106Figure 2-6. Vector Table ...................................................................................................... 113Figure 2-7. Exception Stack Frame ...................................................................................... 116Figure 3-1. SRD Use Example ............................................................................................. 134Figure 3-2. FPU Register Bank ............................................................................................ 137Figure 4-1. JTAG Module Block Diagram .............................................................................. 202Figure 4-2. Test Access Port State Machine ......................................................................... 206Figure 4-3. IDCODE Register Format ................................................................................... 212Figure 4-4. BYPASS Register Format ................................................................................... 212Figure 4-5. Boundary Scan Register Format ......................................................................... 212Figure 5-1. Basic RST Configuration .................................................................................... 218Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 218Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 218Figure 5-4. Power Architecture ............................................................................................ 223Figure 5-5. Main Clock Tree ................................................................................................ 227Figure 5-6. Module Clock Selection ...................................................................................... 235Figure 7-1. Hibernation Module Block Diagram ..................................................................... 510Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 514Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 514Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 515Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 519Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 519Figure 7-7. Tamper Block Diagram ....................................................................................... 519Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 520Figure 8-1. Internal Memory Block Diagram .......................................................................... 578Figure 8-2. Flash Memory Configuration ............................................................................... 582Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 583Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 583Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 584Figure 8-6. Prefetch Fills from Flash ..................................................................................... 585Figure 8-7. Mirror Mode Function ......................................................................................... 586Figure 9-1. DMA Block Diagram ......................................................................................... 656Figure 9-2. Example of Ping-Pong DMA Transaction ........................................................... 663Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 665Figure 9-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 666Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 668Figure 9-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 669Figure 10-1. Digital I/O Pads ................................................................................................. 725Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 726Figure 10-3. GPIODATA Write Example ................................................................................. 727


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Figure 10-4. GPIODATA Read Example ................................................................................. 727Figure 11-1. EPI Block Diagram ............................................................................................. 795Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 802Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 803Figure 11-4. SDRAM Write Cycle ........................................................................................... 804Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 814Figure 11-6. iRDY Signal Connection ..................................................................................... 814Figure 11-7. PSRAM Burst Read ........................................................................................... 817Figure 11-8. PSRAM Burst Write ........................................................................................... 817Figure 11-9. Read Delay During Refresh Event ...................................................................... 818Figure 11-10. Write Delay During Refresh Event ....................................................................... 819Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 820Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 823Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 823Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 824Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 824Figure 11-16. Continuous Read Mode Accesses ...................................................................... 824Figure 11-17. Write Followed by Read to External FIFO ............................................................ 825Figure 11-18. Two-Entry FIFO ................................................................................................. 825Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 828Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 829Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 829Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 830Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 830Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 830Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 830Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 831Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 831Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 831Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 832Figure 13-1. GPTM Module Block Diagram ............................................................................ 934Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 942Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 943Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 945Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 945Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 946Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 946Figure 13-8. Timer Daisy Chain ............................................................................................. 947Figure 14-1. WDT Module Block Diagram ............................................................................. 1007Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1032Figure 15-2. ADC Module Block Diagram ............................................................................. 1033Figure 15-3. ADC Sample Phases ....................................................................................... 1038Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1038Figure 15-5. Skewed Sampling ............................................................................................ 1039Figure 15-6. Sample Averaging Example .............................................................................. 1041Figure 15-7. ADC Input Equivalency .................................................................................... 1042



Figure 15-8. ADC Voltage Reference ................................................................................... 1042Figure 15-9. ADC Conversion Result ................................................................................... 1043Figure 15-10. Differential Voltage Representation ................................................................... 1045Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1046Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1048Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1049Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1050Figure 16-1. UART Module Block Diagram ........................................................................... 1140Figure 16-2. UART Character Frame .................................................................................... 1143Figure 16-3. IrDA Data Modulation ....................................................................................... 1145Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1205Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1212Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1213Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1214Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1214Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1215Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1216Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1216Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1217Figure 18-1. I2C Block Diagram ........................................................................................... 1254Figure 18-2. I2C Bus Configuration ....................................................................................... 1256Figure 18-3. START and STOP Conditions ........................................................................... 1257Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1257Figure 18-5. R/S Bit in First Byte .......................................................................................... 1258Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1258Figure 18-7. High-Speed Data Format .................................................................................. 1264Figure 18-8. Master Single TRANSMIT ................................................................................ 1268Figure 18-9. Master Single RECEIVE ................................................................................... 1269Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1270Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1271Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1272Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1273Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1274Figure 18-15. Slave Command Sequence .............................................................................. 1275Figure 19-1. CAN Controller Block Diagram .......................................................................... 1335Figure 19-2. CAN Data/Remote Frame ................................................................................. 1336Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1345Figure 19-4. CAN Bit Time ................................................................................................... 1349Figure 20-1. USB Module Block Diagram ............................................................................. 1386Figure 21-1. Analog Comparator Module Block Diagram ....................................................... 1395Figure 21-2. Structure of Comparator Unit ............................................................................ 1396Figure 21-3. Comparator Internal Reference Structure .......................................................... 1397Figure 22-1. PWM Module Diagram ..................................................................................... 1412Figure 22-2. PWM Generator Block Diagram ........................................................................ 1412Figure 22-3. PWM Count-Down Mode .................................................................................. 1415Figure 22-4. PWM Count-Up/Down Mode ............................................................................. 1415Figure 22-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1416Figure 22-6. PWM Dead-Band Generator ............................................................................. 1416


Table of Contents

Figure 23-1. QEI Block Diagram .......................................................................................... 1490Figure 23-2. QEI Input Signal Logic ...................................................................................... 1491Figure 23-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1493Figure 24-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1512Figure 26-1. Load Conditions ............................................................................................... 1566Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1568Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1568Figure 26-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1570Figure 26-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1571Figure 26-6. POK Assertion vs VDDC ................................................................................... 1572Figure 26-7. POR-BOR VDD Glitch Response ....................................................................... 1572Figure 26-8. POR-BOR VDD Droop Response ...................................................................... 1573Figure 26-9. Digital Power-On Reset Timing ......................................................................... 1574Figure 26-10. Brown-Out Reset Timing .................................................................................. 1575Figure 26-11. External Reset Timing (RST) ............................................................................ 1575Figure 26-12. Software Reset Timing ..................................................................................... 1575Figure 26-13. Watchdog Reset Timing ................................................................................... 1575Figure 26-14. MOSC Failure Reset Timing ............................................................................. 1576Figure 26-15. Hibernation Module Timing ............................................................................... 1589Figure 26-16. ESD Protection ................................................................................................ 1594Figure 26-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1595Figure 26-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1597Figure 26-19. SDRAM Read Timing ....................................................................................... 1597Figure 26-20. SDRAM Write Timing ....................................................................................... 1598Figure 26-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1599Figure 26-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1599Figure 26-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1600Figure 26-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1600Figure 26-25. General-Purpose Mode Read and Write Timing ................................................. 1601Figure 26-26. PSRAM Single Burst Read ............................................................................... 1602Figure 26-27. PSRAM Single Burst Write ............................................................................... 1603Figure 26-28. ADC External Reference Filtering ..................................................................... 1609Figure 26-29. ADC Input Equivalency .................................................................................... 1609Figure 26-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1611Figure 26-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1611Figure 26-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1612Figure 26-33. I2C Timing ....................................................................................................... 1613Figure 26-34. ULPI Interface Timing Diagram ......................................................................... 1615Figure A-1. Key to Part Numbers ........................................................................................ 1623Figure A-2. TM4C1290NCPDT 128-Pin TQFP Package Diagram ......................................... 1625



List of TablesTable 1. Revision History .................................................................................................. 40Table 2. Documentation Conventions ................................................................................ 44Table 1-1. TM4C1290NCPDT Microcontroller Features .......................................................... 47Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 79Table 2-2. Processor Register Map ....................................................................................... 80Table 2-3. PSR Register Combinations ................................................................................. 86Table 2-4. Memory Map ....................................................................................................... 97Table 2-5. Memory Access Behavior ................................................................................... 101Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 103Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 103Table 2-8. Exception Types ................................................................................................ 109Table 2-9. Interrupts .......................................................................................................... 110Table 2-10. Exception Return Behavior ................................................................................. 117Table 2-11. Faults ............................................................................................................... 118Table 2-12. Fault Status and Fault Address Registers ............................................................ 119Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 121Table 3-1. Core Peripheral Register Regions ....................................................................... 128Table 3-2. Memory Attributes Summary .............................................................................. 132Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 134Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 135Table 3-5. AP Bit Field Encoding ........................................................................................ 135Table 3-6. Memory Region Attributes for Tiva C Series Microcontrollers ............................. 136Table 3-7. QNaN and SNaN Handling ................................................................................. 139Table 3-8. Peripherals Register Map ................................................................................... 140Table 3-9. Interrupt Priority Levels ...................................................................................... 165Table 3-10. Example SIZE Field Values ................................................................................ 193Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 202Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 204Table 4-3. JTAG Instruction Register Commands ................................................................. 210Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 214Table 5-2. Reset Sources ................................................................................................... 215Table 5-3. Clock Source Options ........................................................................................ 225Table 5-4. Clock Source State Following POR ..................................................................... 225Table 5-5. System Clock Frequency ................................................................................... 229Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 231Table 5-7. Actual PLL Frequency ........................................................................................ 231Table 5-8. Peripheral Memory Power Control ...................................................................... 237Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 237Table 5-10. MOSC Configurations ........................................................................................ 240Table 5-11. System Control Register Map ............................................................................. 241Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 270Table 5-13. MOSC Configurations ........................................................................................ 274Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 293Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 296Table 5-16. Module Power Control ........................................................................................ 434Table 5-17. Module Power Control ........................................................................................ 436


Table of Contents

Table 5-18. Module Power Control ........................................................................................ 439Table 5-19. Module Power Control ........................................................................................ 444Table 5-20. Module Power Control ........................................................................................ 446Table 5-21. Module Power Control ........................................................................................ 448Table 5-22. Module Power Control ........................................................................................ 450Table 5-23. Module Power Control ........................................................................................ 453Table 5-24. Module Power Control ........................................................................................ 455Table 5-25. Module Power Control ........................................................................................ 459Table 5-26. Module Power Control ........................................................................................ 461Table 5-27. Module Power Control ........................................................................................ 463Table 5-28. Module Power Control ........................................................................................ 465Table 5-29. Module Power Control ........................................................................................ 467Table 5-30. Module Power Control ........................................................................................ 469Table 5-31. Module Power Control ........................................................................................ 471Table 5-32. Module Power Control ........................................................................................ 473Table 6-1. System Exception Register Map ......................................................................... 500Table 7-1. Hibernate Signals (128TQFP) ............................................................................. 511Table 7-2. HIB Clock Source Configurations ........................................................................ 512Table 7-3. Hibernation Module Register Map ....................................................................... 529Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 582Table 8-2. Flash Memory Protection Policy Combinations .................................................... 587Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 591Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 594Table 8-5. Master Memory Access Availability ..................................................................... 598Table 8-6. Flash Register Map ............................................................................................ 599Table 9-1. DMA Channel Assignments .............................................................................. 657Table 9-2. Request Type Support ....................................................................................... 659Table 9-3. Control Structure Memory Map ........................................................................... 661Table 9-4. Channel Control Structure .................................................................................. 661Table 9-5. DMA Read Example: 8-Bit Peripheral ................................................................ 670Table 9-6. DMA Interrupt Assignments .............................................................................. 671Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 672Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 673Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 674Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 674Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 676Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 676Table 9-13. DMA Register Map .......................................................................................... 678Table 10-1. GPIO Pins With Special Considerations .............................................................. 720Table 10-2. GPIO Pins and Alternate Functions (128TQFP) ................................................... 720Table 10-3. GPIO Drive Strength Options .............................................................................. 731Table 10-4. GPIO Pad Configuration Examples ..................................................................... 732Table 10-5. GPIO Interrupt Configuration Example ................................................................ 733Table 10-6. GPIO Pins With Special Considerations .............................................................. 734Table 10-7. GPIO Register Map ........................................................................................... 735Table 10-8. GPIO Pins With Special Considerations .............................................................. 748Table 10-9. GPIO Pins With Special Considerations .............................................................. 754



Table 10-10. GPIO Pins With Special Considerations .............................................................. 756Table 10-11. GPIO Pins With Special Considerations .............................................................. 759Table 10-12. GPIO Pins With Special Considerations .............................................................. 765Table 10-13. GPIO Drive Strength Options .............................................................................. 778Table 11-1. External Peripheral Interface Signals (128TQFP) ................................................. 795Table 11-2. EPI Interface Options ......................................................................................... 800Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 801Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 805Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 806Table 11-6. Chip Select Configuration Register Assignment ................................................... 807Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 807Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 809Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 811Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 816Table 11-11. Data Phase Wait State Programming .................................................................. 821Table 11-12. EPI General-Purpose Signal Connections ........................................................... 827Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 832Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 858Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 864Table 12-1. Endian Configuration ......................................................................................... 925Table 12-2. Endian Configuration with Bit Reversal ................................................................ 925Table 12-3. CCM Register Map ............................................................................................ 927Table 13-1. Available CCP Pins ............................................................................................ 934Table 13-2. General-Purpose Timers Signals (128TQFP) ....................................................... 935Table 13-3. General-Purpose Timer Capabilities .................................................................... 936Table 13-4. Counter Values When the Timer is Enabled in Periodic

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