The F1958 is part of IDT’s Glitch-FreeTM family of DSAs optimized for the demanding requirements of Base Station (BTS) radio cards and numerous other applications. This device is offered in a compact 4mm x 4mm 24-pin package with 50Ω input and output impedance for ease of integration into the radio or RF system.
The F1958 offers very high reliability due to its construction from a monolithic silicon die in a QFN package. The insertion loss is very low with minimal distortion. Additionally, the device is designed to have extremely accurate attenuation levels. These accurate attenuation levels improve system SNR and/or ACLR by ensuring system gain is as close to the targeted level as possible. In addition, the very fast settling time in parallel mode is ideal for fast switching systems. Finally, the device uses our Glitch-FreeTM technology in contrast to competing DSAs.
Competitive Advantage
Lowest insertion loss for best SNR
Glitch-FreeTM technology to protect power amplifiers or ADC during transitions between attenuation states
Extremely accurate attenuation levels
Ultra-low distortion
MSL1 and 2000 V HBM ESD
Typical Applications
3G/4G/4G+ Base Station Systems
Distributed Antenna Systems, DAS
Remote Radio Heads
Active Antenna Systems, AAS Broadband Satellite Equipment
Figure 2. Pin Assignments for 4mm x 4mm x 0.75mm TQFN Package – Top View
D0
VMODE
GND
GND
Decoder
EPAD
RF1
VDD
1 DATA
LE
GND
GND
RF2
CLK
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
D1
D3
D4
D6
D5
D2
2
3
4
5
6
7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SPIB
I
A
S
Pin Descriptions
Table 1. Pin Descriptions
Number Name Description
1 D0 Parallel control pin – 0.25dB. Pull high for attenuation.
2 VDD Power supply input. Bypass to ground with capacitors as close as possible to pin.
3 VMODE Parallel or serial programming mode pin. Leave open or logic LOW for parallel mode. Logic HIGH for serial mode.
4, 6 - 13, 15 GND Internally grounded. These pins must be grounded as close to the device as possible.
5 RF1 RF Port 1. Can be used as either the input or output RF (bi-directional). Port must be at 0V DC. An external AC coupling capacitor must be used if there is a DC voltage present.
14 RF2 RF Port 2. Can be used as either the input or output RF (bi-directional). Port must be at 0V DC. An external AC coupling capacitor must be used if there is a DC voltage present.
16 LE Serial latch enable.
17 CLK Serial clock input.
18 DATA Serial data input.
19 D6 Parallel control pin – 16dB. Pull HIGH for attenuation. [a]
20 D5 Parallel control pin – 8dB. Pull HIGH for attenuation. [a]
21 D4 Parallel control pin – 4dB. Pull HIGH for attenuation. [a]
22 D3 Parallel control pin – 2dB. Pull HIGH for attenuation. [a]
23 D2 Parallel control pin – 1dB. Pull HIGH for attenuation. [a]
24 D1 Parallel control pin – 0.5dB. Pull HIGH for attenuation. [a]
– EPAD Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance.
[a] There is a 500kΩ pull-down resistor to ground.
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the F1958 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Symbol Minimum Maximum Units
Power Supply Voltage VDD -0.3 5.8 V
VMODE, DATA, CLK, LE, D[6:0] VCTRL -0.3 Lower of
(VDD+0.25, 5.8) V
RF1, RF2 VRF -0.3 0.3 V
Maximum RF Input Power to RF1 or RF2 (> 100 MHz) PMAX +34 dBm
Specifications apply at VDD = 3.3V, TEP = 25°C, fRF = 2GHz, LSB = 0.25dB steps and Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111].
Parameter Symbol Condition Minimum Typical Maximum Units
Logic Input HIGH VIH All logic pins 2.6 [a] 5.5 V
Logic Input LOW VIL All logic pins 0 1 V
Logic Current IIH, IIL -15 +15 µA
DC Current IDD VDD = 3.3V 250 400
µA VDD = 5.5V 310
Attenuation Range No missing codes 31.75 dB
Minimum Gain Step for Monotonicity
LSB
fRF < 4.0GHz 0.25
dB fRF < 6.0GHz 0.50
fRF < 8.0GHz 1.00
DSA Settling Time [b] tSET
Max to min attenuation to settle to within 0.5dB of final value
1.2
µs Min to max attenuation to settle to within 0.5dB of final value
2.0
Maximum Video Feed-Through VIDFT Measured with 10ns rise time, 0V to 3.3V control pulse
10 mVpp
Maximum Spurious Level on any RF Port [c]
SPURMAX Unused RF ports terminated into 50Ω
-118 dBm
Serial Clock Speed fCLK 10 MHz
Parallel to Serial Setup tPS 100 ns
Serial Data Hold Time tH 10 ns
LE Delay Time from final serial clock rising edge
10 ns
Maximum Switch Rate SWRATE 25 kHz
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization.
[b] Speeds are measured after SPI programming is completed (data latched with LE = LOW to HIGH transition). [c] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
Specifications apply at VDD = 3.3V, TEP = 25°C, fRF = 2GHz, LSB = 0.25dB steps and Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111].
Parameter Symbol Condition Minimum Typical Maximum Units
Insertion Loss IL
1MHz ≤ fRF ≤ 1GHz 1.1
dB
1GHz < fRF ≤ 2GHz 1.3 1.8 [a]
2GHz < fRF ≤ 3GHz 1.5
3GHz < fRF ≤ 4GHz 1.6
4GHz < fRF ≤ 5GHz 1.9
5GHz < fRF ≤ 6GHz 2.6
Relative Phase Between the Minimum and Maximum Attenuation
Φ∆
fRF = 1GHz 12
deg fRF = 2GHz 25
fRF = 4GHz 50
fRF = 6GHz 70
Step Error DNL Maximum error between any two adjacent attenuation levels
0.15 0.28 dB
Absolute Attenuation Error INL
Max. error for state 19.75dB, fRF = 2000MHz
-0.4 +0.5
dB Max. error, over all states fRF = 2000MHz
-0.8 -0.25 +0.08
+0.5
RF1 Port Return Loss RL1
1MHz ≤ fRF ≤ 2GHz 20
dB 2GHz < fRF ≤ 4GHz 17
4GHz < fRF ≤ 6GHz 13
RF2 Port Return Loss RL2
1MHz ≤ fRF ≤ 2GHz 20
dB 2GHz < fRF ≤ 4GHz 16
4GHz < fRF ≤ 6GHz 12
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization.
Specifications apply at VDD = 3.3V, TEP = 25°C, fRF = 2GHz, LSB = 0.25dB steps and Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111].
Parameter Symbol Condition Minimum Typical Maximum Units
Input IP3 IIP3
PIN = +19dBm per tone 50MHz tone separation
Attn = 0.00dB 64
dBm Attn = 15.75dB 64
Attn = 31.75dB 64
PIN = +16dBm per tone 1MHz tone separation
fRF = 0.7GHz 60 [a] 63.3
dBm fRF = 1.8GHz 60 63.7
fRF = 2.2GHz 60 63.4
fRF = 2.6GHz 60 63.7
Input 0.1dB Compression [b] IP0.1dB 35 dBm
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization.
[b] The input 0.1dB compression point is a linearity figure of merit. Refer to the Recommended Operating Conditions section and Figure 3 for the maximum operating power levels.
3.00 V / -40 C 3.30 V / -40 C 5.00 V / -40 C 5.25 V / -40 C3.00 V / +25 C 3.30 V / +25 C 5.00 V / +25 C 5.25 V / +25 C3.00 V / +105 C 3.30 V / +105 C 5.00 V / +105 C 5.25 V / +105 C
The F1958 can be programmed using either the parallel or the serial mode, which is selectable via VMODE (pin 3). The serial mode is selected by pulling VMODE to a logic HIGH, and the parallel mode is selected by floating VMODE or setting it to logic LOW.
Serial Mode
F1958 Serial Mode is selected by pulling VMODE to a logic HIGH. The serial interface uses a 8-bit word with only 7 bits used. The serial word is shifted in LSB (D0) first. When serial programming is used, all the parallel control input pins (1, 19 - 24) must be grounded.
In the Serial Mode, the F1958 is programmed via the serial port on the rising edge of Latch Enable (LE). It is required that LE be kept logic LOW until all data bits are clocked into the shift register. The F1958 will change attenuation state after the data word is latched into the active register. Refer to Figure 33.
Table 10. SPI Timing Diagram Values for the Serial Mode
Parameter Symbol Test Condition Min Typical Max Units
CLK Frequency fC 25 MHz
CLK HIGH Duration Time tCH 20 ns
CLK LOW Duration Time tCL 20 ns
DATA to CLK Setup Time tS 10 ns
CLK Period [a] tP 40 ns
CLK to Data Hold Time tH 10 ns
Final CLK Rising Edge to LE Rising Edge tCLS 10 ns
LE to CLK Setup Time tLS 10 ns
LE Trigger Pulse Width tL 10 ns
LE Trigger to CLK Setup Time [b] tLC 10 ns
[a] (tCH + tCL) ≥ 1/fC. [b] Once all desired data has been clocked in, LE must transition from LOW to HIGH after the minimum setup time tLC and before
any further CLK signals.
Serial Mode Default Startup Condition
When the device is first powered up, it will default to the maximum attenuation of 31.75dB independent of the VMODE and parallel pin [D6:D0] conditions.
Table 11. Default Setting Truth Table for Serial Control Word
For the F1958, the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode.
Direct Parallel Mode
Direct Parallel Mode is selected when VMODE is floating or a logic LOW and LE is a logic HIGH. In this mode, the device will immediately react to any voltage changes on the parallel control pins (1, 19 - 24). Use Direct Parallel Mode for the fastest settling time. The serial pins, CLK and DATA, can be either grounded or left opened in the Parallel Mode.
Latched Parallel Mode
Latched Parallel Mode is selected when VMODE is floating or a logic LOW and LE is toggled from logic LOW to HIGH. To utilize Latched Parallel Mode:
Set VMODE to logic LOW or leave floating.
Set LE to logic LOW.
Adjust pins (1, 19 - 24) to the desired attenuation setting. (Note the device will not react to these pins while LE is a logic LOW).
Set LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D6 - D0.
If LE is set to a logic LOW then the attenuator will not change state.
The truth table for the Parallel Mode is identical for bits D6 to D0 as shown in the Serial Mode truth table; see Table 9.
Set up a power supply in the voltage range of 3.0V to 5.5V with the power supply output disabled. The voltage can be applied via one of the following connections (see Figure 38):
J11 connector
J5 header connection (note the polarity of the GND pin on this connector)
Pin 9 (VDD) and pin 10 (GND) on the J6 header connection
Figure 38. Power Supply Connections
VDD
VDD
Parallel Logic Control Setup
The Evaluation Board has the ability to control the F1958 in the Parallel Mode. For external control, apply logic voltages to the J6 header pins 1 through 7 (see Figure 39). For manual control, switches 1 through 7 on SW1 can be set. The switch is a three-position switch. The bottom position, "-" will ground the pin. The center position "O" will leave the pin open circuited. Setting the switch to the top position "+" will apply a voltage that is supplied to the switch.
The logic voltage can be applied in one of three ways:
Apply a voltage through a SMA connector (J9). This connector is not supplied.
Apply a voltage on pin 2 of the J7 header connector.
Short out the two header connectors, J7 and J8, so a resistor divider will generate the correct logic voltage from the power supply on the Evaluation Board. The logic voltage will be VDD.
The Evaluation Board has the ability to control the F1958 in the Serial Mode. Connect the serial controller to the J10 header connection as shown in Figure 40. To use the Serial Mode, set SW1 switch 8 to the "+" or "O" position.
The attenuation setting can be programmed according to Table 9.
Figure 40. Serial Logic Connections
RF1 RF2
VDD
VLOGIC
SW1 Switch for parallel control
VMODE
VDD
J10 Serial Control Pins
J6 Parallel
Control Pins
Power-On Procedure
Set up the voltage supplies and Evaluation Board as described in the "Power Supply Setup" section and either the "Parallel Logic Control Setup" or "Serial Logic Control Setup" sections above.
Enable the power supply.
Enable the proper attenuation setting according to Table 9.
A common power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade the noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage changes or transients should have a slew rate smaller than 1V/20µs. In addition, all control pins should remain at 0V (+/-0.3V) while the supply voltage ramps or while it returns to zero.
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to pins for the SPI (16, 17, 18), parallel (1, 19-24) and VMODE pin (3) as shown below. Note the recommended resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity. For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control line.
Figure 41. Control Pin Interface for Signal Integrity
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available.
Orderable Part Number Package MSL Rating Shipping Packaging Temperature
F1958NBGK 4mm x 4mm x 0.75mm 24 pin QFN 1 Tray -40°C to +105°C
F1958NBGK8 4mm x 4mm x 0.75mm 24 pin QFN 1 Reel -40°C to +105°C
F1958EVB Evaluation Board
F1958EVS Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is available for download on the product page on the IDT website: http://www.idt.com/F1958
Marking Diagram
F1958
NBGK
Z1716AAG
1. Line 1 and 2 are the part number. 2. Line 3 “Z” is for die version. 3. Line 3 “yyww” = 1716 has two digits for the year and week that the part was assembled. 4. Line 3 “NG” denotes Assembly Lot number.
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the Uni ted States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.
