TMS320C6416 DSK Reference Technical

TMS320C6416 DSK

2003 DSP Development Systems

ReferenceTechnical

TMS320C6416 DSK Technical Reference

505945-0001 Rev. A April 2003

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

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Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2003 Spectrum Digital, Inc.

Contents

1 Introduction to the TMS320C6416 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C6416 DSK Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320C6416 DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.4 DC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.5 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.6 MISC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 Flash ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 LEDs and DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320C6416 DSK and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.6.1 J201, USB Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.2 J8, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.7 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.8 Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the TMS320C6416 DSKB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the TMS320C6416 DSK

About This Manual

This document describes the board level operations of the TMS320C6416 DSPStarter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6416 Digital Signal Processor.

The TMS320C6416 DSK is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320C6416 DSP to determineif the processor meets the designers application requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The TMS320C6416 DSK will sometimes be referred to as the DSK.

Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320C64xx DSP CPU Reference GuideTexas Instruments TMS320C64xx DSP Peripherals Reference Guide

Table 1: Manual History

Revision History

A Production Release

1-1

Chapter 1

Introduction to the TMS320C6416 DSK

Chapter One provides a description of the TMS320C6416 DSK alongwith the key features and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-6

Spectrum Digital, Inc

1-2 TMS320C6416 DSK Module Technical Reference

1.1 Key Features

The C6416 DSK is a low-cost standalone development platform that enables users toevaluate and develop applications for the TI C64xx DSP family. The DSK also servesas a hardware reference design for the TMS320C6416 DSP. Schematics, logicequations and application notes are available to ease hardware development andreduce time to market.

The DSK comes with a full compliment of on-board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments TMS320C6416 DSP operating at 600 MHz.

• An AIC23 stereo codec

• 16 Mbytes of synchronous DRAM

• 512 Kbytes of non-volatile Flash memory

• 4 user accessible LEDs and DIP switches

• Software board configuration through registers implemented in CPLD

• Configurable boot options

• Standard expansion connectors for daughter card use

• JTAG emulation through on-board JTAG emulator with USB host interface or external emulator

• Single voltage power supply (+5V)

Figure 1-1, Block Diagram C6416 DSK

Ext.JTAG

AIC23Codec

Hos

t Por

t Int

MUX

MUX

MIC

IN

LIN

E O

UT

HP

OU

T

LIN

E IN

Peripheral Exp

LED DIP

EMIFA

HPI

McBSPs

JTAG

0 1 2 30 1 2 3

CPL

D

Memory Exp

VoltageReg

PWR

USB

EmbeddedJTAG

JP1 1.4V

JP2 3.3V

END

IAN

BOO

TM 1

BOO

TM 0

6416DSP

SDR

AM

648

Flas

h

8

EMIFB

1 32

ConfigSW3

32

JP45V


1-3

1.2 Functional Overview of the TMS320C6416 DSK

The DSP on the 6416 DSK interfaces to on-board peripherals through one of twobusses, the 64-bit wide EMIFA and the 8-bit wide EMIFB. The SDRAM, Flash andCPLD are each connected to one of the busses. EMIFA is also connected to thedaughtercard expansion connectors which is used for third party add-in boards.

An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP1 is used for the codec control interface and McBSP2 is used for data. AnalogI/O is done through four 3.5mm audio jacks that correspond to microphone input, lineinput, line output and headphone output. The codec can select the microphone or theline input as the active input. The analog output is driven to both the line out (fixedgain) and headphone (adjustable gain) connectors. McBSP1 and McBSP2 can be re-routed to the expansion connectors in software.

A programmable logic device called a CPLD is used to implement glue logic that tiesthe board components together. The CPLD also has a register based user interfacethat lets the user configure the board by reading and writing to the CPLD registers.

The DSK includes 4 LEDs and 4 position DIP switch as a simple way to provide theuser with interactive feedback. Both are accessed by reading and writing to the CPLDregisters.

An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the 1.4V DSP core voltage and 3.3V I/O supplies. Theboard is held in reset until these supplies are within operating specifications. Aseparate regulator powers the 3.3V lines on the expansion interface.

Code Composer communicates with the DSK through an embedded JTAG emulatorwith a USB host interface. The DSK can also be used with an external emulatorthrough the external JTAG connector.



1.3 Basic Operation

The DSK is designed to work with TI’s Code Composer Studio developmentenvironment and ships with a version specifically tailored to work with the board.Code Composer communicates with the board through the on-board JTAG emulator.To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation anddrivers.

After the install is complete, follow these steps to run Code Composer. The DSK mustbe fully connected to launch the DSK version of Code Composer.

1) Connect the included power supply to the DSK.

2) Connect the DSK to your PC with a standard USB cable (also included).

3) Launch Code Composer from its icon on your desktop.

Detailed information about the DSK including a tutorial, examples and referencematerial is available in the DSK’s help file. You can access the help file through CodeComposer’s help menu. It can also be launched directly by double-clicking on the filec6416dsk.hlp in Code Composer’s docs\hlp subdirectory.


1-5

1.4 Memory Map

The C64xx family of DSPs has a large byte addressable address space. Program codeand data can be placed anywhere in the unified address space. Addresses are always32-bits wide.

The memory map shows the address space of a generic 6416 processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.

Each EMIF (External Memory Interface) has 4 separate addressable regions calledchip enable spaces (CE0-CE3). The SDRAM occupies CE0 of EMIFA while the CPLDand Flash are mapped to CE0 and CE1 of EMIFB respectively. Daughtercards useCE2 and CE3 of EMIFA.

Figure 1-2, Memory Map, C6416 DSK

Internal Memory

Reserved Spaceor

Peripheral Regs

EMIFB CE0

EMIFB CE3

EMIFB CE2

EMIFB CE1

AddressGeneric 6416

Address Space

0x60000000

0x64000000

0x68000000

0x6C000000

SDRAM

CPLD

Flash

DaughterCard

6416 DSK

InternalMemory

Reservedor

Peripheral

EMIFA CE0

EMIFA CE3

EMIFA CE2

EMIFA CE1

0x80000000

0x90000000

0xA0000000

0xB0000000

0x00000000

0x00100000



1.5 Configuration Switch Settings

The DSK has 3 configuration switches that allows users to control the operational stateof the DSP when it is released from reset. The configuration switch block is labeledSW3 on the DSK board, next to the reset switch.

Configuration switch 1 controls the endianness of the DSP while switches 2 and 3configure the boot mode that will be used when the DSP starts executing. By default allswitches are off which corresponds to EMIFB boot (out of 8-bit Flash) in little endianmode. The figure below shows these settings.

1.6 Power Supply

The DSK operates from a single +5V external power supply connected to the mainpower input (J5). Internally, the +5V input is converted into +1.4V and +3.3V using adual voltage regulator. The +1.4V supply is used for the DSP core while the +3.3Vsupply is used for the DSP's I/O buffers and all other chips on the board. The powerconnector is a 2.5mm barrel-type plug.

There are three power test points on the DSK at JP1, JP2 and JP4. All 6416 I/Ocurrent passes through JP2 while all core current passes through JP1. All systemcurrent passes through JP4. Normally these jumpers are closed. To measure thecurrent passing through remove the jumpers and connect the pins with a currentmeasuring device such as a multimeter or current probe.

The DSK provides +3.3V, up to 1A for the daughter card. The +3.3V supply is derivedfrom the +5V power source via the main +3.3 volt regulator. It is also possible toprovide the daughter card with +12V and -12V when the external power connector (J6)is used.

Table 1: Configuration Switch Settings

Switch 3 Switch 2 Switch 1 Configuration Description

Off Off EMIF boot from 8-bit Flash

Off On No Boot

On Off Reserved

On On HPI boot

Off Little endian

On Big endian

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe TMS320C6416 DSK.

Topic Page

2.1 CPLD (Programmable Logic) 2-22.1.1 CPLD Overview 2-22.1.2 CPLD Registers 2-32.1.3 USER_REG Register 2-32.1.4 DC_REG Register 2-42.1.5 Version Register 2-42.1.6 MISC Register 2-52.2 AIC23 Codec 2-62.3 Sychronous DRAM 2-72.4 Flash Memory 2-72.5 LEDs and DIP Switches 2-72.6 Daughter Card Interface 2-8



2.1 CPLD (Programmable Logic)

The C6416 DSK uses an Altera EPM3128TC100-10 Complex Programmable LogicDevice (CPLD) device to implement:

• 4 Memory-mapped control/status registers that allow software control of various board features.

• Address decode and memory access logic.

• Control of the daughter card interface and signals.

• Assorted "glue" logic that ties the board components together.

2.1.1 CPLD Overview

The CPLD logic is used to implement functionality specific to the DSK. Your ownhardware designs will likely implement a completely different set of functions or takeadvantage of the DSPs high level of integration for system design and avoid the use of external logic completely.

The CPLD implements simple random logic functions that eliminate the need foradditional discrete devices. In particular, the CPLD aggregates the various resetsignals coming from the reset button and power supervisors and generates a globalreset.

The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industrystandard VHDL (Hardware Design Language) and included with the DSK.


2-3

2.1.2 CPLD Registers

The 4 CPLD memory-mapped registers allows users to control CPLD functions insoftware. On the 6416 DSK the registers are primarily used to access the LEDs andDIP switches and control the daughter card interface. The registers are mapped intoEMIFB data space at address 0x60000000. They appear as 8-bit registers with asimple asynchronous memory interface. The following table gives a high leveloverview of the CPLD registers and their bit fields:

The table below shows the bit definitions for the 4 registers in CPLD.

2.1.3 USER_REG Register

USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on oroff to allow the user to interact with the DSK. The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.

Table 1: CPLD Register Definitions

Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 USER_REG USR_SW3R

USR_SW2R

USR_SW1R

USR_SW0R

USR_LED3R/W

0(Off)

USR_LED2R/W

0(Off)

USR_LED1R/W

0(Off)

USR_LED0R/W

0(Off)

1 DC_REG DC_DETR

0 DC_STAT1R

DC_STAT0R

DC_RSTR

0(No reset)

0 DC_CNTL1R/W

0(low)

DC_CNTL0R/W

0(low)

4 VERSION CPLD_VER[3.0]R

0 BOARD VERSION[2.0]R

6 MISC McBSP2_ENR

(MCBSP2enabled)

SCR_4R/W

0

SCR_3R/W

0

SCR_2R/W

0

SCR_1R/W

0

FLASH_PAGER/W

0(A19=0)

McBSP2ON/OFFBoardR/W

0(Onboard)

McBSP1ON/OFFBoardR/W

0(Onboard)

Table 2: CPLD USER_REG Register

Bit Name R/W Description

7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)




3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)






2.1.4 DC_REG Register

DC_REG is used to monitor and control the daughter card interface. DC_DET detectsthe presence of a daughter card. DC_STAT and DC_CNTL provide simplecommunications with the daughter card through readable status lines and writablecontrol lines.

The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.

2.1.5 VERSION Register

The VERSION register contains two read only fields that indicate the BOARD andCPLD versions. This register will allow your software to differentiate betweenproduction releases of the DSK and account for any variances. This register is notexpected to change often, if at all.

Table 3: DC_REG Register


7 DC_DET R Daughter Card Detect (1= Board detected)

6 0 R Always 0

5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)

4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)

3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)

2 0 R Always zero

1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)

0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)

Table 4: Version Register Bit Definitions

Bit # Name R/W Description

7 CPLD_VER3 R Most Significant CPLD Version Bit

6 CPLD_VER2 R CPLD Version Bit

5 CPLD_VER1 R CPLD Version Bit

4 CPLD_VER0 R Least Significant CPLD Version Bit

3 0 R Always 0

2 DSK_VER2 R Most Significant DSK Board Version Bit

1 DSK_VER1 R DSK Board Version Bit

0 DSK_VER0 R Least Significant DSK Board Version Bit


2-5

2.1.6 MISC Register

The MISC register is used to provide software control for miscellaneous boardfunctions. On the 6416 DSK, the MISC register controls how auxiliary signals arebrought out to the daughter-card connectors.

McBSP1 and McBSP2 are usually used as the control and data ports of the on-boardAIC23 codec. The power-on state of these bits (both 0s) represents that configuration. Set MCBSP1SEL or MCBSP2SEL to route the McBSPs to the daughtercardconnectors rather than the codec.

The Flash and CPLD share CE1 which means that the highest address bit (A21) isused to differentiate between the two. In this configuration 512Kbytes of 8-bit Flash arevisible at the beginning of CE1 which matches the chip on the production board. If theFlash is replaced with a 1Mbyte chip, only 512Kbytes of Flash will still be visible butFLASH_PAGE can be used to select between the top and bottom halves. FLASH_PAGE replaces the address bit (A21) that is lost sharing CE1 with the CPLD.

The 6416’s PCI interface and McBSP2 share some pins. The McBSP2_EN signal isused to disable McBSP2 when the PCI interface is active. McBSP2_EN is generatedon the board when an appropriate daughtercard that uses PCI is plugged in, it can beread through this CPLD bit.

The scratch bits are unused. They can be set to any value.

Table 5: MISC Register


7 McBSP2_EN R Value of McBSP2_EN from PCI header

6 SCRATCH_4 R/W Scratch bit 4




2 FLASH_PAGE R/W Flash address bit 19

1 MCBSP2SEL R/W McBSP2 on/off board (0 = on-board, 1 = off-board)

0 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)



2.2 AIC23 Codec

The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for inputand output of audio signals. The codec samples analog signals on the microphone orline inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples backinto analog signals on the line and headphone outputs so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internalconfiguration registers and one to send and receive digital audio samples. McBSP1 isused as the unidirectional control channel. It should be programmed to send a 16-bitcontrol word to the AIC23 in SPI format. The top 7 bits of the control word shouldspecify the register to be modified and the lower 9 should contain the register value. The control channel is only used when configuring the codec, it is generally idle whenaudio data is being transmitted,

McBSP2 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The DSK examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side. Thepreferred serial format is DSP mode which is designed specifically to operate with theMcBSP ports on TI DSPs.

The codec has a 12MHz system clock. The 12MHz system clock corresponds to USBsample rate mode, named because many USB systems use a 12MHz clock and canuse the same clock for both the codec and USB controller. The internal sample rategenerate subdivides the 12MHz clock to generate common frequencies such as48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATEregister. The figure below shows the codec interface on the C6416 DSK.

Figure 2-1, TMS320C6416 DSK CODEC INTERFACE

MIC IN

LINE IN

LINE OUT

HP OUT

ADC

DAC

McBSP2

DSP Format

0 LEFTINVOL1 RIGHTINVOL2 LEFTHPVOL3 RIGHTHPVOL4 ANAPATH5 DIGPATH6 POWERDOWN7 DIGIF8 SAMPLERATE9 DIGACT15 RESET

Con

trol R

egis

ters

LRCINBCLK

DIN

DOUTLRCOUTFSX2

DX2

CLKXFSR2

CLKR

DR2

CSSCLKSDIN

McBSP1

SPI Format

FSX1

TX1CLKX1

AIC23 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT


2-7

2.3 Synchronous DRAM

The DSK uses a pair of industry standard 64 megabit SDRAMs in CE0 of EMIFA. Thetwo devices are used in parallel to create a 64-bit wide interface. Total availablememory is 16 megabytes.

The DSK uses an EMIFA clock of 100MHz. The integrated SDRAM controller is startedby configuring the EMIF in software. Timings can be found in the SDRAM datasheetand the DSK help file. When using the SDRAM, note that one row of the memory arraymust be refreshed at least every 15.6 microseconds to maintain the integrity of itscontents.

2.4 Flash Memory

The DSK uses a 512Kbyte external Flash as a boot option. It is connected to CE1 ofEMIFB with an 8-bit interface. Flash is a type of memory which does not lose itscontents when the power is turned off. When read it looks like a simple asynchronousread-only memory (ROM). Flash can be erased in large blocks commonly referred toas sectors or pages. Once a block has been erased each word can be programmedonce through a special command sequence. After than the entire block must be erasedagain to change the contents.

The Flash requires 70ns for both reads and writes. The general settings used with theDSK use 8 cycles for both read and write strobes (80ns) to leave a little extra margin.

2.5 LEDs and DIP Switches

The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) thatprovide the user a simple form of input/output. Both are accessed through the CPLDUSER_REG register.



2.6 Daughter Card Interface

The DSK provides three expansion connectors that can be used to accept plug-indaughter cards. The daughter card allows users to build on their DSK platform toextend its capabilities and provide customer and application specific I/O. Theexpansion connectors are for memory, peripherals, and the Host Port Interface (HPI)

The memory connector provides access to the DSP’s asynchronous EMIF signals tointerface with memories and memory mapped devices. It supports byte addressing on32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals likeMcBSPs, timers, and clocks. Both connectors provide power and ground to thedaughter card

The HPI is a high speed interface that can be used to allow multiple DSPs tocommunicate and cooperate on a given task. The HPI connector brings out the HPIspecific control signals as well as McBSP2.

Most of the expansion connector signals are buffered so that the daughter card cannotdirectly influence the operation of the DSK board. The use of TI low voltage, 5V tolerantbuffers, and CBT interface devices allows the use of either +5V or +3.3V devices to beused on the daughter card.

Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET andDC_DET exist and are accessible through the CPLD DC_REG register. The DSKalso multiplexes the McBSP1 and McBSP2 of on-board or external use. This functionis controlled through the CPLD MISC register.

3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the TMS320C6416 DSKand its connectors.

Topic Page

3.1 Board Layout 3-23.2 Connector Index 3-33.3 Expansion Connectors 3-33.3.1 J4, Memory Expansion Connector 3-43.3.2 J3, Peripheral Expansion Connector 3-53.3.3 J1, HPI Expansion Connector 3-63.4 Audio Connectors 3-73.4.1 J301, Microphone Connector 3-73.4.2 J303, Audio Line In Connector 3-73.4.3 J304, Audio Line Out Connector 3-83.4.4 J302, Headphone Connector 3-83.5 Power Connectors 3-93.5.1 J5, +5 Volt Connector 3-93.5.2 J6, Optional Power Connector 3-93.6 Miscellaneous Connectors 3-103.6.1 J201, USB Connector 3-103.6.2 J8, External JTAG Connector 3-103.6.3 JP3, PLD Programming Connector 3-113.7 System LEDs 3-113.8 Reset Switch 3-12



3.1 Board Layout

The C6416 DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which ispowered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6416 DSK.

Figure 3-1, TMS320C6416 DSK

J4

J5J6 JP3

J302

J8SW1 SW2J201 D7-10

J304J303J301 J3 J1 J2


3-3

3.2 Connector Index

The TMS320C6416 DSK has many connectors which provide the user accessto the various signals on the DSK.

Note: “*” Not populated

3.3 Expansion Connectors

The TMS320C6416 DSK supports three expansion connectors that follow the TexasInstruments interconnection guidelines. The expansion connector pinouts aredescribed in the following three sections.

The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profileconnectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectorsare designed for high speed interconnections because they have low propagationdelay, capacitance, and cross talk. The connectors present a small foot print on theDSK. Each connector includes multiple ground, +5V, and +3.3V power signals so thatthe daughter card can obtain power directly from the DSK. The peripheral expansionconnector additionally provides both +12V and -12V to the daughter card. Therecommended mating connector, whose part number is TFM-140-32-S-D-LC, is asurface mount connector that provides a 0.465” mated height.

Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin

Table 1: TMS320C6416 DSK Connectors

Connector # Pins Function

J4 80 Memory

J3 80 Peripheral

J1 80 HPI

J301 3 Microphone

J303 3 Line In

J304 3 Line Out

J303 3 Headphone

J5 2 +5 Volt

J6 * 4 Optional Power Connector

J8 14 External JTAG

J201 5 USB Port

JP3 10 CPLD Programming

SW3 8 DSP Configuration Jumper



3.3.1 J4, Memory Expansion Connector

Table 2: J4, Memory Expansion Connector

Pin Signal I/O Description Pin Signal I/O Description

1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin

3 AEA21 O EMIF address pin 21 4 AEA20 O EMIF address pin 20




11 GND Vss System ground 12 GND Vss System ground








27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2

29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0


33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30




41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
















73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable

75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready

77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2



3-5

3.3.2 J3, Peripheral Expansion Connector

Table 3: J3, Peripheral Expansion Connector


1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin





11 N/C - No connect 12 N/C - No connect




19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin

21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source

23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data


27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect

29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data


33 CLKX2 I/O McBSP2 transmit clock 34 CLKS2 I McBSP2 clock source

35 FSX2 I/O McBSP2 transmit frame sync 36 DX2 O McBSP2 transmit data


39 CLKR2 I/O McBSP2 receive clock 40 N/C - No connect

41 FSR2 I/O McBSP2 receive frame sync 42 DR2 I McBSP2 receive data


45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input

47 N/C - No connect 48 EXT_INT5 I External interrupt 5

49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input


53 EXT_INT4 I External interrupt 4 54 N/C - No connect



59 RESET O System reset 60 N/C - No connect


63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control

65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status

67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7

69 ACE3# O Chip enable 3 70 N/C - No connect



75 DC_DET# Vss System ground 76 GND Vss System ground

77 GND Vss System ground 78 ECL KOUT O EMIF Clock




3.3.3 J1, HPI Expansion Connector

Table 4: J1, HPI Expansion Connector


1 PCI_EN I PCI enable 2 BSP2_EN I MCBSP2_EN

3 GND Vss System ground 4 HPI_RS# I HPI reset

5 XSP_CS O PCI serial 6 BEA13 I PCI EEPROM auto-init


9 AD1 I/O PCI address/data 1 10 PCBE0# I/O PCI command/byte ena 0

11 AD3 I/O PCI address/data 3 12 AD0 I/O PCI address/data 0



17 GND System ground 18 AD6 I/O PCI address/data 6

19 AD8 I/O PCI address/data 8 20 GND Vss System ground




27 GND Vss System ground 28 AD15 I/O PCI address/data 15

29 PCBE1# I/O PCI command/byte ena 1 30 GND Vss System ground

31 GND Vss System ground 32 PPAR I/O PCI parity

33 PSERR# I/O PCI system error 34 GND Vss System ground

35 GND Vss System ground 36 PSTOP# I/O PCI stop

37 PPERR# I/O PCI parity error 38 GND Vss System ground

39 GND Vss System ground 40 PTRDY# I/O PCI target ready

41 PDEVSEL# I/O PCI device select 42 GND Vss System ground

43 GND Vss System ground 44 PFRAME# I/O PCI Frame

45 PIRDY# I/O PCI initiator ready 46 GND Vss System ground


49 PCBE2# I/O PCI command/byte ena 2 50 AD18 I/O PCI address/data 18




57 AD23 I/O PCI address/data 23 58 PIDSEL I PCI init device select

59 PCBE3# I/O PCI command/byte ena 3 60 AD24 I/O PCI address/data 24




67 AD29 I/O PCI address/data 29 68 PGNT# I PCI bus grant


71 GND Vss System ground 72 PRST# I PCI reset

73 PREQ# O PCI bus request 74 GND Vss System ground

75 GND Vss System ground 76 PINTA# O PCI interrupt A

77 PCLK I PCI Clock 78 GND Vss System ground

79 GND Vss System ground 80 N/C - No connect


3-7

3.4 Audio Connectors

The C6416 DSK has 4 audio connectors. They are described in the followingsections.

3.4.1 J301, Microphone Connector

The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it ismonaural. The signals on the plug are shown in the figure below.

3.4.2 J303, Audio Line In Connector

The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.

Microphone In

Ground

Figure 3-2, Microphone Stereo Jack

Microphone Bias

Left Line In

Ground

Figure 3-3, Audio Line In Stereo Jack

Right Line In



3.4.3 J304, Audio Line Out Connector

The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.

3.4.4 J303, Headphone Connector

Connector J4 is a headphone/speaker jack. It can drive standard headphones or a highimpedance speaker directly. The standard 3.5 mm jack is shown in the figure below

.

Left Line Out

Ground

Figure 3-4, Audio Line Out Stereo Jack

Right Line Out

Left Headphone

Ground

Figure 3-5, Headphone Jack

Right Headphone


3-9

3.5 Power Connectors

The C6416 DSK has 2 power connectors. They are described in the followingsections.

3.5.1 J5, +5 Volt Connector

Power (+5 volts) is brought onto the TMS320C6416 DSK via connector J5. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. TheA diagram of J5 is shown below.

3.5.2 J6, Optional Power Connector

Connector J6 is an optional power connector. It will operate with the standard personalcomputer power supply. To populate this connector use a Molex #15-24-4041. Thetable below shows the voltages on the respective pins.

Table 5: J6, Optional Power Connector

Pin # Voltage Level

1 +12 Volts

2 -12 Volts

3 Ground

4 +5 Volts

PC Board

J5+5V

Ground

Front ViewFigure 3-6, TMS320C6416 DSK Power Connector

WARNING !Do not plug into J5 and J6 at the same time.



3.6 Miscellaneous Connectors

The C6416 DSK has 3 additional connectors to aid the user in developing with thisproduct. They are described in the following sections.

3.6.1 J201, USB Connector

Connector J201 provides a Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the DSK. This allows for code development and debugwithout the use of an external emulator. The signals on this connector are shown in thebelow.

3.6.2 J8, External JTAG Connector

The TMS320C6416 DSK is supplied with a 14 pin header interface, J8. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.The pinout for the connector is shown figure 3-6 below.

Table 6: J201, USB Connector

Pin # USB Signal Name

1 USBVdd

2 D+

3 D-

4 USB Vss

5 Shield

6 Shield

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 3-7, JTAG INTERFACE


3-11

The signal names for each pin are shown in the table below.

3.6.3 JP3, PLD Programming Connector

This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for theprogramming of the CPLD. This connector is not intended to be used outside thefactory.

3.7 System LEDs

TheTMS320C6416 DSK has four system light emitting diodes (LEDs). TheseLEDs indicate various conditions on the DSK. These function of each LED is shown inthe table below.

Table 7: J8, JTAG Interface

Pin # Signal Name

1 TMS

2 TRST-

3 TDI

4 GND

5 PD

6 no pin

7 TDO

8 GND

9 TCK-RET

10 GND

11 TCK

12 GND

13 EMU0

14 EMU1

Table 8: System LEDs

Reference Designator Color Function On Signal

State

D4 Green USB Emulation in use. When External JTAG Emulator is used this LED is off.

1

D3 Green +5 Volt present 1

D6 Orange RESET Active 1

DS201 Green USB Active, Blinks during USB data transfer 1



3.8 Reset Switch

There are three resets on the TMS320C6416 DSK. The first reset is the power onreset. This circuit waits until power is within the specified range before releasing thepower on reset pin to the TMS320C6416.

External sources which control the reset are push button SW2, and the on boardembedded USB JTAG emulator.

A-1

Appendix A

Schematics

This appendix contains the schematics for the TMS320C6416 DSK.Board components with designators between 200 and 299 (e.g. DS201,R211) are part of Spectrum Digital’s embedded JTAG emulator and are notincluded in these schematics.


A-2 TMS320C6416 DSK Module Technical Reference

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NBC BC

AB

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NAB

BCAB

BCO

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B CB C

5059

42D

TMS3

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416

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B

314

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

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of

CLK

MO

DE0

CLK

MO

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( 2)

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(2)

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(2)

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( 2)

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(2)

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(2)

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CLK

MO

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MO

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DG

ND

3 .3V

DG

ND

3.3V

DG

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DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

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DG

ND

DG

ND

DG

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3 .3V

3 .3V

T P29

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n

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hip

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33

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1 133 4 7 8 11

2 5 6 9 10

1 4 17 1 8 21 22

24 121 5 16 1 9 20 23

1OE

2OE

1A1

1 A2

1 A3

1A4

1A5

1B1

1 B2

1 B3

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2 A2

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V cc

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2 B2

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R51

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AD17

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A D18

AC18

D6

B 5 A4A F6

A E6

A D6

A C6

H4

H2

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A E5

A D5

A F4

C6 A 5 C5

AF18

A B16

AF16

A B15

H25 A1

1

E MU

0EM

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EMU

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U3

EMU

4EM

U5

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U7

E MU

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U11

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IN

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MO

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CLK

MO

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PLLV

RES

ET

NM

IE X

TIN

T4_G

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7

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A-5

EMIF

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5059

42B

TMS3

20C

6416

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B

414

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

T AED

34

TAED

51

T AED

48

TAED

45

T AED

42

T AED

54

T AED

46

T AED

57T A

ED56

TAED

37

TAED

43

TAED61

T AED

55

TAED32

T AED

44

TAED

61

T AED

33

TAED

53

TAED58

TAED

36

T AED

49

TAED

39

TAED55

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T AED

62

T AED

50

TAED

32

T AED

58

T AED

38

T AED

40

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47

TAED62

T AED

60

T AED

52

TAED

63

TAED60

TAED53T A

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59

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35

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T ASD

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#

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LKO

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TAED31

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12

T AED

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7

TAED17

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8

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16

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6

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13

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9

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7

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12

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T ABE

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4

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31

T AED

28T A

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7

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5

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29

T AED

18

TAED

3

T AEA

6

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3

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9

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13

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5

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T ABE

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T AED

24

T AED

1

T AEA

11

TAED28

TAED

19

T AED

2

T AEA

9

TAED18

TAED13

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13

TAED

15

T AED

8

TAED8

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5

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16

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11

T AED

17

T AED

25

T AED

10

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9

T AEA

14

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T AEA

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T AEA

8

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11

T AED

30

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10

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TAED6

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8

TAEA

3

T AEA

7

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T AED

6

TAED20

T AEA

6

TAED5

TAED30

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5

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T AED

12

TAED3

T AEA

4

T AEA

10

TAEA

16

TAEA

15

TAEA

3T A

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TAED

0

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RAS

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TASD

WE#

TAC

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TASD

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T ASD

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CE0

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CAS

#

T AEC

LKO

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T AEC

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TASD

CKE

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CKE

T AEA

21

T AEA

17

TAEA

20

TAEA

22

T AEA

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EA18

TAAR

DY

AEA8

AEA2

0

A BE1

#

AED43

AED36

AEA1

4

A EA1

7

A BE6

#

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DY

A EA1

3

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AED58

AED46

A EA1

2

A EA1

5

A CE2

#

AED40

AEA3

A EA1

1

A EA1

8

A BE5

#

ABE0

#

ABE2

#

AED52

AED44

AEA5

AED59

AED34

ASD

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AED51

AED32

A EA9

A EA2

1

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LKO

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ABE4

#

AED45

AED53

AED41

A EA4

A EA7

A CE0

#

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A SD

CAS

#

AED48

A EA6

A EA1

9

A EC

LKO

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A BE3

#

AED42

AEA1

6

A BE7

#

AED38

A EA1

0

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#

AED33

AEA2

2

A SD

RAS

#

AED49

AED37

T ASD

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E#

TAED57

TAED42TAED41

TAED36

AED63AED62AED61AED60

AED57AED56AED55AED54

AED50

AED29

AED7

AED1AED0

AED14

AED11

AED4

AED18

AED16

AED13

AED2

AED30

AED21

AED9

AED6

AED17

AED20

AED15

AED27AED26

AED24

AED8

AED25

AED12

AED28

AED23

AED3

AED31

AED22

AED19

AED10

AED5

TAED33TAED34TAED35

TAED37

TAED39TAED40

TAED43TAED44TAED45TAED46

TAED48TAED49

TAED52

TAED54

TAED56

TAED59

TAED63

T AEA

17T A

EA17

T AEA

[22.

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(9)

TAAR

DY

(9)

TASD

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( 2,9

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(9)

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( 2,9

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TABE

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BE0#

( 9)

TAED

[63.

.0]

(9)

3.3V

3.3V

DG

ND

DG

ND

DG

ND

3.3V

RN14B 33

RN11F 33

U10

A

T MS3

20C

6416

GLZ

AD26AC26AC25AB25AB24AB26AA24AA25AA23AA26Y24Y25Y23Y26W23W24AD19AC19AF20AC20AE20AD20AF21AC21AE21AD21AF22AD22AE22AE23AF23AF24

T 23

T 24

R25

R26

M25

M26

L23

L 24

L 26

K 23

K 24

K25

M22

P 22

N22

R22

J 25

J 24

K 26

L 25

J26

J 23

A24A23B23B22C22A22C21B21D21A21C20B20D20A20D19C19H24H23G26G23G25G24F26F23F25F24E26E24E25D25D26C26

T 22

V 24

V 25

V 26

U23

U24

U25

U26 T2

5T 2

6R

23R

24 P23

P 24

P26

N23

N24

N26

M23

M24 L 2

2V2

3

AED32AED33AED34AED35AED36AED37AED38AED39AED40AED41AED42AED43AED44AED45AED46AED47AED48AED49AED50AED51AED52AED53AED54AED55AED56AED57AED58AED59AED60AED61AED62AED63

ABE7

A BE6

ABE5

A BE4

ABE3

A BE2

ABE1

A BE0

ACE3

ACE2

A CE1

A CE0

A PD

TA B

USR

EQ0

A HO

LDA

ASO

E3A _

ARE/

SDC

AS/S

ADS/

SRE

A_AO

E/SD

RAS

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EA _

AWE/

SDW

E/SW

E

ASD

CKE

AEC

LKO

UT1

A EC

LKO

UT2

AED0AED1AED2AED3AED4AED5AED6AED7AED8AED9AED10AED11AED12AED13AED14AED15AED16AED17AED18AED19AED20AED21AED22AED23AED24AED25AED26AED27AED28AED29AED30AED31

AEA2

2A E

A21

AEA2

0A E

A19

AEA1

8A E

A17

AEA1

6A E

A15

A EA1

4AE

A13

AEA1

2A E

A11

A EA1

0A E

A9A E

A8A E

A7A E

A6A E

A5AE

A4A E

A3

AAR

DYAH

OLD

RN

8H3 3

R41

1 0K

RN

12C

3 3

RN

8G33

RN13D 33

RN10D 33

RN14F 33

R44

3 3

RN11B 33

RN

12B

33

R46

3 3R

433 3

RN

8F3 3

RN13H 33

RN

12A

3 3

RN14A 33

RN11G 33

RN

8E3 3

T P18

RN

9H3 3

RN13C 33

RN10E 33

RN14E 33

RN7

A33

RN

7B3 3

RN11C 33

RN

7C33

RN

7D3 3

RN

7E3 3

RN

7F3 3

RN

7G33

RN

7H3 3

RN

8D3 3

T P17

RN

9G33

C97

0.1

C75

0.1

C73

0.1

RN13G 33

RN10A 33

RN5B 33

RN5D 33RN5E 33RN5F 33

RN4B 33

RN6H 33

RN6F 33 RN11H 33

RN

8C33

C95

0.1

RN6C 33

RN3D 33

RN6A 33

RN4D 33

RN5C 33

RN3G 33

RN3A 33

RN3C 33

RN4C 33

RN4G 33

RN6D 33

RN3E 33

RN6E 33

RN5H 33RN4A 33

RN6G 33

C44

0.1

RN3B 33

RN3H 33

RN6B 33

RN5G 33

RN4E 33

RN4H 33

RN3F 33

RN4F 33

RN

9F3 3

RN5A 33U

9

MT4

8LC

2M32

B2T

G-6

2 4 5 7 8 10 11 1 3 7 4 7 6 7 7 7 9 80 8 2 83 8 5 31 3 4 3 6 37 3 9 40 4 2 4 5 4 7 4 8 5 0 5 1 5 3 54 5 63 3

24 66 65 64 6 3 6 2 6 1 6 0 2 7 26 2 52 3 22 68 6 72 07 1 1 6 1 9 1 8 1 75 9 28 8 6 72 5 8 44 8 4 78 52 46 3 8 32 12 6

4 3 29 1 5 1 8 1 75 55 49 4 1 35 9 3

2 1 70 6 973 5 7 30 1 4

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

DQ

16

DQ

18D

Q19

DQ

20D

Q21

DQ

22D

Q23

DQ

24D

Q25

DQ

26D

Q27

DQ

28D

Q29

DQ

30D

Q31

DQ

17

A10 A9 A 8 A7 A6 A5 A4 A3 A2 A1 A0BA1

BA0

CLK

CKEC

S

DQ

M1

DQ

M0

RAS

CAS W

E

DQ

M3

DQ

M2

V SS

V SS

VSS

VSS

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

V SSQ

VSSQ

VSSQ

V DD

V DD

VDD

VDD

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

V DDQ

VDDQ

VDDQ

NC

NC

NC

NC

NC

NC

NC

C74

0.1

C45

0.1

U13

MT4

8LC

2M32

B2TG

-6

2 4 5 7 8 10 11 1 3 7 4 7 6 7 7 7 9 80 8 2 83 8 5 31 3 4 3 6 37 3 9 40 4 2 4 5 4 7 4 8 5 0 5 1 5 3 54 5 63 3

24 66 65 64 6 3 6 2 6 1 6 0 2 7 26 2 52 3 22 68 6 72 07 1 1 6 1 9 1 8 1 75 9 28 8 6 72 5 8 44 8 4 78 52 46 3 8 32 12 6

4 3 29 1 5 1 8 1 75 55 49 4 1 35 9 3

2 1 70 6 973 5 7 30 1 4

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

DQ

16

DQ

18D

Q19

DQ

20D

Q21

DQ

22D

Q23

DQ

24D

Q25

DQ

26D

Q27

DQ

28D

Q29

DQ

30D

Q31

DQ

17

A10

A9 A 8 A7 A6 A5 A4 A3 A2 A1 A0BA1

BA0

CLK

CKE

CS

DQ

M1

DQ

M0

RAS

CAS

WE

DQ

M3

DQ

M2

V SS

V SS

VSS

VSS

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

V SSQ

VSSQ

VSSQ

V DD

V DD

VDD

VDD

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

V DDQ

VDDQ

VDDQ

NC

NC

NC

NC

NC

NC

NC

RN

8B3 3

C42

0.1

RN13B 33

RN10F 33

RN14D 33

RN11D 33

RN

9E3 3

R42

3 3

RN8

A33

R26

3 3

TP11

RN13F 33

RN

9D3 3

RN10B 33

RN14H 33

C43

0.1

C41

0.1

RN

9C3 3

RN13A 33

+C

T5 10

RN10G 33

RN14C 33

T P14

RN11E 33

T P13

R45

33

RN

9B3 3

+C

T13

10

R48

3 3

R25

3 3

RN13E 33

R47

33

RN10C 33

RN14G 33

RN11A 33

RN9

A33

T P12

RN

12D

33

R49

3 3

RN10H 33



EMIF

B &

FLA

SH

LIL_

END

IAN

BOO

T_M

OD

E1BO

OT_

MO

DE0

A ECL

KIN

_SEL

1A E

CLKI

N_S

EL0

BEC

LKIN

_SEL

0BE

CLK

IN_S

EL1

E EAI

UT O

PIA_

EN

NEA

R D

SP

NEA

R D

SP

NEA

R D

SP

P EN

CIL

SW

ITC

H

END

IAN

BOO

T-1

B OO

T-0

OFF

- O

PEN

ON

- C

LOSE

D

IPU

IPU

IPD

5059

42C

TMS3

20C6

416

DSK

B

514

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

B EA6

BEA1

7

B EA7

BEA1

1

B EA1

9

B EA8

BEA3

B EA1

0BE

A9

B EA2

0

BEA1

2

BEA2

BEA1

4B E

A13

B EA1

5

B EA1

8

B EA1

6

BEA5

BEA4

BEA1

BEC

LKO

UT2

TBAO

E#

BEC

LKO

UT1

B ARE

#

TBE

CLK

OU

T1

BAO

E#T B

AWE#

B AW

E#

BCE1

#TB

CE

1# TBE

CLK

OU

T2

TBED0

TBED5

T BE

D3

TBED2

TBE

D5

TBED1

TBED4T B

ED

1TBED6

TBED3T B

ED

0

TBED7T B

ED

4

T BE

D2

T BE

D6

TBAO

E#

TBE

D7

TBAW

E#

TBEA

9

TBEA

7

TBEA

1TB

EA17

T BEA

17

TBEA

3TB

EA15

TBEA

4

TBEA

5

TBEA

11

TBEA

8

T BEA

8

T BEA

13T B

EA6

TBEA

8

TBEA

12

TBEA

14

TBEA

14

T BEA

7

TBEA

18

T BEA

4

T BEA

13

TBEA

15

T BEA

15

T BEA

9

TBEA

16

T BEA

20

T BEA

10

T BEA

16

TBEA

2

TBEA

17

TBEA

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UR

DATA

4

UR

DATA

0

UR

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AV

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DATA

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SOC

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DATA

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DATA

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RDA

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DATA

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UR

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DATA

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ATA0

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UXD

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ADD

R2

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ADD

R0

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ADD

R4

UXCL

AV

UXS

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UXC

LK

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0U

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DD

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PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7PAD8PAD9PAD10PAD11PAD12PAD13PAD14PAD15PAD16PAD17PAD18PAD19PAD20PAD21PAD22PAD23PAD24PAD25PAD26PAD27PAD28PAD29PAD30PAD31

PDEV

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PSTO

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PAD2

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PAD2

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PAD2

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PAD1

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P AD

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CBSP

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MC

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T BEA

13

TBEA

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DG

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DG

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DG

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DG

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DG

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DG

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34

56

78

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1 71 8

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2 32 4

2 52 6

2728

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3132

3 33 4

3536

3 73 8

3940

4 14 2

4344

4 54 6

4748

4950

5152

5 35 4

5556

5758

5960

6 16 2

6364

6566

6768

6970

7172

7374

7576

7778

7980

12

34

56

78

91 0

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1920

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2324

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2930

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3 33 4

3536

3 73 8

3 94 0

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4344

4546

4748

4950

5152

5354

5 55 6

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5960

6162

6 36 4

6566

6768

6970

7172

7374

7576

7778

7980

R19

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1 4

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9 1213 12 1 5103 5 6

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1 A

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13 A 4A

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1 B1

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1 B2

2 B1

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34

56

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2526

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2930

3 13 2

3334

3 53 6

3738

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4 34 4

4546

4748

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5 15 2

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6768

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12

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4546

4748

4950

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5 35 4

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6 16 2

6364

6566

6768

6970

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7576

7778

7980

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A E9

A F11

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A B13

AB11

AD7

A E7

AF7

A F9

AE8

A D8

AD9

AD10

AD11

AC14

AE15

A C13

A E10

A F10

AC10

A C8

AB12

AD13

A D14

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A C12

AC11

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AF12

AD12

AF14

AD15

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R0U

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SX1

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DD

R4_D

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ATA0

UXD

ATA1

UXD

ATA2

UXD

ATA3

UXD

ATA4

UXD

ATA5

UXD

ATA6

UXD

ATA7

UXC

LKUX

CLAV

UXE

NB

UXS

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UR

ADD

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ADD

R1

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KX1

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DATA

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TA3

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DATA

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RDA

TA5

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DATA

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RDA

TA7

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CLK

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LAV

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HC

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AD31_HD31AD30_HD30AD29_HD29AD28_HD28AD27_HD27AD26_HD26AD25_HD25AD24_HD24AD23_HD23AD22_HD22AD21_HD21AD20_HD20AD19_HD19AD18_HD18AD17_HD17AD16_HD16AD15_HD15AD14_HD14AD13_HD13AD12_HD12AD11_HD11AD10_HD10

AD9_HD9AD8_HD8AD7_HD7AD6_HD6AD5_HD5AD4_HD4AD3_HD3AD2_HD2AD1_HD1AD0_HD0

PCBE

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PID

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P10

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0 F

OR

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5059

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TMS3

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Tues

day,

Apr

il 01

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3

Title

Size

Doc

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t Num

ber

Rev

Dat

e:Sh

eet

of

TAEA

13

DC

_D30

DC

_D16

DC

_D26

DC

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DC

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DC

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T AEA

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DC

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DC

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DC

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T AED

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1

DC_

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TAEA

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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DC_

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T AEA

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DC

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DC

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T AED

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DC

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DC

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DC_

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DC

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DC_

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DC

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DC

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DC

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T AEA

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T AED

9

T AED

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T AEA

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DC

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DC

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DC

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DC

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DC

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DC_

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T AED

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DC

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DC

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DC_

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19

T AED

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DC

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DC

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DC

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DC_

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DC

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DC

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5

TAEA

16

TAED

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DC

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31

DC

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14

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12

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10 TAED

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22TA

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28TA

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26TA

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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3 .3V

DG

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3 .3V

3 .3V

3 .3V 3 .

3V

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

3 .3V

DG

ND

3 .3V

3.3V

U16

SN74

LVTH

1624

5A

7 18314 2 47 4 6 44 4 3 41 4 0 38 3 7

2 3 5 6 8 9 11 1 236 35 33 3 2 30 29 27 2 6

13 14 16 1 7 19 20 22 2 3

48 1 25 24 4 10 15 21

28 34 39 45

V cc

Vcc

Vcc

V cc

1A1

1 A2

1A3

1 A4

1 A5

1A6

1A7

1A8

1B1

1 B2

1B3

1 B4

1 B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2 A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2 B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R40

31K

U6

SN74

LVTH

1624

5A

7 18314 2 47 4 6 44 4 3 41 4 0 38 3 7

2 3 5 6 8 9 11 1 236 35 33 3 2 30 29 27 2 6

13 14 16 1 7 19 20 22 2 3

48 1 25 24 4 10 15 21

28 34 39 45

V cc

Vcc

Vcc

V cc

1A1

1 A2

1A3

1 A4

1 A5

1A6

1A7

1A8

1B1

1 B2

1B3

1 B4

1 B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2 A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2 B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

U17

S N74

LVTH

1624

5A

7 1 83 142 47 4 6 44 43 41 4 0 38 3 7

2 3 5 6 8 9 11 1 236 3 5 33 32 30 29 2 7 2 6

13 1 4 16 17 19 20 2 2 2 3

4 8 1 25 2 4 4 10 1 5 2 1

2 8 34 3 9 4 5

V cc

Vcc

Vcc

V cc

1 A1

1A2

1A3

1A4

1A5

1 A6

1 A7

1A8

1 B1

1B2

1B3

1B4

1B5

1 B6

1 B7

1B8

2 A1

2A2

2A3

2A4

2 A5

2A6

2 A7

2A8

2 B1

2B2

2B3

2B4

2 B5

2B6

2 B7

2B8

1OE

1 DIR

2OE

2 DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

C14

0.1

C16

0.1

C17

0.1

C15

0.1

R15

22

U5

S N74

LVTH

1624

5A

7 1 83 14 2 4 7 46 44 43 4 1 40 3 8 37

2 3 5 6 8 9 1 1 123 6 35 33 32 30 2 9 2 7 2 6

1 3 14 16 17 19 2 0 2 2 2 3

4 8 1 2 5 24 4 1 0 1 5 2 1

28 3 4 3 9 4 5

Vcc

V cc

V cc

Vcc

1A1

1A2

1A3

1A4

1 A5

1 A6

1A7

1 A8

1B1

1B2

1B3

1B4

1 B5

1 B6

1B7

1 B8

2A1

2A2

2A3

2 A4

2A5

2 A6

2A7

2 A8

2B1

2B2

2B3

2 B4

2B5

2 B6

2B7

2 B8

1 OE

1DIR

2 OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

C18

0 .1

C21

0 .1

C19

0 .1

R13

10K

C20

0 .1

R14

1K

C94

0 .1

C96

0 .1

C11

6

0 .1

C11

5

0 .1

C11

8

0.1

C98

0.1

C99

0.1

C11

7

0.1



DA

UGH

TER

CAR

D I/

F

Exte

rnal

Mem

ory

Inte

rface

Exte

rnal

Per

iphe

ral I

nter

face

5059

42C

TMS3

20C

6416

DSK

B

914

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

DC

_D27

DC

_D11

DC

_D19

DC

_D9

DC_

A2

DC

_A18

DC

_A12

DC

_D5

DC

_D17

DC

_A14

DC

_A10

DC

_A17

DC

_D15

DC

_A19

DC

_D3

DC

_A21

DC

_D7

DC_

A6

DC

_A16

DC

_D13

DC

_A13

DC_

A3

DC

_D21

DC_

A9

DC

_D29

DC

_D23

DC_

A4D

C_A5

DC

_A15

DC

_D1

DC_

A7

DC

_A11

DC

_A20

DC

_D25

DC_

A8

DC

_D20

DC

_D4

DC

_D31

DC

_D18

DC

_D22

DC

_D14

DC

_D2

DC

_D30

DC

_D6

DC

_D24

DC

_D26

DC

_D28

DC

_D16

DC

_D10

DC

_D0

DC

_D12

DC

_D8

DC

_DR

0(5

)DC

_CLK

S0( 5

)

DC

_EIN

T7(2

)

DC

_CLK

X0( 5

)

DC

_CLK

R2

(5)

DC

_A[2

1..2

]( 9

)

DC

_CN

TL0

(2)

DC

_BE3

#( 9

)

DC

_AO

E#( 9

)D

C_C

E2#

(9)

DC

_BE0

#(9

)

DC

_CLK

X2(5

)

DC

_TO

UT0

( 2)

DC

_FSR

2(5

)

DC

_CN

TL1

( 2)

DC

_TO

UT1

(2)

DC

_RS

T#( 2

)

DC

_EIN

T4(2

)

DC

_AW

E#(9

)

DC

_DR

2( 5

)

DC

_BE1

#(9

)

DC

_FSX

2( 5

)

DC

_EIN

T5( 2

)

DC

_EC

LKO

UT

( 9)

DC

_FSR

0(5

)

DC

_TIN

P0( 2

)

DC

_AR

DY

( 9)

DC

_CLK

S2( 5

)

DC

_DX0

(5)

DC

_FSX

0( 5

)

DC

_CE3

#(9

)

DC

_EIN

T6( 2

)

DC

_CLK

R0

( 5)

DC

_D[3

1..0

]( 9

)

DC

_TIN

P1( 2

)

DC

_AR

E#(9

)

DC

_DX2

( 5)

DC

_BE2

#( 9

)

DC

_DET

( 2)

DC

_STA

T1(2

)D

C_S

TAT0

(2)

DG

ND

DG

ND

DG

ND

DG

ND

- 12V

1 2V

3.3V

5V

3.3V

5V

3.3V

3.3V

5V5V

3.3V

3.3V

R16

4.7K

R2

0

R65

10K

J4

CO

NN

ECTO

R 4

0 X

212

34

56

78

91 0

1 11 2

1 31 4

1 51 6

1 71 8

1920

2 12 2

2324

2 52 6

2728

2 93 0

3 13 2

3 33 4

3536

3 73 8

3940

4 14 2

4 34 4

4 54 6

4 74 8

4 95 0

5 15 2

5 35 4

5556

5 75 8

5960

6 16 2

6364

6 56 6

6768

6 97 0

7172

7 37 4

7576

7778

7980

12

34

56

78

91 0

1112

1 31 4

1516

1 71 8

1920

2 12 2

2324

2 52 6

2 72 8

2930

3132

3 33 4

3 53 6

3 73 8

3 94 0

4 14 2

4 34 4

4 54 6

4748

4 95 0

5152

5 35 4

5556

5758

5960

6 16 2

6364

6566

6768

6970

7172

7374

7576

7778

7980

J3

CO

NN

ECTO

R 4

0 X

212

34

56

78

91 0

1 11 2

1 31 4

1 51 6

1 71 8

1920

2 12 2

2324

2 52 6

2728

2 93 0

3 13 2

3 33 4

3536

3 73 8

3940

4 14 2

4 34 4

4 54 6

4 74 8

4 95 0

5 15 2

5 35 4

5556

5 75 8

5960

6 16 2

6364

6 56 6

6768

6 97 0

7172

7 37 4

7576

7778

7980

12

34

56

78

91 0

1112

1 31 4

1516

1 71 8

1920

2 12 2

2324

2 52 6

2 72 8

2930

3132

3 33 4

3 53 6

3 73 8

3 94 0

4 14 2

4 34 4

4 54 6

4748

4 95 0

5152

5 35 4

5556

5758

5960

6 16 2

6364

6566

6768

6970

7172

7374

7576

7778

7980


A-11

3.3

sq in

AG

ND,

min

ther

mal

pad

Con

nect

at p

in 1

S ets

Vol

tage

3.3V

@1.

5Am

p M

ax

3.3

sq in

AG

ND,

min

ther

mal

pad

1.4V

@1.

5Am

p M

ax

Con

nect

at p

in 1

WARN

ING:

DO N

OT S

UPPL

Y PO

WER

TO B

OTH

POWE

R CO

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AT

THE

SAME

TIM

E!

T O B

E PO

PULA

TED

BY

THE

USE

R IF

NEE

DED

.

Mol

ex 1

5-24

-404

1

2.5

MM

JAC

K

POW

ER IN

PUT

DAUG

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CARD

STA

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ING

KEEP

TR

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A M

INIM

UM

OF

0.07

0 IN

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OM

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WER

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PRU

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z

3.3V

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z

1.09

W

0.52

W

0.77

8A

0.15

7A (

no e

mif

clk)

MEA

SUR

ED C

URR

ENT

ON

C64

16TE

B, ~

0.7A

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EA

CH

REG

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TOR

CAN

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PPLY

UP

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A O

FC

UR

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T. H

OW

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CO

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HAV

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OPE

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0.

EM

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M P

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E.D

SP P

OW

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512

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LAN

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FOLL

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5431

0 EV

M L

AYO

UT

1 .4V

-> 1

7.4K

1%

1 .2V

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1%

1 .1V

-> 4

2.2K

1%

OPT

ION

AL C

RO

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REM

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0.02

5 O

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S FO

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ERM

EASU

REM

ENT

5059

42D

TMS3

20C

6416

TEB

B

1014

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

SEN

SE_D

SP_C

VDD

SVS_

RST

#(2

)

DSP

IO_3

.3V

DSP

_CVD

D

AGND

3.3V

AGND

3.3V

5 V

-12V

12V

DG

ND

DG

ND

DSP

IO_3

.3V

DSP

_CVD

D

DG

ND

DG

ND

5 V

U7

T PS5

4310

PWP

1 2 3 4 5 6 7 8 9 1 01 11 21314151 61 7181 92021

AGND

V SEN

SEC

OM

PPW

RG

DB O

OT

PH1

P H2

PH3

P H4

PH5

PGN

D1

P GN

D2

PGN

D3

VIN1

VIN2

VIN3

VBIA

SS S

/EN

AS Y

NC

RT

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D

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1 000

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C63

0 .1u

FC

64

0 .1u

F

+C

T9

1 0uF

LES

R

U2

TPS5

4310

PWP

1 2 3 4 5 6 7 8 9 1 01 112131 4151 61 7181 9202 1

AGND

V SEN

SEC

OM

PP W

RG

DB O

OT

PH1

PH2

PH3

PH4

PH5

PGN

D1

PGN

D2

PGN

D3

VIN1

VIN2

VIN3

V BIA

SSS

/EN

AS Y

NC

RT

POW

ERPA

D

C2

560p

F

C3

0.04

7uF

L12 .

7 uH

C9

0.1u

FC

7

0 .1u

F

+C

T3

1 0uF

LES

R

L2

BLM

41P

750S

PT

C4

0.01

uF

TP32

T est

Poi

nt

1

C1

1000

pF

R6

1 7.4

K 1%

+C

T210

0uF

4V

R7 10

K 1%

R8

1 07

1%C

53 3

00pF

R5

1.65

K 1%

D12

MU

RS1

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L 32 .

7 uH

C10

0 .04

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C12

7

NO

-PO

P

J 5 RAS

M71

2

CEN

TER

SHU

NT

SLEE

VE

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1%

R20

107

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3733

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C12

470p

FR11

2K 1

%C

3682

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R1 0

3 .74

K 1%

+C

T4

1 00u

F 4V

R38 10

K

+C

T16

4 7uF

R9

7 1.5

KC

6

0.1u

F

R3 1

7 1.5

K 1%

C65

0.1u

F

R66

0

C66

0.03

9uF

JP2

NO

-PO

P

12

J P1

NO

-PO

P

12

R99

0 J P4

NO

-PO

P

12

R4

0

D3

GR

EEN

C8

0.03

9uF

M4

125_

PHM

212

5_PH

M3

125_

PHM

112

5_PH

+C

T15

1 00

uF

+C

T1

100

uF

R34

6N

UR

347

NU

T P31

TP

T P2

TPTP1

TP

L4

B LM

41P

750S

PT

J6

NU

1234

+12

-12

GN

D+5

R52

1 80

D13

MU

RS1

20T3

D14

MU

RS1

20T3

D15

MU

RS1

20T3

D16

MU

RS1

20T3



DSP

PO

WER

& D

ECO

UPL

ING

All

capa

cito

rs o

n th

is s

heet

are

dec

oupl

ing

capa

cito

r s fo

r the

DSP

. The

y sh

ould

be

plac

ed a

s cl

ose

as p

ossi

ble

to th

e D

SP.

5059

42B

TMS3

20C

6416

DSK

B

1114

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

DSP

IO_3

.3V

DSP

_CVD

D

DG

ND

DG

ND

DG

ND

DG

ND

DS P

IO_3

.3V

DS P

IO_3

.3V

DSP

IO_3

.3V

DS P

_CVD

DD

S P_C

VDD

DS P

_CVD

D

DSP

_CVD

D

DS P

IO_3

.3V

DSP

IO_3

.3V

C76

0.1

U1 0

H

TMS3

20C

6416

GLZ

A2 A 25 B1 B 14

B26 E 7 E8 E10

E 17

E 19

E20 F 9 F12

F15

F18

G5

G2 2 H

5H

2 2 J 21 K5 K22

M6

M21 N

2

P25

R21

U5

U22

V6 V21

W5

W22

Y5 Y 22

AA9

AA12

AA15

A A18

AB7

A B8

AB10

A B17

AB19

AB20

AE1

AE13

A E26

A F2

A F25

L5 M5

T 5R5

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DV D

DD

VDD

DV D

DD

VDD

DVD

DD

V DD

DVD

DD

VDD

DV D

DD

VDD

DVD

DD

VDD

DVD

D

DVD

D

DVD

D

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DV D

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

D

DVD

DD

VDD

DVD

D

DVD

D

U1 0

I

TMS3

20C

6416

GLZ

A8 A 19 B3 B 13

B24

C2

C4

C23

C25 D

3D

5D

22D

24 E4 E6 E 9 E18

E 21

E23 F 5 F8 F10

F11

F13

F 14

F 16

F 17

F 19

F 22

G9

G12

G15

G18 H

1H

6H

21H

26 J5 J 7 J20

J 22

K 21 L 6 L 21

M7

M20 N

6N

21N

25 P2

P6 P 21

R7

R20

T6 T 21

U6

U21

V 5 V 7 V20

V 22

W1

W6

W2 1

W26

Y9 Y 12

Y15

Y 18

AA5

AA8

AA10

AA11

A A13

A A14

A A16

A A17

A A19

AA22

A B4

AB6

A B9

AB18

A B21

A B23

A C3

AC5

A C22

AC24

A D2

A D4

A D23

A D25

A E3

A E14

A E24

AF8

A F19

VSS

V SS

V SS

VSS

VSS

V SS

V SS

V SS

VSS

V SS

V SS

VSS

VSS

VSS

VSS

V SS

V SS

VSS

V SS

VSS

VSS

VSS

V SS

VSS

V SS

VSS

V SS

VSS

V SS

VSS

V SS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

C52

0.1

C10

20.

1

C11

00.

1C

880.

1

C78

0.1

C24

0.1

C10

40.

1

C10

30.

1

U1 0

G

TMS3

20C

6416

GLZ

A1 A 26 B2 B 25

C3

C24 D

4D

23 E 5 E 22 F6 F 7 F20

F21

G6

G7

G8

G10

G1 1

G13

G16

G17

G1 9

G20

G21

H20 K 7 K 2

0 L 7 L20

N7

P20

T7 T 20

U7

U20

W7

W20

Y6 Y7 Y 8 Y 10

Y11

Y 14

Y16

Y17

Y19

Y 20

Y21

A A6

AA7

A A20

AA21

AB5

AB22

AC4

A C23

A D3

A D24

A E2

A E25

AF1

A F26

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CV D

DC

VDD

CV D

DC

VDD

CVD

DC

V DD

CVD

DC

VDD

CV D

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

D

C25

0.1

C62

0.1

C30

0 .1

C10

50 .

1

C11

10.

1

C10

80 .

1

C10

90.

1

C32

0 .1

C77

0 .1

C50

0 .1

C58

0.1

C46

0 .1

C79

0 .1

C49

0 .1

C91

0 .1

C10

70 .

1

C90

0.1

C60

0 .1

C34

0.1

C61

0 .1

C31

0.1

C57

0 .1

C87

0 .1

C89

0 .1

C84

0.1

C35

0.1

+C

T6 10

C10

10.

1

C80

0.1

C55

0.1

+C

T8 10

C48

0.1

C86

0.1

C56

0.1

+C

T11

1 0+

CT1

41 0

+C

T7 1 0

C85

0.1

C10

60.

1

C53

0.1

C11

20.

1

U10

J

TMS3

20C

6416

GLZ

F 3 A3 G2

G14 H

3H

7 J 4 K6

N3

N20

P 3 P7 R6

W2 5

Y 13

RSV

RSV

RSV

RS V

RSV

RS V

RSV

RSV

RSV

RSV

RSV

RS V

RSV

RS V

RSV

C33

0.1

+C

T12

10

C54

0.1

C47

0.1

C26

0.1

C81

0.1

C27

0.1

C23

0.1

C82

0.1

C10

00.

1

C83

0.1

C59

0.1

C29

0.1

C51

0.1


A-13

J TAG

MUL

TIPL

EXER

S

EMU

LATI

ON

DSP

JTAG

HEA

DER

ROUT

E TR

ACES

AS

O NE

GRO

UP. M

ATC H

S IG

N AL L

ENG

TH.

LOC

ACTE

R-P

ACK

NEA

R D

SP

USB

IN U

SE

5059

42B

TMS3

20C

6416

DSK

B

1214

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

X DS_

TRST

#T_

TMS

XDS_

EMU

1

X DS_

TDO

X DS_

TMS

XDS_

EMU

0

XDS_

TVD

XDS_

TDI

T_EM

U1

X DS_

4.1V

T_EM

U0

HU

RR

ICAN

E_D

ETn

HU

R_E

MU

9H

UR

_EM

U8

HU

R_E

MU

3H

UR

_EM

U2

HU

R_E

MU

5H

UR

_EM

U4

HU

R_E

MU

7H

UR

_EM

U6

HU

R_E

MU

1H

UR

_EM

U0

MU

X_EM

U0

MU

X_EM

U1

HU

R_E

MU

10H

UR

_EM

U11

HU

R_T

CK

HU

R_T

CKR

TN

T_TR

STn

T_TC

K

HU

RR

ICAN

E_D

ETn

XDS_

TCKR

ET

XDS_

TCK

T_TC

K_R

ET

T _TD

O

T _TD

I

DSP

_TD

O(2

)D

SP_T

DI

(2)

DSP

_TM

S(2

)

T_E

MU

0

T_E

MU

1

DSP

_EM

U9

(2)

DSP

_EM

U8

( 2)

DSP

_EM

U2

(2)

DSP

_EM

U7

( 2)

DS P

_EM

U3

(2)

DSP

_EM

U5

(2)

DSP

_EM

U4

( 2)

DSP

_EM

U6

( 2)

T_TC

K_R

ET

DSP

_EM

U0

(2)

DSP

_EM

U1

( 2)

DSP

_EM

U10

(2)

DS P

_EM

U11

(2)

DSP

_TC

K( 2

)

DSP

_TR

ST#(2

)

T _T M

S

T_TC

K

T_TR

STn

X DS_

4.1V

T_TD

O

T _TD

I

DG

ND

3 .3V

DG

ND

DG

ND

DG

ND

3 .3V

DG

ND

5V

DG

ND

DG

ND3.

3V

DG

ND

3 .3V

DG

ND

DG

ND

DG

ND

3 .3V

3.3V

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

DG

ND

3.3V

RN

2C42

RN

2D42

RN

1E4 2

RN

1D4 2

U24

SN74

LVC

1G32

1 24

5 3

R96

33

R92

33

R93

1.6K

D5 LM

4040

DCI

M3-

4.1

21

RN

2B4 2

RN2

A42

C12

2.1

uF

R89

150

U26 SN

74LV

C1G

321 2

4

5 3

R95

100

1%

C12

6

22pF

J8

HEA

DER

7x2

, Em

ulat

ion

1 3 5 7 9

2 4 8 101 1

1 213

14

R67

4 7K

R90

47K

C12

4.1

uF

U19

S N74

CBT

3257

PW

4

1 4

71 1

9 1 21 3 12 151 03 5 6

1 6 8

1 A

4B1

2 A3 B

13 A 4 A

4 B2

S1 B1

OE

3 B2

1 B2

2 B1

2 B2

V CC

GN

D

U25

SN74

CBT

3257

PW

4

14

711

9 1213 12 15103 5 6

1 6 8

1A

4B1

2A3B

13A 4A

4B2

S1 B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

J7 HEA

DER

4x1

5

A 1 A2 A 3 A4 A 5 A6 A7 A8 A9 A 10

A 11

A 12

A 13

A 14

A15

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

B14

C14B1

3C

13 B 12

C12B 1

1C

11B 10

C10B 9C

9 B 7C7B6C6B 5C5 B4C4B3 C3B 2C2 B 1B 15

C1

C15 B 8C

8

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DT Y

PE0

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DT Y

PE1

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

E MU

0E M

U1

EMU

2E M

U3

TCLK

EMU

4E M

U5

EMU

6E M

U7

EMU

8E M

U9

EMU

10

T DO

E MU

11EM

U12

EMU

13EM

U14

E MU

15

T DI

EMU

16E M

U17

T RST

nT M

S

E MU

18

ID0

I D1

I D2

I D3

T VD

TCKR

TN

D4

LTS

T-C

150G

KT

R9 4

30.1

K

R88

1K

C12

3

0 .1

U23

SN74

LVC

1G32

1 24

5 3

U22

SN74

AHC

1G14

3

4

5

2

U18 S N

74AH

C1G

14

3

4

5

2

RN

1G4 2

RN

1F42

RN

2H42

RN

1B42

RN1

A4 2

RN

1C42

RN

2G42

RN

2F4 2

RN

2E4 2

R91

1K

C12

5

0 .1



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Hier

arch

aric

al B

lock

s

5059

42A

TMS3

20C6

416

DSK

B

1314

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

USB

/Em

ulat

ion

USB

/Em

ulat

ion

5V

USB

_DSP

_RST

#

T_TD

O

T_TC

KT_

TMS

T_TR

STn

T_E

MU

0T_

EM

U1

T_TD

I

3.3V

PON

RSn

GN

D

T_TC

K_R

ET

CLK

_12M

HZ

CLK

_24M

HZ

AIC

23 A

udio

AIC

23 A

udio

GN

D

DAT

A_BC

LKD

ATA_

SYN

CIN

DAT

A_DI

ND

ATA_

DO

UT

CTL

_DAT

AC

TL_C

LKC

TL_C

S

CO

DEC

_SYS

CLK

AIC

3.3V

DAT

A_SY

NC

OU

T

CLK

_12M

HZ

USB

_DSP

_RST

#

T_TD

IT_

TMS

T_TC

K

T_E

MU

0T_

EM

U1

T_TD

OSV

S_R

ST#

T_TR

STn

T_TC

K_R

ETC

TL_C

LKX1

CTL

_FSX

1

CTL

_DX1

BCLK

AIC

23SD

ATAO

UT

LRC

OU

T

AIC

23SD

ATAI

NLR

CIN

CO

DEC

_CLK

5V

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

U11

SN74

LVC

1G32

1 24

5 3

C67

.1uF

R32

33


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Con

trol P

ort

AU

DIO

5059

42A

TMS3

20C

6416

DSK

B

1414

Tues

day,

Apr

il 01

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

LLIN

E_O

UT

RLI

NE_

OU

T

AIC

23LR

CIN

AIC

23CS

SPIM

OD

E

3.3V

A

3.3V

A

AIC

3.3V

AIC

3.3V

AIC

3.3V

AIC

3.3V

AIC

3.3V

+

C32

510

uF

C32

60.

1uF+

C31

910

uF

C32

20.

1uF

R32

52.

2K

R32

8N

O P

OP

R32

64.

7K

R33

74.

7K

R33

44.

7K

R33

64.

7K

R33

54.

7K

C34

1

0.1u

F

+C32

3220

uF

+ C32

4220

uF

L306

BLM

21P2

21SN

C34

0N

O P

OP

C34

4N

O P

OP

C34

5N

O P

OP

R34

30

C32

1

47pF

+

C31

5

1uF

L307

BLM

21P2

21SN

C33

9N

O P

OP

C33

847

0nF

J302

Hea

d Ph

one

Out

3 4 2 1

C34

2

0.1u

F

R33

247

KC

333

470n

F

C33

447

0nF

R33

347

KJ3

03

Line

In

3 4 2 1

R34

533

C33

20.

1uF

J301

Mic

roph

one

In

3 4 2 1

+C

343

10uF

C33

747

0nF

R31

20

C33

6N

O P

OP

L305

BLM

21P2

21SN

C32

9N

O P

OP

+

C33

110

uF

J304

Line

Out

3 4 2 1

R34

1 47K

R34

2 47K

R33

910

0

R33

80

L304

BLM

21P2

21SN

C33

0N

O P

OP

C33

5N

O P

OP

RN

314

10K

1 2 3 45678

RN

316

33

1 2 3 45678

R34

010

0

PW P

acka

geU

307 TL

V320

AIC2

3

22141115 25

34 5 212423

10 9 28

16 17 18 20 19

26 13 12

8

167

2 27

MO

DE

AVdd

HPG

ND

AGND

XTI/M

CLK

BCLK

DIN

LRCI

N

CS

SCLK

SDIN

RH

POU

TLH

PO

UT

DG

ND

VMID

MIC

_BIA

SM

IC_I

NLL

INE_

INR

LIN

E_IN

XTO

RLI

NE_

OU

TLL

INE_

OU

T

HPV

dd

BVdd

DO

UT

LRC

OU

T

CLK

OU

T

DVd

d

L308

BLM

21P2

21SN

L303

BLM

21P2

21SN

C31

8N

O P

OP

R34

42.

2

L301

HZ0

805E

601R

R32

70

C32

0N

O P

OP

L309

BLM

21P2

21SN

C31

7N

O P

OP

C31

6N

O P

OP

C32

7N

O P

OP

R33

10

+C

347

10uF

+C

346

10uFL3

02BL

M21

P221

SN

C32

8N

O P

OP

RN

315

10K

1 2 3 45678

CTL

_CLK

CTL

_CS

CTL

_DAT

A

DAT

A_DI

ND

ATA_

SYN

CIN

DAT

A_BC

LKD

ATA_

DO

UT

DAT

A_SY

NC

OU

T

CO

DEC

_SYS

CLK

AIC

3.3V

GN

D



B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about theTMS320C6416 DSK produced by Spectrum Digital.


B-2 TMS320C6416 DSK Module Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE

Printed in U.S.A., April 2003505945-0001 Rev. A

Date post:	31-Dec-2016
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