TMS320VC5416 DSK Technical Reference -...

TMS320VC5416 DSK

2002 DSP Development Systems

ReferenceTechnical

TMS320VC5416 DSK Technical Reference

506005-0001 Rev. A March 2002

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2002 Spectrum Digital, Inc.

Contents

1 Introduction to the TMS320VC5416 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320VC5416 DSK Module, key features, and board outline. 1.0 Overview of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1 Key Features of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 Operation of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the TMS320VC5416 DSK. Information is provided on the DSK’s various interfaces. 2.0 The TMS320VC5416 DSK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1 The TMS320VC5416 DSK Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2 TMS320VC5416 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.3 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.4 Interface CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.4.1 CPLD Control Registers and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4.4.1.1 DSP USER_REG Register (I/O Address 0x0000) . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.4.1.2 DSP Daughter Card Register (I/O Address 0x0001) . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.4.1.3 DSP CODEC_L_CMD (I/O Address 0x0002) and . . . . . . . . . . . . . . . . . . . . . . 2-13 CODEC_H_CMD Register (I/O Address 0x0003) 2.2.4.1.4 Version Register (I/O Address: 0x0004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.2.4.1.5 DSP DM_CNTL Register (I/O Address 0x0005) . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.4.1.6 MISC Register (I/O Address 0x0006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.4.1.7 CODEC_CLK Register (I/O Address: 0x0007) . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.2.5 Flash ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.2.6 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.2.7 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.2.7.1 Programming the Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.2.7.2 Programming the Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.2.7.3 PCM3002 Codec Input/Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.2.8 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.2.8.1 Program Space Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.2.8.2 Data Space Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.2.8.2.1 Data Space 32 Bit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.2.8.3 I/O Space Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.2.8.3.1 I/O Space 32 Bit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.2.9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.2.9.1 Software Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.3 TMS320VC5416 DSK Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2.3.1 JP4, DSP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2.4 TMS320VC5416 DSK Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.4.1 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.4.2 P1, Memory Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.4.3 P2, Peripheral Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.4.4 P3, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.4.5 J1, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.4.6 J2, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.4.7 J3, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.4.8 J4, Headphones/Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.4.9 J5, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.4.10 J6, +5 Volt Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.4.11 J7, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.4.12 JP1, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.5 User LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.5.1 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.6 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.6.1 Reset Switch/Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.6.2 4 Position User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.7 J201, Universal Serial Bus (USB) Embedded JTAG Emulation Connector . . . . . . . 2-46A TMS320VC5416 DSK CPLD Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Lists the VHDL for CPLD U18, used on the TMS320VC5416 DSK A.1 CPLD Equations for VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2B TMS320VC5416 DSK Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the schematics for the TMS320VC5416 DSKC TMS320VC5416 DSK List of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Contains the list of materials used to build the TMS320VC5416 DSKD TMS320VC5416 DSK Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Contains the mechanical information about the TMS320VC5416 DSK

About This Manual

This document describes the board level operations of the TMS320VC5416 DSPStarter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320VC5416 Digital Signal Processor.

The TMS320VC5416 DSK is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320VC5416 DSP to determineif the processor meets the designers application requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The TMS320VC5416 will sometimes be referred to as the C54XX.

The TMS320VC5416 DSK will sometimes be referred to as the DSK.

Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320VC54XX Users GuideTexas Instruments TMS320VC54XX Fixed Point Assembly Language Users GuideTexas Instruments TMS320VC54XX Fixed Point C Language Users GuideTexas Instruments TMS320VC54XX Code Composer Studio Users Guide

Table 1: Hardware History

Revision History

B Beta Release

C Production Release

Table 2: Manual History

Revision History

A Beta Release

1-1

Chapter 1

Introduction to the TMS320VC5416 DSK

Chapter One provides a description of the TMS320VC5416 DSK alongwith the key features and a block diagram of the circuit board.

Topic Page

1.0 Overview of the TMS320VC5416 DSK 1-21.1 Key Features of the TMS320VC5416 DSK 1-21.2 Functional Overview of the TMS320VC5416 DSK 1-3

Spectrum Digital, Inc

1-2 TMS320VC5416 DSK Module Technical Reference

1.0 Overview of the TMS320VC5416 DSK

The TMS320VC5416 DSK is a stand-alone development and evaluation module. Itallows evaluators to examine certain characteristics of the C5416 digital signalprocessor (DSP) to determine if it meets their application requirements. Furthermore,the module is an excellent platform to develop and run software for theTMS320VC5416 family of processors.

The DSK allows full speed verification of VC5416 code. With 64K words of on boardRAM memory, 256K words of on board Flash ROM, and a Burr Brown PCM 3002stereo codec, the board can solve a variety of problems as shipped. Three expansionconnectors are provided for interfacing to evaluation circuitry not provided on the asshipped configuration.

To simplify code development and shorten debugging time, a special version of CodeComposer Studio is shipped with the board.

1.1 Key Features of the TMS320VC5416 DSK

The VC5416 DSK has the following features:

• VC5416 operating at 16-160 MHz.

• On board USB JTAG controller with plug and play drivers

• 64K words of on board RAM

• 256K words of on board Flash ROM

• 3 Expansion Connectors (Memory Interface, Peripheral Interface,and Host Port Interface)

• On board IEEE 1149.1 JTAG Connection for Optional Emulation Debug

• Burr Brown PCM 3002 Stereo Codec

• +5 volt operation


1-3

1.2 Functional Overview of the TMS320VC5416 DSK

Figure 1-1 shows a block diagram of the basic configuration for the VC5416 DSK. Themajor interfaces of the DSK include the target RAM and ROM interface, FPGAinterface, Codec interface, and expansion interface.

The VC5416 interfaces to 64K words of on board RAM and 256K words of Flash ROM.An external I/O interface supports parallel I/O ports and multi channel bufferedsynchronous serial ports. A Flash Boot ROM is mapped into data memory space.Four stereo jacks provide input and outputs to and from the codec.

JTAG

DATA

ADDRESS

CONTROL

TMS320VC5416

FlashROM

256K x 16

SRAM

64K x 16

EXPANSION

ADDRESS/DATA

Figure 1-1, BLOCK DIAGRAM, TMS320VC5416 DSK

User

Switch

UserLEDs

HPI -IO

/CONTROL

EXPANSION

EmbeddedUSBJTAG

Controller

STEREOCODEC

HPIEXPANSION

DECODE

FPGA

DATA

McBSP

McBSP

McBSP



2-1

Chapter 2

Operation of the TMS320VC5416 DSK

This chapter describes the operation of the TMS320VC5416 DSK, the keyinterfaces and an outline of the circuit board.

Topic Page

2.0 The TMS320VC5416 DSK Operation 2-32.1 The TMS320VC5416 DSK Board 2-32.1.1 Power Connector 2-42.2 TMS320C5416 DSK Memory Interface 2-52.2.1 Program Memory Interface 2-82.2.2 Data Memory 2-92.2.3 I/O Space 2-102.2.4 Interface CPLD 2-112.2.4.1 CPLD Control Registers and Status Registers 2-112.2.4.1.1 DSP USER_REG Register (I/O Address 0x0000) 2-122.2.4.1.2 DSP Daughter Card Register (I/O Address 0x0001) 2-122.2.4.1.3 DSP CODEC_L_CMD (I/O Address 0x0002) and 2-13

CODEC_H_CMD Register (I/O Address 0x0003)2.2.4.1.4 Version Register (I/O Address: 0x0004) 2-132.2.4.1.5 DSP DM_CNTL Register (I/O Address 0x0005) 2-142.2.4.1.6 MISC Register (I/O Address 0x0006) 2-162.2.4.1.7 CODEC_CLK Register (I/O Address: 0x0007) 2-172.2.5 Flash ROM Interface 2-182.2.6 SRAM Interface 2-212.2.7 Codec Interface 2-242.2.7.1 Programming the Codec Interface 2-252.2.7.2 Programming the Data Interface 2-252.2.7.3 PCM3002 Codec Input/Output Circuitry 2-26



Topic Page

2.2.8 Daughter Card Interface 2-272.2.8.1 Program Space Accesses 2-272.2.8.2 Data Space Accesses 2-282.2.8.2.1 Data Space 32 Bit Accesses 2-292.2.8.3 I/O Space Accesses 2-302.2.8.3.1 I/O Space 32 Bit Accesses 2-312.2.9 Wait States 2-322.2.9.1 Software Wait State Generator 2-322.3 TMS320VC5416 DSK Jumpers 2-362.3.1 JP4, DSP Clock and Mode Configuration 2-362.4 TMS320VC5416 DSK Connectors 2-372.4.1 Expansion Connectors 2-372.4.2 P1, Memory Expansion Connector 2-382.4.3 P2, Peripheral Expansion Connector 2-392.4.4 P3, HPI Expansion Connector 2-402.4.5 J1, Microphone Connector 2-412.4.6 J2, Audio Line In Connector 2-412.4.7 J3, Audio Line Out Connector 2-412.4.8 J4, Headphone/Speaker Connector 2-422.4.9 J5, Optional Power Connector 2-422.4.10 J6, +5 Volt Connector 2-422.4.11 J7, External JTAG Connector 2-432.4.12 JP1, PLD Programming Connector 2-442.5 User LEDs 2-442.5.1 System LEDs 2-442.6 Switches 2-452.6.1 Reset Switch/Reset Logic 2-452.6.2 4 Position User DIP Switch 2-452.7 J201, Universal Serial Bus (USB) Embedded JTAG 2-46

Emulation Connector


2-3

2.0 The TMS320VC5416 DSK Operation

This chapter describes the VC5416 DSK module, key components, and how theyoperate. It also provides information on the DSK’s various interfaces.The VC5416DSK consists of five major blocks of logic.

• C5416 External memory • Codec Interface• CPLD Registers and Interface• Expansion interface• JTAG Interface

2.1 The TMS320VC5416 DSK Board

The VC5416 DSK is a 8.25 x 4.5 inch (210 x 115 mm.) multi-layer board which ispowered by an external +5 volt only power supply. Figure 2-1 shows the layout of the VC5416 DSK.



2.1.1 Power Connector

The VC5416 DSK is powered by a +5 volt only, 3 amp power supply which is availablewith the module. The typical board current requirements, without expansions boards, is0.5 - 0.75 amps. The power is supplied via 2.5 millimeter jack JP6. If expansion boardsare connected to the module a higher amperage power supply may be necessary. Theboard also has a +3.3 and +1.6 volt regulator to provide power to the lower voltagecomponents.

Figure 2-1, TMS320VC5416 DSK

P1

JP4

J2

J5J6

J1

P2

P3

JP1

J3 J4

J7 S1 TP6-9D9-12 S2J201


2-5

2.2 TMS320C5416 DSK Memory Interface

The DSK includes 64K words of SRAM. The board also features 256K words flashROM for boot loading.

It is important to remember that internal memory has a higher precedence than theexternal memory. For more information on the memory in the device populated in yourDSK card please refer to Texas Instruments TMS320C54XX Users Guide orTMS320VC5416 data sheet. Futhermore, it is important to take into account thatexternal memory is affected by wait-states. Wait state generation for off-chip memoryspace (data, program, or I/O) is done with the Software Wait State GenerationRegister(SWWSR). To obtain wait states for off-chip memory, bits in the SWWSR mustbe appropriately programmed. The board powers up with maximum wait-states. TheDSK board does not generate wait states via the ready signal for external programmemory, data memory, or I/O accesses.

External memory decode is done via CPLD U8. The complex program logic deviceselects the RAM, FLASH ROM, or on board peripherals. The VHDL for the CPLD areincluded in Appendix A.

The internal PMST register (Processor Mode Status Register) greatly affects thememory decode for the VC5416 and VC5416 DSK. The user should be familiar withthis register to help in the understanding of the DSK’s operation. The figure belowshows the bit fields of the PMST register and a brief description of the register’sfunction bits.

The bit fields in PMST are described in the table below.

Table 1: PMST Bit Field Definition

Bit #Bit

NameReset Value

Function

15-7 IPTR 1FFh

Interrupt vector pointer - The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in the program memory space. The RESET instruction does not affect this field.

SSTSMULCLKOFFDROMAVISOVLYMP/MCIPTR

0123456715

Figure 2-2, Processor Mode Status Register (PMST)

R/W-0 R/W-0R/W-0R/W-0 R/W-0R/W-0MP/MCPin



6 MP/MC MP/MCPin

Microprocessor/microcontroller Mode - MP/MC enables/disables the on-chip ROM to be addressable in program memory space.

- MP/MC = 0: The on-chip ROM is enables and addressable.

- MP/MC = 1: The on-chip ROM is not addressable.

MP/MC is set to the value corresponding to the logic level on the MP/MC pin when samples at reset. This pin is not samples again until the next reset. The RESET instruction does not affect this bit. This can also be set or cleared by software.

5 OVLY 0

RAM overlay. OVLY enables the on-chip dual address dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are:

- OVLY = 0: The on-chip RAM is addressable in data space but not in program space.

- OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (address 0h to 7Fh)., however it not mapped into program space.

4 AVIS 0

Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins.

- AVIS = 0: The external address lines do not change with the internal program address. control and data lines are not affected and the address bus is driven with the last address on the bus.

- AVIS = 1: This mode allows the internal program address to appear at the pins of the 5416 so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside in-chip memory.


Bit #Bit

NameReset Value

Function


2-7

3 DROM 0

DROM - Enables on-chip DARAM4-7 to be mapped into data space. The DROM values are:

- DROM = 0: The on-chip DARAM4-7 is not mapped into data space

- DROM = 1: The on-chip DARAM4-7 is mapped into data space

2 CLKOFF 0 CLKOUT off. When the CLKOFF bit is a 1, the output of the CLKOUT is disabled and remains at a high level

1 SMUL N/ASaturation on multiplication. When SMUL = 1, saturation ofa multiplication result occurs before performing the multiplication in a MAC or MAS instruction. The SMUL bit applies only when the OVM=1 and FRCT=1.

0 SST N/ASaturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation


Bit #Bit

NameReset Value

Function



2.2.1 Program Memory Interface

There are two configurations for program memory. The selection of these configurations is done by the 54X’s OVLY bit. When in OVLY mode, addresses0x0000 - 0x8000 are internal for every page. This is the preferred mode to be used bythe DSK. When in linear mode program memory is mapped externally.

Manual sections 2.2.5 and 2.2.6 show how on-board memory is mapped into theexternal spaces of the processor.

The following figure shows the program memory map for TMS320VC5416.

Figure 2-3, TMS320VC5416 DSK Program Space

Hex

0x0000

0x007F0x0080

0x7FFF

0x8000

0xC0000xBFFF

External

Reserved(OVLY=1) External(OVLY=0)

On-ChipDARAM0-3 (OVLY=1) External (OVLY=0)

0xFF000xFEFF

0xFF800xFF7F

On-Chip ROM(4K x 16 bit)

Reserved

Interrupts(On-Chip)

0xFFFF

MP/MC=0(Microcomputer Mode)

Hex

0x0000

0x007F0x0080

0x7FFF

0x8000

External

Reserved(OVLY=1) External(OVLY=0)

On-ChipDARAM0-3 (OVLY=1) External (OVLY=0)

0xFF7F0xFF80

Interrupts(On-Chip)

0xFFFF

MP/MC=1(Microprocessor Mode)

On-ChipDARAM0-3(OVLY=1External

(OVLY=0)

On-Chip(DARAM4-7(MP/MC=0)

External(MP/MC=1)

ProgramHex

010000

017FFF018000

01FFFF


(OVLY=0)

External

ProgramHex

040000

047FFF048000

04FFFF


(OVLY=0)

On-Chip(SARAM4-7(MP/MC=0)

External(MP/MC=1)

ProgramHex

030000

037FFF038000

03FFFF


(OVLY=0)

On-Chip(SARAM0-3(MP/MC=0)

External(MP/MC=1)

ProgramHex

020000

027FFF028000

02FFFF


(OVLY=0)

External

ProgramHex

7F0000

7FFFFF7F8000

7FFFFF

Page 3XPC=3

Page 2XPC=2

Page 1XPC=1

Page 4XPC=4

Page 127XPC=7Fh

Page 0 Program Page 0 Program


2-9

2.2.2 Data Memory

The external data memory is mapped from 0x8000 to 0xFFFF for the DSK. This allowsa reach of 32K words. The on board CPLD further supplies 5 additional address lines toallow for thirty-two (32), 32K word pages to be accessed in data space. All on boardaccesses are mapped into the processors data memory space from 0x8000 to 0xFFFFand use the extended address lines from the CPLD.

Refer to the section on Data Space Access for how the DSP and CPLD pages addressinteract. The figure below shows the data space memory map for the TMS320VC5416processor.

Figure 2-4, TMS320VC5416 DSK Data Space

Hex

0x0000

0x005F

0x0060

0x007F

0x0080

0x7FFF

0x8000

0xFFFF

Memory-MappedRegisters

Scratch-Pad RAM

On-ChipDARAM0-3

(32K x 16 bit)

On-ChipDARAM4-7(DROM=1)

orExternal

(DROM=0)

Data

Address ranges for on-chip DARAM in data memory are: DARAM0: 0x0080-0x1FFFDARAM1: 0x2000-0x3FFFDARAM2: 0x4000-0x5FFFDARAM3: 0x6000-0x7FFFDARAM4: 0x8000-0x9FFFDARAM5: 0xA000-0xBFFFDARAM6: 0xC000-0xDFFFDARAM7: 0xE000-0xFFFF



2.2.3 I/O Space

The TMS320VC5416 processor has no on-chip I/O accesses. The DSK uses thisspace to access the on board CPLD and expansion connectors for daughter cardaccesses.

The I/O map for the TMS320VC5416 DSK is shown below. The CPLD has eight (8)8 bit registers which control various functions as explained in the “Interface CPLD”section of this manual.

Hex

0x0000

0x0007

0x0008

0x7FFF

0x8000

0xFFFF

Reserved

Figure 2-5, TMS320C5416 I/O Space

CPLD ConfigurationRegisters

Daughter CardAccess


2-11

2.2.4 Interface CPLD

The VC5416 uses a CPLD to interface to the Flash ROM, SRAM, Codec control, andthe Daughter Card Interface. The CPLD is mapped into the I/O address space andcontains eight (8) 8-bit registers as shown below.

2.2.4.1 CPLD Control Registers and Status Registers

There are eight DSP CPLD registers mapped into the DSP's lower I/O address spacestarting at address 0x0000 to 0x0007. Since the CPLD decoder only uses part of theDSP’s Address for decoding, the registers will be mirrored within the I/O spaceaddresses in 64 word increments within the lower 16K of the I/O address space. It isrecommended that the CPLD registers only be accessed at locations 0x0000 to 0x0007so future implementations will not case software changes.

The table below shows the bit definitions for the 8 registers in CPLD.

Note: “R” indicates Read Only, “R/W” indicate Read and Writable

Table 2: CPLD Register Definitions

I/O Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 USER_REG USR_SW3R

USR_SW2R

USR_SW1R

USR_SW0R

USR_LED3R/W

USR_LED2R/W

USR_LED1R/W

USR_LED0R/W

1 DC_REG DC_DETR

DC_IO_CTLR/W

0

DC_STAT1R

DC_STAT0R

DC_RSTR

0(on reset)

0 DC_CNTL1R/W

0(low)

DC_CNTL0R/W

0(low)

2 CODEC_L CODEC_L_CMD[7..0]R/W

0

3 CODEC_H CODEC_H_CMD[15..8]R/W

0

4 VERSION CPLD_VER[3.0]R

0 BOARD VERSION[2.0]R

5 DM_CNTL DM_SELR/W0(int)

MEMTYPE_DSR/W

0(flash)

MEMTYPE_PSR/W

0(flash)

DM_PG4R/W

0(page 0)

DM_PG3R/W

0(page 0)

DM_PG2R/W

0(page 0)

DM_PG1R/W

0(page 0)

DM_PG0R/W

0(page 0)

6 MISC CODEC_RDYR

0(Ready)

0 0 0 0 DC_WIDER/W

0(16 bits)

DC32-ODDR/W

0(even)

BSP2SELR/W

0(CODEC)

7 CODEC_CLK 0 0 0 0 DIV_SELR/W

CLK_STOPR/W

CLK_DIV1R/W

CLK_DIV0R/W



2.2.4.1.1 DSP USER_REG Register (I/O Address 0x0000)

The USER register controls the status of the 4 user LED’s and the state of the 4Position User DIP Switch. The table below summarizes (bold indicates default) thefunction of each bit in the USER_REG register.

2.2.4.1.2 DSP Daughter Card Register (I/O Address 0x0001)

The DC_REG register provides user control of the two daughter card control outputs,the daughter card reset signal, and the status of the two daughter card Status signalsand the Daughter Card Detect Signal. The table below summarizes (bold indicatesdefault) the function of each bit in the DC_REG register.

Table 3: USER_REG Bit Definition

Bit # Name R/W Description

7 USER_SW3 R User DIP Switch S2-4 (1 = Off, 0=On)




3 USER_LED3 R/W User Defined LED D12, Control(0=Off, 1=On)




Table 4: DC_REG Bit Definitions


7 DC_DET R Daughter Card Detection(0=No board, 1=Daughter Card Detected)

6 DC_IO_CTL R/W 0=None, 1=DC_RE-,DC_WE- active on I/O Cycles

5 DC_STAT1 R Daughter Card Status 1 (0=low, 1=high)

4 DC_STAT0 R Daughter Card Status 0 (0=low, 1=high)

3 DC_RST R/W Daughter Card Reset (1=Reset Active Low)

2 0 R Always zero

1 DC_CNTL1 R/W Daughter Card Control 1 (0=low, 1=high)

0 DC_CNTL0 R/W Daughter Card Control 0 (0=low, 1=high)


2-13

2.2.4.1.3 DSP CODEC_L_CMD (I/O Address 0x0002) and CODEC_H_CMD Register (I/O Address 0x0003)

This Read/Write register is use to send command codes to the on board Burr-BrownPCM3002 CODEC. The two 8-bit register form the 16 command word that is to besent to the CODEC. Any read accesses to these two I/O addresses will only read thelast command that was written to the CODEC. Write accesses to I/O address 0x0002will only store the byte into the CODEC_L register. After the completion of a write toI/O address 0x0003, the CPLD will transfer the complete 16-bit command word to the CODEC.

Refer to the PCM3002 data sheet for complete definition of the bits and commands.

NOTE: After each write of CODEC_H register the DSP is required to wait 1millisecond, before writing any data to either location. The user may poll bit 7 of I/Oaddress 0x06 (MISC Register) to determine if the Codec is Ready, this bit contains theCODEC_RDY- bit. When the CODEC_RDY- is equal to zero (0x0), then a newcommand can be written to these command registers. When the CODEC_RDY is equalto one (1), then the previous command in still be shifted into the PCM3002 device.

2.2.4.1.4 Version Register (I/O Address: 0x0004)

This register contains two version codes of the DSK. The CPLD version code is theupper 4-bits of this register. The CPLD version code is coded into the device duringcompilation of the VHDL source. The board version code is read from the lowest 3-bitsof this register. The board version is set during board assembly.

Table 5: Version Register Bit Definitions


7 CPLD_VER3 R Most Significant CPLD Version Bit

6 CPLD_VER2 R CPLD Version Bit

5 CPLD_VER1 R CPLD Version Bit

4 CPLD_VER0 R Least Significant CPLD Version Bit

3 0 R Always 0

2 DSK_VER2 R Most Significant DSK Board Version Bit

1 DSK_VER1 R DSK Board Version Bit

0 DSK_VER0 R Least Significant DSK Board Version Bit



2.2.4.1.5 DSP DM_CNTL Register (I/O Address 0x0005)

The DM_CTRL register enables the DSP software to control the data and programmemory space selection between external on-board and off-board daughter card memory. This Register also supplies the upper page address bits for data memoryaccesses. Since the 5416 DSK only provides a 32K window for external data memory5 additional address bits are supplied by the CPLD, to expand the DSK’s data reach.

The DM_SEL bit selects whether accesses to data memory locations at 0x8000 to0xFFFF are onboard, or whether the accesses select daughter card memory locations.

MEMTYPE_DS selects whether onboard data memory accesses from 0x8000 to0xFFFF access flash memory (The default at reset to allow the DSP to support parallelbooting from on-board FLASH) or whether these accesses select the on-board SRAM.Note that DM_SEL has precedence over MEMTYPE_DS, therefore DM_SEL must be“0” to access on board data memory space.

MEMTYPE_PS selects either Flash in external on board program space(MEMTYPE_PS=0) or SRAM in external on board space (MEMTYPE_PS=1). Allexternal accesses to program space from 0x000000 to 0x3FFFFF access on boardmemory. Accesses from 0x40000 to 0x7FFFFF access daughter card program spacememory.

The DM_PG[4..0] bits are used as Page address bits for Data memory accesses.The DSP’s address A0-A14 plus the 5 DM_PG[4-0] are combined to make a 19 bitword address. Both the SRAM and the FLASH as well as the Daughter Card Interfaceuse this access mechanism.

(Note that the SRAM pages are 32K each, and the FLASH pages are 32K each.) With the five DM_PG bits provided, thirty-two, 32K data memory pages can be accessed onboard,as well as on a daughter card.


2-15

The table below shows the DM_CTL bit definitions.

Descriptions appearing in bold are defaults.

Table 6: Data Memory (DM_CNTL) Bit Definitions


7 DM_SEL R/W Data Memory Selection (0=on board memory, 1 daughter card)

6 MEMTYPE_DS R/W 0= FLASH ENABLED, 1 = SRAM Memory For Data Space Access

5 MEMTYPE_PS R 0= FLASH ENABLED, 1 = SRAM Memory For Program Space Access

4 DM_PG4 R/W Flash/SRAM/Daughter Cards Memory Page Bit 4 (defaults to 0) MSB

3 DM_PG3 R/W Flash/SRAM/Daughter Cards Memory Page Bit 3 (defaults to 0)



0 DM_PG0 R/W Flash/SRAM/Daughter Cards Memory Page Bit 0 (defaults to 0) LSB



2.2.4.1.6 MISC Register (I/O Address 0x0006)

The MISC Register contains function bits that control data memory access width, theDSP’s MCBSP2 selection and the Codec Control Shift register ready status.

DB_WIDE determines whether daughter card data memory and I/O accesses are 16 or32-bit. When 32-bit (wide) mode is selected, daughter card data memory and I/Oaccesses are asserted to the daughter card based on the DB_32ODD selection. When DB_WIDE is 0, 16-bit accesses are performed, and when DB_WIDE is 1, 32-bitaccesses are performed.

DB_32ODD selects whether a 32 bit daughter card accesses are to an even (0) or odd (1) address. This selection is required to enable data and I/O selects to thedaughter card at the appropriate time. If a 32-bit daughter card access is to an oddaddress, then DB_32ODD should be to 1. If a 32-bit daughter card access is to aneven address, then DB_32ODD should be 0. For, 32-bit daughter card writes, theupper 16 bits should be written first to the destination address plus 1, and then lower 16bits should be written to the destination address. For example, for a 32-bit write todaughter card memory at 0x8000, DB_32ODD should be 0, the most-significant word(MSW) should be written to 0x8001, and the least-significant word (LSW) should bewritten to 0x8000. For 32-bit daughter card reads, the lower 16 bits should be read firstfrom the source address, and then the upper 16 bits should be read from the sourceaddress plus 1. For example, for a 32-bit read from daughter card memory at 0x8001,DB_32ODD should be 1, the LSW should be read from 0x8001 and the MSW shouldbe read from 0x8002

CODEC_RDY is the status bit of the Control channel shift register for the on boardPCM3002 Codec. Before writing to the Codec Control channel the CODEC_RDY bitshould be checked.

BSP2SEL is used to determine if the McBSP 2 channel on the 5416 is used to accessthe data channel on the onboard PCM3002 codec or if the McBSP 2 channel will berouted to the HPI Expansion Connector.

Table 7: MISC Register Bit Definitions


7 CODEC Ready R CODEC Command Transfer Ready (0-ready, 1=not ready)

6 0 R Always zero

5 0 R Always zero

4 0 R Always zero

3 0 R Always zero

2 DC_WIDE R/W Daughter Card Data Memory Width Select (0=16 bits, 1=32 bits)

1 DC32_ODD R/W 32 Bit Daughter Card Address Access Mode (0=even, 1=odd)

0 BSP2SEL R/W McBSP2 Select (0=PCM3002 Data Channel,1=Daughter card)


2-17

2.2.4.1.7 CODEC_CLK Register (I/O Address: 0x0007)

This register controls the divide ratio of the PCM3002 Codec. At reset the register isinitialized to zero (0x00). The Codec input Clock is 12.288 Megahertz at reset. TheCodec Output clock is equal to the Codec input Clock resulting in a 48Khertz samplerate. The Codec input clock can be divided and sent to the codec output Clock via thisregister. The CLK_DIV bits are only valid when the DIV_SEL bit is set to 1.

There is a specific sequence that must be followed when changing the Clock divider toensure proper operation. This sequence is outlined below.

1) Set the CLK_STOP bit CODEC_CLK_REG = CODEC_CLK_REG | CLK_STOP;

2) Set the CLK_DIV1 and CLK_DIV0 bits CODEC_CLK_REG = (CODEC_CLK_REG & ~0x03) | (USER_CLK_DIV1 | USER_CLK_DIV0);

3) Reset the CLK_STOP bit CODEC_CLK_REG = CODEC_CLK_REG & ~CLK_STOP;

4) Set the DIV_SEL CODEC_CLK_REG = CODEC_CLK_REG | DIV_SEL;

Table 8: Codec Clock Register Bit Definitions


7 0 R Always zero

6 0 R Always zero

5 0 R Always zero

4 0 R Always zero

3 DIV_SEL R/W 1=Codec Clock Divide Selected Rate is set by CLK_DIV Bits0=Codec In Clock same as Codec Out Clock

2 CLK_STOP R/W CLK_STOP

1 CLK_DIV1 R/W 00 divide by 2 (fs=24Khz.), 01=divide by 4 (fs=12Khz),10=divide by 6 (fs=8Khz), 11 divide by 8 (fs=6Khz)0 CLK_DIV0 R/W



2.2.5 Flash ROM Interface

The 256K word Flash is mapped into the VC5416’s program space and data space.This flash is meant for boot loading of programs using the VC5416’s parallel bootloader in microcontroller mode or direct loading in microprocessor mode.

For data space accesses there are eight pages (8) of 32K words of flash mapped in theVC5416’s data space from 0x8000 to 0xFFFF. The selected page is determined by theCPLD’s DM_PG[4:0] bits in the DM_CTRL register. These pages are referred to asF_PAGE0 - F_PAGE7 for easy reference. Various control bits in the DM_CTRL registerand the VC5416’s internal PMST register affect the decoding as shown in the tablesbelow.

The table below shows how this memory is mapped via data memory accesses.External Data Accesses in 0x08000-0x0FFFF are paged with A0-A14 being supplieddirectly by the DSP and page address DM_PG[0-4] being supplied by the interfaceCPLD.

Note: Address line A15 is not used but must be a ‘1’ to access external data space.

A[15:0] is DSP AddressDM_PG[4:0] are located in DM_CTNL Register of CPLD at I/O Location 0x0005 bits 4-0. See section 2.2.4.1.5 that discusses the DM_CTNL register.M[19:0] is memory Address

Table 9: FLASH ROM Data Space Access Addressing

A15=1A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

DSPAddress

DM_PG4 DM_PG3 DM_PG2 DM_PG1 DM_PG0 PageAddress

M19 M18 M17 M16 M15 M14

M13

M12

M11

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1

M0

MemoryAddress


2-19

The PMST Register and the interface CPLD are the factors that control the Datamemory decoding as shown in the table below.

Note: External address is A0-A14 plus 5 page register bits.* in VC5416 processor’s PMST register** in CPLD registers

Table 10: Flash ROM Data Memory Address

DSP ADDRESS RANGE DM_PG[4.0]** DROM* DM_SEL** MEMTYPE_DS** ACCESS

0x0000-0x07FFF X X X X Internal DARAMand Registers

0x8000-0xFFFF X 1 X X Internal DARAM

0x8000-0xFFFF 0 0 0 0 External(F_PAGE0)








0x8000-0xFFFF 8-31 0 0 0 External FlashIMAGES



Program space directly accesses the flash memory as long as the access is between0x000000 to 0x3FFFFF. The overlay and MP/MC- bits in the PMST register willdetermine if the memory is internal or external. MEMTYPE_PS determines if SRAM orflash ROM is selected.

* in VC5416 processor** in CPLD

Table 11: Flash ROM Program Memory Address

DSP ADDRESS RANGE MP/MC * OVLY * MEMTYPE_PS** ACCESS

0x000000-0x007FFF X 1 X Internal

0x000000-0x007FFF X 0 0 ExternalF_PAGE 0

0x008000-0x00BFFF X X 0 ExternalF_PAGE 1

0x00C000-0x00FFFF 0 X X Internal

0x00C000-0x00FFFF 1 X 0 ExternalF_PAGE 1

0x01000-0x017FFF X 1 0 Internal

0x010000-0x017FFF X 0 X ExternalF_PAGE 2

0x018000-0x01FFFF X X 0 ExternalF_PAGE 3







.

. IMAGES

.

0x3F8000-0x3FFFFF X 1 X External ImageF_PAGE 7


0x408000-0x40FFFF X X 0

Daughter Card Access in32K pages

(0x8000-0xFFFF)if OVLY=1

All pages from 0x400000-0x7FFFFFif OVLY=0


2-21

2.2.6 SRAM Interface

The 64K word SRAM is mapped into the VC5416’s program space and data space.This SRAM provides a mechanism to support on chip DMA and allows development ofboot code for flash rom

For data space accesses there are two pages (2) of 32K words of SRAM mapped in theVC5416’s data space from 0x8000 to 0xFFFF. The selected page is determined by theCPLD’s DM_PG[4:0] bits in the DM_CTRL register. These pages are referred to asSR_PAGE0 and SR_PAGE1 for easy reference. Various control bits in the DM_CTRLregister and the VC5416’s internal PMST register affect the decoding as shown in thetables below.

The table below shows how this memory is mapped via data memory accesses.External Data Accesses in 0x08000-0x0FFFF are paged with A0-A14 being supplieddirectly by the DSP and page address DM_PG[0-4] being supplied by the interfaceCPLD.

Note: Address line A15 is not used but must be a ‘1’ to access external data space.

A[15:0] is DSP AddressDM_PG[4:0] are located in DM_CTNL Register of CPLD at I/O Location 0x0005 bits 4-0. See section 2.2.4.1.5 that discusses the DM_CTNL register.M[19:0] is memory Address

Table 12: SRAM Data Space Access Addressing

A15=1A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

DSPAddress

DM_PG4 DM_PG3 DM_PG2 DM_PG1 DM_PG0 PageAddress

M19 M18 M17 M16 M15 M14

M13

M12

M11

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1

M0

MemoryAddress



The PMST Register and the interface CPLD are the factors that control the Datamemory decoding as shown in the table below.

Note: External address is A0-A14 plus 5 page register bits.* in VC5416 processor’s PMST register** in CPLD registers

Table 13: SRAM Data Memory Address

DSP ADDRESS RANGE DM_PG[4.0]** DROM* DM_SEL** MEMTYPE_DS** ACCESS

0x0000-0x07FFF X X X X Internal DARAMand Registers

0x8000-0xFFFF X 1 X X Internal DARAM

0x8000-0xFFFF 0 0 0 1 External(SR_PAGE0)

0x8000-0xFFFF 1 0 0 1 External(SR_PAGE1)

0x8000-0xFFFF 2-31 0 0 1 External SRAMIMAGES


2-23

Program space directly accesses the SRAM as long as the access is between0x000000 to 0x3FFFFF. The overlay and MP/MC- bits in the PMST register willdetermine if the memory is internal or external. MEMTYPE_PS determines if SRAM orflash ROM is selected.

* in VC5416 processor** in CPLD

Table 14: SRAM Program Memory Address

DSP ADDRESS RANGE MP/MC * OVLY * MEMTYPE_PS** ACCESS


0x000000-0x007FFF X 0 1 ExternalSR_PAGE 0

0x008000-0x00BFFF X X 1 ExternalSR_PAGE 1

0x00C000-0x00FFFF 0 X X Internal

0x00C000-0x00FFFF 1 X 1 ExternalSR_PAGE 1


0x010000-0x017FFF X 0 X Image SR_PAGE 0

0x018000-0x01FFFF X X 0 Image SR_PAGE 1

.

. IMAGES

.

0x3F8000-0x3FFFFF X 1 X ImageSR_PAGE 1


0x408000-0x40FFFF X X 0

Daughter CardAccesses in32K pages

(0x8000-0xFFFF)if OVLY=1

All pages from 0x400000-0x7FFFFFif OVLY=0



2.2.7 Codec Interface

The DSK uses a PCM3002 stereo Codec to provide analog inputs and outputs. Theinterface to the codec is through two channels, one for control the other for data. TheCPLD on the DSK’s is used to interface to the control channel via 2 –8 bit registers inI/O space CODEC_L and CODEC_H. Furthermore, the CPLD generates all requiredtiming signals for the PCM3002 via a clock oscillator and the CODEC_CLK controlregister. The default CODEC system clock is 12.488-MHz. The CPLD uses theCODEC system clock to generate a bit clock of 3.0122-MHz and a frame sync signal of48-KHz. This can be changed to other frequencies as outlined in the CODEC_CLKsection of the CPLD. The Data to the codec, is supplied via the VC5416’s McBSP2interface. There is a bit in the MISC register of the CPLD which will allow the McBSP2register to be routed to the HPI expansion connector, however, the default path is to thePCM3002 Codec.

The diagram below shows the interconnection between the Codec, CPLD, and DSP.

DATAADDRESS CONTROL

TMS320VC5416

Figure 2-6, TMS320VC5416 DSK CODEC INTERFACE

PCM3002

MC

MD

ML

SYSCLK

CONTROL I/F

BCLKINLRCINDINDOUT

DATA I/F

QUICK

SWITCH

CPLD

12.288 Mhz

OSC

HPICONNECTOR

McBSP2

MUX


2-25

2.2.7.1 Programming the Codec Control Interface

The PCM3002 Control Interface has four 16-bit internal registers that are softwarecontrolled via a serial interface. The CPLD has two internal 8-bit registers that whenwritten in sequence will transfer their contents to the CODEC’s control interface. Theserial master control signals of the CODEC consist of the CODEC_MC (master clock),CODEC_MD (master data), and CODEC_ML (master load).

To write a control word to the CODEC, the user will write two 8-bit bytes to the CPLD atI/O locations 0x0002 (CODEC_L), and 0x0003 (CODEC_H). The first byte is the lowerorder byte of the 16-bit control word, the second byte is the higher order byte of the 16-bit control word.

After the completion of the write to CODEC_H, the CPLD will automatically transmit thedata serially to the CODEC control interface over the master control signals. Beforeanother Control Interface Codec Transfer is done, the programmer needs to check theCODEC_RDY bit in the MISC Register of the CPLD (IO address 0x0006 bit 7). Thisbit gives the current state of the control interface shift register in the CPLD.

For additional information about the control bits of the CODEC, please refer to thePCM3002 data sheet.

2.2.7.2 Programming the Data interface

The Data interface on the PCM3002 is connected to the McBSP2 pins on the VC5416DSP. The table below shows the pin assignments of this interconnection.

The CPLD has a CODEC_CLK register that allows the programmer to change thesampling frequencies shown in the CODEC_CLK register section.

Table 15: PCM3002 - VC5416 Interconnect

PCM3002 Signal Type

CPLD Signal Type

VC5416 Signal Type

SYSCLK I CODEC_CLK O N/A

BCLKIN I CODEC_BCLK O BCLKR2BCLKX2

I

LRCIN I N/A BFSR2BFSX2

O

DIN I N/A BDX2 O

DOUT O N/A BDR2 I



2.2.7.3 PCM3002 Codec Input/Output Circuitry

Four industry standard 3.5 mm. connectors are used in the audio interface, one for line-level audio inputs, one for a microphone, one for line-level audio outputs, and onefor speakers or headphones. The line-level inputs are stereo, while the microphoneinput only supports a single channel (mono). On the output side there are stereoconnections on both the amplified and unamplified signals.

The two analog inputs (line and microphone) are AC coupled, active filtered and mixedprior to being digitized by the PCM3002E connected to the McBSP2 port of the DSP. The line-level input has a fixed gain of 0dB. The line-level inputs support signal levelsof up to 2Vrms. The microphone input is designed for electret microphones thatrequire a bias voltage. A dynamic microphone can be used if capacitors are used toblock the bias voltage. The maximum allowable signal level from the microphone is 1Vrms. The microphone input has a potentiometer which allow the user to adjust gain onthe microphone input.

The DAC output from the PCM3002 CODEC has programmable attenuation from+0dB to mute in –1.5dB increments. The DAC output channel is filtered using a

multiple-feedback 2nd order active filter. The post-filter has a cut-off frequency of30KHz. The post-filtered information is directly passed to a standard stereo audio jackfor line-level loads (~10Kohms) and also passed through an output driver stage forconnection to low impedance speakers or headphones (e.g. 8 to 32 ohms).


2-27

2.2.8 Daughter Card Memory Interface

The 5416 DSK supports the standard daughter card interface interconnections.Accesses to the Daughter-cards can be done via Program Space, Data Space, or I/O space. On the 5416 DSK Daughter cards all spaces support 16 data bits transfersand Data Space and I/O accesses can support 32 data bits transfers. DM_SEL mustbe set for data space accesses. I/O space and program space accesses use memorydecode to control accesses

It is recommended to run the EMIF in CLKOUT/2 mode at higher clock rates (above100 MHz) to avoid buffer conflicts.

Sample programs for accessing daughter card 16 bit program memory, 16 and 32 bitdata memory, and 16 and 32 bit I/O memory are included in the .pdf file:c:\TI\docs\pdf\5416_dsk_expsw.pdf.

2.2.8.1 Program Space Accesses

Daughter-Card Program Space accesses on the DSK are available when A22 is a logic 1. All Daughter Card Program Space accesses are 16 bits wide. Therefore, allexternal accesses from 0x400000 to 0x7FFFFF access the daughter card space.Note that if the OVLY bit is selected only the upper 32K of each (0x8000 - 0xFFFF) ismapped to the daughter card interface. These accesses are shown in the table below:

* In VC5416 processor

Table 16: Program Space Accesses

DSP Address Range OVLY * Access

0x000000-0x3FFFFF X On-board/internal

0x400000-0x407FFF 1 Internal DSP Access

0x400000-0x407FFF 0 Daughtercard

0x408000-0x40FFFF X Daughtercard

0x410000-0x417FFF 1 Internal DSP Access

0x410000-0x417FFF 0 Daughtercard

0x418000-0x41FFFF X Daughtercard

0x42000 to0x7FFFF

See above maps

Same as above maps



2.2.8.2 Data Space Accesses

Daughter card data memory accesses on the DSK are available when A15 is a logic 1,DROM is turned off in the PMST register, and the DM_SEL bit in the DM_CNTLregister of the CPLD is set to 1. The address range from the DSP is 0x8000 to 0xFFFF,however the 5 DM_PG[0:4] bits are added to the DSP’s A0-A14 lines to make thirty-two (32) 32K 16 bit accessible pages.

Both 16 and 32 bit accesses are available for the data space accesses. Theseaccesses are shown in the table below:

Table 17: Data Space Accesses

DSP AddressRange DM_PG[4:0]** DROM* DM_SEL** MEMTYPE_DS** DC_WIDE** DC32_ODD** ACCESS

0x0000-0x7FFF X X X X X X Internal

0x8000-0xFFFF X X 0 X X X Onboard/internal

0x8000-0xFFFF 0 0 1 X 0 X Daughtercard 16 bit access page 0

0x8000-0xFFFF 1:31 0 1 X 0 X Daughtercard 16 bit access page 1-31

0x8000-0xFFFF 0 0 1 X 1 0 Daughtercard 32 bit access page 0even address

0x8000-0xFFFF 0 0 1 X 1 1 Daughtercard 32 bit access page 0

odd address

0x8000-0xFFFF 1:31 0 1 X 1 0 Daughtercard 32 bit access page 1-31

even address

0x800-0x7FFFF 1:31 0 1 X 1 1 Daughtercard 32 bit access page 1-31

odd address


2-29

2.2.8.2.1 Data Space 32 Bit Accesses

Like with 16 bit data accesses there are two 32 (thirty-two) 32K word pages available to daughter card accesses. However, for 32 bit data space accesses specificsequences must be programmed to get correct 32 bit wide data transfers

For even address sequences (e.g. 0x28400) the accesses are broken up into 2accesses one at 0x8400 and one at 0x8401.Note the upper address comes from theDM[0:4] bits. The DC-32 Odd bit in the CPLD MISC register should be set to 0, and thesequence below shows the correct access procedure.

Write Sequence: 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD bit in the CPLD MISC register 3. Do the 2 Data Space accesses:

- Most Significant WORD at ODD address (0x8401)- Least Significant word at EVEN address (0x8400)

4. Turn off the DC_WIDE bit in the MISC register

Read Sequence 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD in the CPLD MISC register 3. Do the 2 Data Space accesses:

- Least Significant WORD at EVEN address (0X8400)- Most Significant word at ODD address (0x8401)


For Odd address sequences (e.g. 0x28401) the accesses are broken up into 2accesses one at 0x8401 and one at 0x8402. The DC-32 Odd bit in the CPLD MISCregister should be set to 1, and the sequence below shows the correct accessprocedure

Write Sequence: 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD in the CPLD MISC register 3. Do the 2 Data Space accesses:

- Most Significant WORD at EVEN address (0x8402)- Least Significant word at ODD address (0x8401)


Read Sequence 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD in the CPLD MISC register 3. Do the 2 Data Space accesses:

- Least Significant WORD at EVEN address (0x8401)- Most Significant word at ODD address (0x8402)




2.2.8.3 I/O Space Accesses

Daughter-Card I/O Space accesses on the DSK are available when the DSP’s addressbit A15 is a logic 1. The address range for I/O accesses is 32K Words from 0x8000 to0xffff. Access data width can be either 16 bits or 32 bits wide. These accesses areshown in the table below:

** In CPLD

Note specific sequences are necessary for 32 bit access. For 16 bit accesses there isno specific programming sequences that need to be implemented.

Table 18: I/O Space Accesses

DSP Address Range DC_WIDE ** DC32_ODD** Access

0x0000-0x7FFF X X On-board

0x8000-0xFFFF 0 X Daughtercard 16 bit Access

0x8000-0xFFFF 1 0 Daughtercard 32 bit Access

0x8000-0xFFFF 1 1 Daughtercard 32 bit Access


2-31

2.2.8.3.1 I/O Space 32 Bit Accesses

For 32 bit accesses specific sequences must be programmed to get correct 32 bit widedata transfers

For even address sequences (e.g. 0xC000) the accesses are broken up into 2accesses one at 0xC000 and one at 0xC001. The DC-32 Odd bit in the CPLD MISCregister should be set to 0, and the sequence below shows the correct accessprocedure.

Write Sequence: 1. Set the DC_WIDE bit and clear the DG32_ODD bit in the CPLD MISC register 2. Do the 2 I/O accesses:

- Most Significant WORD at ODD address (0xC001)- Least Significant word at EVEN address (0xC000)


Read Sequence 1. Set the DC_WIDE bit and clear the DG32_ODD bit in the CPLD MISC register 2. Do the 2 I/O accesses:

- Least Significant WORD at EVEN address (0XC000)- Most Significant word at ODD address (0xC001)


For Odd address sequences (e.g. 0xC001) the accesses are broken up into 2 accessesone at 0xc001 and one at 0xc0002. The DC-32 Odd bit in the CPLD MISC registershould be set to 1, and the sequence below shows the correct access procedure

Write Sequence: 1. Set the DC_WIDE and DC32_ODD bits in the CPLD MISC register 2. Do the 2 I/O accesses:

- Most Significant WORD at EVEN address (0xC002)- Least Significant word at ODD address (0xC001)


Read Sequence 1. Set the DC_WIDE and DC32_ODD bits in the CPLD MISC register 2. Do the 2 I/O accesses:

- Least Significant WORD at EVEN address (0xC001)- Most Significant word at ODD address (0xC002)




2.2.9 Wait States

The TMS320VC5416 has an on chip wait state generator controller controlled byregisters SWWSR and SWCR mapped in the data memory. The table below showsthese 2 registers and their function.

2.2.9.1 Software Wait State Generator

The software wait state generator on the TMS320VC5416 can be extended externalbus cycles by up to 14 machine cycles. Devices that require more then 14 wait-statescan be interfaced using the hardware READY line.

The software wait state register, SWWSR, controls the operation of the wait stategenerator. The 14 LSBs of the SWWSR specifies the number of wait states (0-7) to beinserted for external memory accesses to five separate ranges. This allows a differentnumber of wait states for each of the 5 address ranges. Additionally, the software waitstate multiplier, SWSM, bit of the wait state control register, SWCR, defines amultiplication factor of 1 or 2 for the number of wait states. At reset, the wait stategenerator is initialized to provide 7 wait states on all external memory accesses. TheSWWSR bit fields are shown in the table below.

Table 19: SWWSR Register Bit Fields

Bits 15 14 12 11 9 8 6 5 3 2 0

Space XPA I/O Data Data Program Program

Read, Write R/W R/W R/W R/W R/W R/W

Reset Value 0 111 111 111 111 111


2-33

The bit fields in SWWSR are described in the table below.

Table 20: SWWSR Bit Field Definition

Bit #Bit

NameReset Value

Function

15 XPA0 Extended program address control bit. XPA is used in

conjunction with the program space fields (bits 0-5) to select the address range for program space wait states

14-12 I/O 111

I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses within addresses 0x0000-0xFFFF. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

11-9 Data 111

Upper Data Space. The field value (0-7) corresponds to the base number of wait states for external data space accesses within addresses 0x8000-0xFFFF. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

8-6 Data 111

Lower Data Space. The field value (0-7) corresponds to the base number of wait states for external data space accesses within addresses 0x0000-0x7FFF. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

5-3 Program 111

Upper Program Space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within addresses:

- XPA= 0: 0x8000 - 0xFFFF- XPA= 1: The upper program space bit field has no effect on wait states

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

2-0 Program 111

Lower Program Space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within addresses:

- XPA= 0: 0x8000 - 0x7FFF- XPA= 1: 0x00000 - 0xFFFFF

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.



The software wait state multiplier bit of the software wait state control register,SWWSR, is used to extend the base number of wait states selected by the SWWSR.The SWSR bit fields are shown in the table below.

The bit fields in SWWSR are described in the table below.

This controller allows various regions in memory to be programmed to different waitstate values. The TMS320VC5416 powers up with maximum wait states. On theTMS320VC5416 DSK the access time for various components in the table below.

Table 21: Software Wait State Control Register Bits Fields

Bit # 15 1 0

Function Reserved SWSM

Reset, Write R/W R/W

Reset Value 0 0

Table 22: SWWSR Bit Field Definition

Bit #Bit

NameReset Value

Function

15-1 Reserved 0 These bits are reserved and unaffected by writes

0 SWSM 0

Software wait state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2.

- SWSM = 0: wait state base values are unchanged (multiplied by 1)- SWSM = 1: wait state base values are multiplied by 2 for a maximum of 14 wait states.

Table 23: Memory Wait States

Device Access Time DecoderTotal Access

Time

SRAM 12 ns. 10 ns. 22 ns.

Flash 70 ns. 10 ns. 80 ns.

CPLD 60 ns. 60 ns.


2-35

The access time on the TMS320VC5416 is ta(A)M1 for non-consecutive accesses andta(A)M2 for consecutive accesses. The table below shows various access times forvarious frequencies.

It is recommended to operate the EMIF in CLKOUT/2 mode at higher frequencies (CPU frequency from 96 - 160 Mhz.) to avoid buffer contention from daughter cardbuffers. Note that wait states with EMIF in CLKOUT/2 mode can be programmed toone-half the value in the table below.

The table below shows the maximum wait states for the various frequencies.various frequencies.

Table 24: Access Times

Frequency 2HEach Wait

Stateta(A)1st Cycle

(2H-4)

160 Mhz. 6.25 ns. WS*6.25 ns. 2.25 ns.

120 Mhz. 8.33 ns. WS*8.33 ns. 6.4 ns.

96 Mhz. 10.4 ns. WS*10.4 ns. 6.4 ns.

48 Mhz. 20.83 ns. WS*20.83 ns. 16.83 ns.

Table 25: Minimum Wait States

Frequency SRAM Flash CPLD

160 Mhz. 3 12 9

120 Mhz. 2 10 7

96 Mhz. 2 7 6

48 Mhz. 0 4 3



2.3 TMS320VC5416 DSK Jumpers

The TMS320VC5416 DSK has a single jumper block, JP4, which controls the power upCLKMODE and MP/MC setting.

2.3.1 JP4, DSP Clock and Mode Configuration

Jumper JP4 is a 4 x 2 connector that determines the power up CLKMODE on theDSP, and selects whether the DSP is in microcomputer mode or microcontroller mode.The table below shows the clock and mode selection settings.

Note: “*” is the default setting. This is the 2 x CLKIN PLL On, OSC On, Microcontroller Mode

The figure below show JP4 in the default configuration.

Table 26: JP4, DSP Configuration

CLKMD1 CLKMD2 CLKMD3 MP/MC Clock Mode DSP MP/MC Mode

OFF OFF OFF OFF 1/2 x CLKIN PLL Off, OSC On Microprocessor Mode

OFF OFF ON OFF 1 x CLKIN PLL On, OSC On Microprocessor Mode

OFF ON OFF OFF 1/4 x CLKIN PLL Off, OSC On Microprocessor Mode

OFF ON ON OFF 2 x CLKIN PLL On, OSC On Microprocessor Mode

ON OFF OFF OFF RESERVED Microprocessor Mode

ON OFF ON OFF 5 x CLKIN PLL On, OSC On Microprocessor Mode

ON ON OFF OFF 10 x CLKIN PLL On, OSC On Microprocessor Mode

ON ON ON OFF 1/2 x CLKIN PLL Off, OSC Off Microprocessor Mode

OFF OFF OFF ON 1/2 x CLKIN PLL Off, OSC On Microcontroller Mode

OFF OFF ON ON 1 x CLKIN PLL On, OSC On Microcontroller Mode

OFF ON OFF ON 1/4 x CLKIN PLL Off, OSC On Microcontroller Mode

OFF ON ON ON 2 x CLKIN PLL On, OSC On * Microcontroller Mode

ON OFF OFF ON RESERVED Microcontroller Mode

ON OFF ON ON 5 x CLKIN PLL On, OSC On Microcontroller Mode

ON ON OFF ON 10 x CLKIN PLL On, OSC On Microcontroller Mode

ON ON ON ON 1/2 x CLKIN PLL Off, OSC Off Microcontroller Mode

CLK

MD

1C

LKM

D2

CLK

MD

3M

P/M

C

JP4

Figure 2-7, JP4, DSP Configuration - Default Setting


2-37

2.4 TMS320VC5416 DSK Connectors

The TMS320VC5416 DSK has sixteen (16) connectors which provide the user accessto the various on the DSK. The position of each connector is identified in Figure 2-1.These connectors, their size, their function, and the side of the printedcircuit board they are mounted on are shown in the table below.

Note: “*” Not populated

2.4.1 Expansion Connectors

The TMS320VC5416 DSK supports three expansion connectors that follow the TexasInstruments interconnection guidelines. The expansion connector pinouts aredescribed in the following three sections.

Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin

Table 27: TMS320VC5416 DSK Connectors

Connector # Pins Function

P1 80 Memory

P2 80 Peripheral

P3 80 HPI

J1 2 Microphone

J2 2 Line In

J3 2 Line Out

J4 2 Speaker

J5 * 4 Optional Power Connector

J6 2 +5 Volt

J7 14 External JTAG

J201 5 USB JTAG

JP1 10 CPLD Programming

JP4 8 DSP Configuration Jumper



2.4.2 P1, Memory Expansion Connector

Table 28: P1, Memory Expansion Connector

Pin # Signal Name I/O/Z Pin # Signal Name I/O/Z1 +5 Volts O 2 +5 volts O3 DC_A19 O 4 DC_A18 O5 DC_A17 O 6 DC_A16 O7 DC_A15 O 8 DC_A14 O9 DC_A13 O 10 DC_A12 O11 GND O 12 GND O13 DC_A11 O 14 DC_A10 O15 DC_A9 O 16 DC_A8 O17 DC_A7 O 18 DC_A6 O19 DC_A5 O 20 DC_A4 O21 +5 Volts O 22 +5 Volts O23 DC_A3 O 24 DC_A2 O25 DC_A1 O 26 DC_A0 O27 DC_A21 O 28 DC_A20 O29 GND O 30 GND O31 GND O 32 GND O33 DC_D31 I/O/Z 34 DC_D30 I/O/Z35 DC_D29 I/O/Z 36 DC_D28 I/O/Z37 DC_D27 I/O/Z 38 DC_D26 I/O/Z39 DC_D25 I/O/Z 40 DC_D24 I/O/Z41 +3.3 Volts O 42 +3.3 Volts O43 DC_D23 I/O/Z 44 DC_D22 I/O/Z45 DC_D21 I/O/Z 46 DC_D20 I/O/Z47 DC_D19 I/O/Z 48 DC_D18 I/O/Z49 DC_D17 I/O/Z 50 DC_D16 I/O/Z51 GND O 52 GND O53 DC_D15 I/O/Z 54 DC_D14 I/O/Z55 DC_D13 I/O/Z 56 DC_D12 I/O/Z57 DC_D11 I/O/Z 58 DC_D10 I/O/Z59 DC_D9 I/O/Z 60 DC_D8 I/O/Z61 GND O 62 GND O63 DC_D7 I/O/Z 64 DC_D6 I/O/Z65 DC_D5 I/O/Z 66 DC_D4 I/O/Z67 DC_D3 I/O/Z 68 DC_D2 I/O/Z69 DC_D1 O 70 DC_D0 O71 GND O 72 GND O73 DC_RE- O 74 DC_WE- O75 DC_OE- O 76 DC_RDY I77 DC_MSTRB- O 78 DC_DS- O79 GND O 80 GND O


2-39

2.4.3 P2, Peripheral Expansion Connector

Table 29: P2, Peripheral Expansion Connector

Pin # Signal Name I/O/Z Pin # Signal Name I/O/Z1 +12 Volts * O 2 -12 Volts * O3 GND O 4 GND O5 +5 Volts O 6 +5 Volts O7 GND O 8 GND O9 +5 Volts O 10 +5 Volts O11 RESERVED 12 RESERVED13 RESERVED 14 RESERVED15 RESERVED 16 RESERVED17 RESERVED 18 RESERVED19 +3.3 Volts O 20 +3.3 Volts O21 DC_BCLKX0 I/O/Z 22 RESERVED23 DC_BFSX0 I/O/Z 24 DC_BDX0 O/Z25 GND O 26 GND O27 DC_BCLKR0 I/O/Z 28 RESERVED29 DC_BFSR0 I/O/Z 30 DC_BDR0 I31 GND O 32 GND O33 DC_BCLKX1 I/O/Z 34 RESERVED35 DC_BFSX1 I/O/Z 36 DC_BDX1 O/Z37 GND O 38 GND O39 DC_BCLKR1 I/O/Z 40 RESERVED41 DC_BFSR1 I/O/Z 42 DC_BDR1 Z43 GND O 44 GND O45 DC_TOUT O 46 RESERVED47 RESERVED 48 DC_INT1- I49 DC_XF O 50 DC_BIO- I51 GND O 52 GND O53 INT3- I 54 RESERVED55 RESERVED 56 DC_IOSTRB- O57 RESERVED 58 RESERVED59 RESET- O 60 RESERVED61 GND O 62 GND O63 DC_CNTL1 O 64 DC_CNTL0 O65 DC_STAT1 I 66 DC_STAT0 I67 DC_INT2- I 68 DC_INT3- I69 DC_PS- O 70 DC_IS- O71 RESERVED 72 RESERVED73 RESERVED 74 RESERVED75 DC_DETECT- I 76 GND O77 GND O 78 DC_CLKOUT/2 O79 GND O 80 GND O

* Provided from optional power connector J5



2.4.4 P3, HPI Expansion Connector

Table 30: P3, HPI Expansion Connector

Pin # Signal Name I/O/Z Pin # Signal Name I/O/Z1 +5 Volts O 2 +5 Volts O3 HP_BCLKX2 I/O/Z 4 HP_BCLKR2 I/O/Z5 HP_BFSX2 I/O/Z 6 HP_BFSR2 I/O/Z7 HP_BDX2 O/Z 8 HP_BDR2 I9 RESERVED 10 HP_CLKOUT/2 O11 GND O 12 GND O13 HP_HRW I 14 HP_HCNTL0 I15 HP_HAS- I 16 HP_HCS- I17 HP_HCNTL1 I 18 HP_HBIL I19 HP_HDS2 I 20 HP_HDS1 I21 +5 Volts O 22 +5 Volts O23 HP_HRDY O 24 HP_HPINT- O25 HP_HPI_EN I 26 HP_HPI16 I27 RESERVED 28 RESERVED29 RESERVED 30 RESERVED31 GND O 32 GND O33 RESERVED 34 RESERVED35 RESERVED 36 RESERVED37 RESERVED 38 RESERVED39 RESERVED 40 RESERVED41 RESERVED 42 RESERVED43 RESERVED 44 RESERVED45 RESERVED 46 RESERVED47 RESERVED 48 RESERVED49 RESERVED 50 RESERVED51 GND O 52 GND O53 RESERVED 54 RESERVED55 RESERVED 56 RESERVED57 RESERVED 58 RESERVED59 RESERVED 60 RESERVED61 GND O 62 GND O63 HP_D7 I/O/Z 64 HP_D6 I/O/Z65 HP_D5 I/O/Z 66 HP_D4 I/O/Z67 HP_D3 I/O/Z 68 HP_D2 I/O/Z69 HP_D1 I/O/Z 70 HP_D0 I/O/Z71 GND O 72 GND O73 HP_HOLDA- O 74 HP_HOLD- I75 RESERVED 76 RESERVED77 HP_DSPIACK- O 78 HP_RST- O79 GND O 80 GND O


2-41

2.4.5 J1, Microphone Connector

The microphone interfaces to the PCM3002E via a simple op-amp circuit. The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural.The signals on the plug are shown in the figure below.

2.4.6 J2, Audio Line In Connector

The audio line in is a stereo input. This input interfaces to the PCM3002E via a simpleop-amp bias circuit. The input connector is a 3.5 mm stereo jack. The signals on themating plug are shown in the figure below.

2.4.7 J3, Audio Line Out Connector

The audio line out is a stereo output. This output is driven by the PCM3002E througha simple op-amp circuit. The output connector is a 3.5 mm stereo jack. The signals onthe mating plug are shown in the figure below.

Microphone In

Ground

Figure 2-8, Microphone Stereo Jack

Left Line In

Ground

Figure 2-9, Audio Line In Stereo Jack

Right Line In

Left Line Out

Ground

Figure 2-10, Audio Line Out Stereo Jack

Right Line Out



2.4.8 J4, Headphone/Speaker Connector

Connector J4 is a headphone/speaker jack. It is driven by a small TPA302 amplifierconnected to the PCM3002E codec and can drive standard headphones or a highimpedance speaker directly. The standard 3.5 mm jack is shown in the figure below.

2.4.9 J5, Optional Power Connector

Connector J5 is an optional power connector. It will operate with the standard personalcomputer power supply. To populate this connector use a Molex #15-24-4041. Thetable below shows the voltages on the respective pins.

2.4.10 J6, +5 Volt Connector

Power (5 volts) is brought onto the TMS320VC5416 DSK via the J6 connector. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. TheThe diagram of J6, which has the input power is shown below.

Table 31: J5, Optional Power Connector

Pin # Voltage Level

1 +12 Volts

2 -12 Volts

3 Ground

4 +5 Volts

Left Headphone

Ground

Figure 2-11, Headphone Jack

Right Headphone

WARNING !Do not plug into J5 and J6 at the same time.

PC Board

J6+5V

Ground

Front ViewFigure 2-12, TMS320VC5416 DSK Power Connector


2-43

2.4.11 J7, External JTAG Connector

The TMS320VC5416 DSK is supplied with a 14 pin header interface, J7. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.The pinout for the connector is shown figure 2-6 below.

The signal names for each pin are shown in the table below.

Table 32: J7, JTAG Interface

Pin # Signal Name

1 TMS

2 TRST-

3 TDI

4 GND

5 PD

6 no pin

7 TDO

8 GND

9 TCK-RET

10 GND

11 TCK

12 GND

13 EMU0

14 EMU1

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 2-13, JTAG INTERFACE



2.4.12 JP1, PLD Programming Connector

This connector interfaces to the Altera CPLD, U18. It is used in the in the factory for theprogramming of the CPLD. This connector is not intended to be used outside thefactory.

2.5 User LEDs

TheTMS320VC5416 DSK has four user definable light emitting diodes (LEDs). TheseLEDs are used by the Power On Self Test (POST) but are available for user programs.They are accessed via the I/O address 0x0000. The function of each LED is shown inthe table below.

2.5.1 System LEDs

TheTMS320VC5416 DSK has four system light emitting diodes (LEDs). TheseLEDs indicate various conditions on the DSK. These function of each LED is shown inthe table below.

Table 33: User LEDs

Reference Designator

LED # Color Controlling SignalOn Signal

State

D9 1 Green CPLD Register 0, Data Bit 0 1




Table 34: System LEDs

Reference Designator

Color FunctionOn Signal

State

D6 Green USB Emulation in use. When External JTAG Emulator is used this LED is off.

1

D7 Green +5 Volt present 1

D8 Green RESET Active 1

D201 Green USB Active, Blinks during USB data transfer 1


2-45

2.6 Switches

The TMS320VC5416 has two switches, a Reset switch, and a 4 position user DIPswitch.

2.6.1 Reset Switch/Reset Logic

There are three resets on the TMS320VC5416 DSK. The first reset is the power onreset. This circuit waits until power is within the specified range before releasing thepower on reset pin to the TMS320VC5416.

External sources which control the reset are push button S1, and the on boardembedded USB JTAG emulator.

2.6.2 4 Position User DIP Switch

The TMS320VC5416 DSK has a 4 position user DIP switch, S2. It is accessible viaCPLD Register 0 at I/O location 0x0000. The function of each switch is shown in thetable below.

On is a logic “1”, Off is a logic “0”.

Table 35: S2 Switch Positions

Position Controlling Signal

1 CPLD Register 0, Data Bit 4






2.7 J201, Universal Serial Bus (USB) Embedded JTAG Emulation Connector

Connector J201 provides a Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the DSK. This allows for code development and debugwithout the use of an external emulator. The signals on this connector are shown in thebelow.

Table 36: J201, USB Connector

Pin # USB Signal Name

1 USBVdd

2 D+

3 D-

4 USB Vss

5 Shield

6 Shield

A-1

Appendix A

TMS320VC5416 DSK CPLD Equations

CPLD equations are installed in .pdf format from the CD-ROM for the DSKin the directory: C:\TI\docs\pdf\5416_dsk_vhdl.pdf


A-2 TMS320VC5416 DSK Module Technical Reference

B-1

Appendix B

TMS320VC5416 DSK Schematics

This appendix contains the schematics for the TMS320VC5416 DSK. Theschematics were drawn in ORCAD. Schematics for the embedded USBJTAG controller are not included.


B-2 TMS320VC5416 DSK Module Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

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REVISION STATUS OF SHEETS

5DATE

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DATE

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3. CAPACITANCE VALUES ARE IN MICROFARADS.

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NOTES, UNLESS OTHERWISE SPECIFIED:

2. RESISTANCE VALUES ARE IN OHMS.

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12-06-2001

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03-18-2002

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ETU

P2

BR

D_S

ETU

P0

DS

P_T

DO

DS

P_T

CK

DS

P_T

MS

DS

P_E

MU

1

DS

P_T

DI

DS

P_E

MU

0

DS

P_T

RST

#

DS

P_I

NT2

#D

SP

_IN

T3#

DS

P_I

NT1

#D

SP

_IN

T0#

DS

P_X

FD

SP

_BIO

#

DS

P_T

OU

TD

SP

_CLK

BR

D_R

ST#

DS

P_I

AC

K#

US

ER

_SW

2

US

ER

_SW

0U

SE

R_S

W1

US

ER

_SW

3

DG

ND

DG

ND

DG

ND

3.3V

3.3V

3.3V

3.3V

1.6V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

DG

ND

3.3V

1.6V

3.3V

DG

ND

TP5

RN

3A10

K1

16A

BR

N3B

10K

215

AB

RN

3C10

K3

14A

BR

N3D

10K

413

AB

R62

33

C68

0.1u

F

TP13

TP1

C69

0.1u

F

C73

0.1u

F

C84

0.1u

F

JP4

HE

AD

ER

4X

2

12

34

56

78

C85

0.1u

F

TP10

TP1

TP11

TP1

C92

0.1u

F

C71

0.1u

F

C94

0.1u

F

C70

0.1u

F

R54

1 0K

RN

3F10

K6

1 1A

BR

N3G

10K

710

AB

RN

3H10

K8

9A

BR

N3E

10K

512

AB

TP12

CLK

IN

TP3

TP4

C67

0.1u

F

C83

0.1u

F

R60

4.7K

C86

0.1u

F

R61

4.7K

U16 16

.000

MH

z

24 31

GN

D

VD

D

OU

TE/

D

L15

Ferri

te C

hip

U21

A

TMS

320V

C54

16-P

GE

32 31

2926 276 3 64 65 66 67

6 1

89 8887 868584 83

9798 9694

797877

82

MP

/MC

BIO

IAQ

MS

C XF

NM

IIN

T0I N

T1IN

T2IN

T3

IAC

K

TMS

TCK

TRS

T

TDI

TDO

EM

U1/

OFF

EM

U0

X2/

CLK

IN

RS

X1

CLK

OU

T

CLK

MD

3C

LKM

D2

CLK

MD

1

TOU

T

S2

SW

DIP

-4

12345

678

RN

2A10

K1

16A

B

RN

2E10

K5

12A

B

RN

2C10

K3

14A

B

RN

2B10

K2

15A

BR

N2D

10K

413

AB

RN

2F10

K6

11A

B

C93

0.1u

F

R53

33

C88

0.1u

F

U21

D

TMS

320V

C54

16-P

GE

1 3

412

141516

33

34 3 7

40

505256 57

68 70

7 2 7675 93

91 9010

6

144

1 42

130

128

126

125

112

111

CVs

sC

Vss

DV

ddC

Vdd

DVs

sC

Vss

CV

ddD

Vdd

CVs

sC

Vss

DVs

s

CVs

s

CV

ddD

Vdd

DVs

s

CV

dd

CVs

s

DVs

sD

Vss

DV

dd

DVs

s

CV

dd

CVs

sD

Vss

DVs

s

CV

dd

DV

dd

DVs

sC

Vss

CV

ddD

Vdd

CVs

s

C87 2 20p

F



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

C54

16 E

MIF

& A

SRA

M/F

LASH

EMIF

FLASH

ASRAM

64Kx16 and 256Kx16 Compatible

512K X 16 Compatible

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

314

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

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ocum

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of

DS

P_D

ATA

15

DS

P_A

DD

R10

DS

P_A

DD

R13

DS

P_A

DD

R16

DS

P_A

DD

R5

DS

P_A

DD

R0

DS

P_A

DD

R2

DS

P_A

DD

R21

DS

P_A

DD

R12

DS

P_A

DD

R1

DS

P_A

DD

R13

DS

P_A

DD

R19

DS

P_A

DD

R8D

SP

_AD

DR

6

DS

P_A

DD

R9

DS

P_A

DD

R14D

SP

_AD

DR

9

DS

P_A

DD

R15

DS

P_A

DD

R12

DS

P_A

DD

R6

DS

P_A

DD

R1

DS

P_A

DD

R0

DS

P_A

DD

R14

DS

P_A

DD

R3

DS

P_A

DD

R2

DS

P_A

DD

R11

DS

P_A

DD

R5

DS

P_A

DD

R17

DS

P_A

DD

R0

DS

P_A

DD

R14

DS

P_A

DD

R1

DS

P_A

DD

R18

DS

P_A

DD

R20

DS

P_A

DD

R4

DS

P_A

DD

R9

DS

P_A

DD

R6

DS

P_A

DD

R8

DS

P_A

DD

R4

DS

P_A

DD

R10

DS

P_A

DD

R13

DS

P_A

DD

R7

DS

P_A

DD

R3D

SP

_AD

DR

2

DS

P_A

DD

R7

DS

P_A

DD

R11

DS

P_A

DD

R12

DS

P_A

DD

R3

DS

P_A

DD

R7

DS

P_A

DD

R4

DS

P_A

DD

R8

DS

P_A

DD

R5

DS

P_A

DD

R22

DS

P_A

DD

R11

DS

P_A

DD

R10

DS

P_D

ATA

6

DS

P_D

ATA

4

DS

P_D

ATA

4

DS

P_D

ATA

15

DS

P_D

ATA

1

DS

P_D

ATA

13

DS

P_D

ATA

15

DS

P_D

ATA

8

DS

P_D

ATA

11

DS

P_D

ATA

13

DS

P_D

ATA

10

DS

P_D

ATA

7

DS

P_D

ATA

5

DS

P_D

ATA

8

DS

P_D

ATA

3

DS

P_D

ATA

3

DS

P_D

ATA

0

DS

P_D

ATA

0

DS

P_D

ATA

2

DS

P_D

ATA

6

DS

P_D

ATA

12

DS

P_D

ATA

14D

SP

_DA

TA10

DS

P_D

ATA

7

DS

P_D

ATA

5D

SP

_DA

TA11

DS

P_D

ATA

2

DS

P_D

ATA

2

DS

P_D

ATA

5

DS

P_D

ATA

13

DS

P_D

ATA

12

DS

P_D

ATA

4

DS

P_D

ATA

9D

SP

_DA

TA8

DS

P_D

ATA

12

DS

P_D

ATA

3

DS

P_D

ATA

6

DS

P_D

ATA

7

DS

P_D

ATA

14

DS

P_D

ATA

1

DS

P_D

ATA

11

DS

P_D

ATA

9

DS

P_D

ATA

14

DS

P_D

ATA

0

DS

P_D

ATA

9

DS

P_D

ATA

1

DS

P_D

ATA

10

DS

P_P

S#

DS

P_M

STR

B#

DS

P_R

/W#

DS

P_D

S#

DSP

_IO

STR

B#

DSP

_IS

#

DS

P_R

DY

AD

DR

17A

DD

R16

AD

DR

15

HP

_HO

LDA

#H

P_H

OLD

#

BR

D_R

ST#

FLA

SH

_CE

#

DS

P_A

DD

R[0

..22]

DS

P_D

ATA

[0..1

5]

AD

DR

16A

DD

R15

AD

DR

17A

DD

R18

AD

DR

19

FLA

SH

_OE

#

FLA

SH

_WE#

SR

AM

_WE

#S

RA

M_R

E#

DS

P_M

STR

B#

AD

DR

18

DG

ND

3 .3V

DG

ND

DG

ND

DG

ND

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

DG

ND

3.3V

DG

ND

DG

ND

C43

0.1u

F

C42

0.1u

FC

720.

1uF

R48

33

R4

10K

C61

0.1u

F

U12

TC55

V16

256F

T

1 2 3 4 5 18 19 20 21 22 2324 25 26 27 42 43 44

7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38

6 17 41 40 39

28

1133

1234

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

WE

OE

BH

EB

LE

NC

VDD1VDD2

VSS1VSS2

U7

AM

29LV

400B

2 1 48345678 9

10 13 14

161819202122232 42537 4627

26 28 11 1247

1529 31 33 35 38 40 4 2 44 30 32 34 36 39 41 43 4517

A14

A15

A16

A13

A12

A11

A10

A9

A8

A19

NC

1N

C2

NC

3

A18

A7

A6

A5

A4

A3

A2

A1

A0

VC

C

VS

SV

SS

CE

OE

WE

RE

SE

T

BY

TE

RY/

BY

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

/A-1

A17

R30

10K

R59

10K

U21

B

TMS

320V

C54

16-P

GE

25 7 8 9 10 11 143

141

140

139

138

137

136

134

133

132

131

123

122

121

119

118

117

116

115

114

113

110

109

108

107

105

104

103

102

101

100

99

19

20 21 22 23 24 252830

A22

A10

A11

A12

A13

A14

A15

A21

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10D

9D

8D

7D

6

A20

A19

A18

A17

A16

D5

D4

D3

D2

D1

D0

RE

AD

Y

PS

DS IS

R/W

MS

TRB

IOS

TRB

HO

LDA

HO

LD

R89

3 3

U13

SN

74LV

C1G

32

1 24

5 3


B-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MEM

OR

YA

DD

RES

SIN

G

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

414

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

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of

AD

DR

15

AD

DR

17

AD

DR

18

AD

DR

16

AD

DR

19

DS

P_D

S#

DM

_PG

3

DM

_PG

2

DM

_PG

1

DM

_PG

0

DS

P_A

DD

R17

DS

P_A

DD

R18

DS

P_A

DD

R16

DS

P_A

DD

R15

DM

_PG

4D

SP

_AD

DR

19

DG

ND

DG

ND

DG

ND

5V 5VD

GN

D

DG

ND

DG

ND

C63

0.1u

F

C64

0.1u

F

U15

SN

74C

BT3

257

4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VC

C

GN

D

U14

SN

74C

BT3

257

4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VC

C

GN

D

R57

33 R50

33



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BU

FFER

S

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

514

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

BD

SP

_AD

DR

7D

SP

_AD

DR

6

DS

P_A

DD

R11

BD

SP

_AD

DR

20

BD

SP

_AD

DR

14D

SP

_AD

DR

13

BD

SP

_AD

DR

18

BD

SP

_AD

DR

10

DS

P_A

DD

R22

BD

SP

_AD

DR

19

BD

SP

_AD

DR

16

BD

SP

_AD

DR

22

DS

P_A

DD

R7

DS

P_A

DD

R0

BD

SP

_AD

DR

17

BD

SP

_AD

DR

12

BD

SP

_AD

DR

15

DS

P_A

DD

R8

BD

SP

_AD

DR

9

DS

P_A

DD

R5

BD

SP

_AD

DR

13

DS

P_A

DD

R4

BD

SP

_AD

DR

4B

DS

P_A

DD

R3

DS

P_A

DD

R20

BD

SP

_AD

DR

21

DS

P_A

DD

R1

DS

P_A

DD

R21

DS

P_A

DD

R9

BD

SP

_AD

DR

0

BD

SP

_AD

DR

5

BD

SP

_AD

DR

2

BD

SP

_AD

DR

11D

SP

_AD

DR

10

BD

SP

_AD

DR

8

DS

P_A

DD

R14

DS

P_A

DD

R2

DS

P_A

DD

R3

DS

P_A

DD

R12

BD

SP

_AD

DR

6

BD

SP

_AD

DR

1

BD

SP

_DA

TA25

BD

SP

_DA

TA6

BD

SP

_DA

TA1

BD

SP

_DA

TA16

BD

SP

_DA

TA15

BD

SP

_DA

TA10

BD

SP

_DA

TA22

DS

P_D

ATA

14

DS

P_D

ATA

7

DS

P_D

ATA

15

BD

SP

_DA

TA14

BD

SP

_DA

TA1

BD

SP

_DA

TA29

BD

SP

_DA

TA8

BD

SP

_DA

TA5

BD

SP

_DA

TA31

BD

SP

_DA

TA8

BD

SP

_DA

TA9

BD

SP

_DA

TA28

BD

SP

_DA

TA26

DS

P_D

ATA

5

DS

P_D

ATA

8

DS

P_D

ATA

4

BD

SP

_DA

TA0

BD

SP

_DA

TA21

BD

SP

_DA

TA23

DS

P_D

ATA

9

DS

P_D

ATA

6

BD

SP

_DA

TA7

BD

SP

_DA

TA2

BD

SP

_DA

TA30

DS

P_D

ATA

12

BD

SP

_DA

TA9

BD

SP

_DA

TA3

BD

SP

_DA

TA20

BD

SP

_DA

TA11

BD

SP

_DA

TA19

BD

SP

_DA

TA5

BD

SP

_DA

TA6

DS

P_D

ATA

2

BD

SP

_DA

TA0

BD

SP

_DA

TA7

BD

SP

_DA

TA11

BD

SP

_DA

TA27

BD

SP

_DA

TA13

BD

SP

_DA

TA14

BD

SP

_DA

TA17

DS

P_D

ATA

10

BD

SP

_DA

TA12

BD

SP

_DA

TA24

DS

P_D

ATA

13

BD

SP

_DA

TA13

DS

P_D

ATA

0

BD

SP

_DA

TA4

BD

SP

_DA

TA15

BD

SP

_DA

TA10

BD

SP

_DA

TA2

BD

SP

_DA

TA18

BD

SP

_DA

TA3

DS

P_D

ATA

11

BD

SP

_DA

TA4

DS

P_D

ATA

3

BD

SP

_DA

TA12

DS

P_D

ATA

1

DSP

_DA

TA_D

IR

DS

P_D

ATA

_OE#

DS

P_A

DD

R[0

..22]

DS

P_D

ATA

[0..1

5]B

DS

P_D

ATA

[0..3

1]

BD

SP

_AD

DR

[0..2

2]

DB

_AB

CE

#D

B_B

AC

E#

DB

_AB

LE#

DB

_AB

OE

#

DB

_BA

LE#

DB

_BA

OE

#

DS

P_T

OU

TD

SP

_CLK

DS

P_R

DY

DS

P_X

F

DC

_CLK

DS

P_B

IO#

AD

DR

19A

DD

R18

AD

DR

17

DC

_BIO

#

AD

DR

16

DC

_TO

UT

DC

_RD

YH

P_C

LK

DC

_XF

AD

DR

15

DC

_CN

TL_O

E#

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

DG

ND

DG

ND

3.3V

3.3V

3.3V

R47

33

C66

0.1u

F

U5

SN

74LV

TH16

244

47 46 44 43

2 3 5 6

3945

7 1 83 142

8 9 1 1 12 13 14 16 17 19 20 22 23

41 40 3 8 37 36 35 33 32 30 29 27 26 1 48 25 24

4 10 15 21 28 34

1A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

GN

DG

ND

Vcc

Vcc

Vcc

Vcc

2Y1

2Y2

2Y3

2Y4

3 Y1

3Y2

3Y3

3Y4

4Y1

4Y2

4Y3

4Y4

2A1

2A2

2A3

2A4

3 A1

3A2

3A3

3A4

4A1

4A2

4A3

4A4

1OE

2OE

3OE

4OE

GN

DG

ND

GN

DG

ND

GN

DG

ND C62

0.1u

F

C37

0.1u

F

C41

0.1u

F

C40

0.1u

F

U11

SN

74LV

TH16

245

7 183142 47 46 44 43 41 40 3 8 37

2 3 5 6 8 9 1 1 1236 35 33 32 30 29 27 26

13 14 16 17 19 20 22 23

48 1 25 24 4 10 15 2 1

28 34 39 4 5

Vcc

Vcc

Vcc

Vcc

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2 A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

2 B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

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57 2250 35

6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 3 26 2 27 1 28 4 11 18 25

52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 54 31 55 30 56 29 32 39 46 53

1A1

Vcc

Vcc

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1A3

1A4

1A5

1A6

1A7

1A8

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2A4

2A5

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1B4

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8 9 11 12 13 14 16 17 19 20 22 23

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1A2

1A3

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1Y1

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GN

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3Y1

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P_D

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DG

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D

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RN

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R63

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DSP McBSP1

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

914

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

CO

DE

C_D

OU

T

CO

DE

C_F

SH

P_B

FSR

2

CO

DE

C_B

ITC

LKH

P_B

CLK

R2

BS

P2_

SEL

HP

_BFS

X2

HP

_BC

LKX2

HP

_BD

R2

DC

_BFS

R0

DC

_BD

R0

DC

_BC

LKR

1

DC

_BFS

X0

DC

_BFS

R1

DC

_BFS

X1

DC

_BC

LKX

0

DC

_BD

R1

DC

_BC

LKR

0

DC

_BC

LKX

1

DS

P_B

FSX0

DS

P_B

DX

0

DS

P_B

CLK

X0

DS

P_B

FSR

0D

SP

_BD

R0

DS

P_B

CLK

R0

DS

P_B

DX

1

DS

P_B

FSX1

DS

P_B

CLK

X1D

SP

_BD

R1

DS

P_B

FSR

1D

SP

_BC

LKR

1

HP

_BD

X2C

OD

EC_D

IN

DC

_BD

X0

DC

_BD

X1

DS

P_B

DX2

DS

P_B

DR

2

DS

P_B

FSR

2

DS

P_B

FSX2

DS

P_B

CLK

R2

DS

P_B

CLK

X2

DC

_IN

T1#

DC

_IN

T3#

DS

P_I

NT0

#D

C_I

NT0

#

DC

_IN

T2#

DS

P_I

NT2

#D

SP

_IN

T1#

DS

P_I

NT3

#

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

5V4.

1V_C

BT1

4.1V

_CB

T1

4.1V

_CB

T1

4.1V

_CBT

1

4.1V

_CBT

1

DG

ND

R94

1.6K

C91

0.1u

F

D5 LM

4040

DC

IM3-

4.1

21

C10

00.

1uF

U23

SN

74C

BTD

3384

1 133 4 7 8 1 1

2 5 6 9 1 0

14 17 18 21 22

24 1215 16 19 20 23

1 OE

2OE

1A1

1A2

1A3

1A4

1A5

1B1

1B2

1B3

1B4

1B5

2A1

2A2

2A3

2A4

2A5

Vcc

GN

D

2B1

2B2

2B3

2B4

2B5

U27

SN

74C

BTD

3384

1 133 4 7 8 11

2 5 6 9 10

14 17 18 21 22

24 1215 16 19 20 23

1OE

2OE

1A1

1A2

1A3

1A4

1A5

1B1

1B2

1B3

1B4

1B5

2A1

2A2

2A3

2A4

2A5

Vcc

GN

D

2B1

2B2

2B3

2B4

2B5

C99

0.1u

FC98

0.1u

F

U26

SN

74C

BT3

257

4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2 S

1B1

OE

3B2

1B2

2B1

2B2

VC

C

GN

D

U25

SN

74C

BT3

257

4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2 S

1B1

OE

3B2

1B2

2B1

2B2

VC

C

GN

D


B-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+3.3V & +1.6V DIGITAL VOLTAGE REGULATOR

EXTERNAL POWER PLUG

INPU

T PO

WER

(DO NOT POPULATE)

ALTERNATE EXTERNAL POWER

SWITCHCRAFT RAPC712 PLUG

DSP CORE & I/O DIFFERENTIAL VOLTAGE PROTECTION

Res

et

Pow

er-O

n

OPTIONAL

DAUG

HTER

CARD

STA

NDO

FF G

ROUN

DING

KE

EP T

RA

CE

S A

MIN

IMU

MO

F 0.

070

INC

HE

S F

RO

MTH

ES

E H

OLE

S.

R104-R107, 1206 BODY

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

1014

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

MA

N_R

ST#

BR

D_R

ST#

BR

D_R

ST

PO

NR

Sn

US

B-1

.6V

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

12V

#

1.6V

3.3V

3.3V

12V

5V

DG

ND

5V_I

N5V

5V

DG

ND

DG

ND

1.6V

3.3V

DG

ND

1.6V

DG

ND

DG

ND

DG

ND

DG

ND

5V

DG

NDR

106

100

R10

710

0

JP2

HEA

DE

R 2

x1

1 2

JP3

HE

ADE

R 2

x1

1 2

R10

21K

R90

0

R10

1

150

R66

0

M4

125_

PH

M2

125_

PH

R10

410

0

R10

510

0

D17

MM

BD41

48

13

D8

Red

R24

90

J5

4-pi

n M

olex

1234

+12

-12

GN

D+5

+C

T13

10uF

R92

732K

, 1%

R84

93.1

K, 1

%

R81

1K

U28

TPS

3307

-18D

8

71 2 346 5

VD

D

MR

SE

NS

E1

SE

NS

E2

SE

NS

E3

GN

D

RE

SE

TR

ES

ET

+C

T11

10uF

C10

5

0.1u

F

C10

1

0.1u

F

C95

0.1u

F

R76

10.7

K, 1

%

R77

30.1

K, 1

%

+C

T25

10uF

J6 RA

SM

712

123

+C

T12

47uF

M3

125_

PH

R79 33

R78 33

U24

TPS

767D

301

5 6 4 3 11 12 10 9 1 2 7 8 13 14

15 16 20 21 26 2728 23 24 25 22 17 18 19

1IN

1IN

1EN

1GN

D

2IN

2IN

2EN

2GN

D

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

1RE

SE

T

1OU

T1O

UT

1FB

/SE

NS

E

2RE

SE

T

2OU

T2O

UT

2SE

NS

E

R24

70

R24

60

M1

125_

PH

+C

T16

47uF

D7

Gre

en

C10

2

0.1u

F

D2

MM

BD

4148

13

D1

MM

BD

4148

13

+C

T15

10uF

+C

T14

47uF

D3

MM

BD

4148

13



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

JTAG MULTIPLEXERS

Emul

atio

n In

terf

ace

DSP JTAG HEADER

Not Installed

US

BE

MB

ED

DE

DE

MU

CBT VOLTAGE DIVIDER

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

1114

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

XD

S_T

DI

XDS_

TMS

XD

S_T

RST

#

XD

S_T

DO

XD

S_T

DO

XD

S_T

MS

XD

S_TR

ST#

XD

S_T

DI

XD

S_E

MU

1

XD

S_ T

CK

XD

S_E

MU

0

XD

S_E

MU

1

EM

U_S

TS

XD

S_E

MU

0

XD

S_T

CK

TBC

_TM

S

TBC

_TD

I

TBC

_TD

O

TBC

_CLK

TBC

_EM

U0

TBC

_EM

U1

TBC

_TR

ST#

XD

S_T

VD

EM

U_S

TS

T_TR

STn

T_TM

S

T_TD

I

T_EM

U1

T_EM

U0

T_TC

K_R

ETT_

TCK

T_TD

OD

SP

_TD

O

DS

P_T

CK

DS

P_T

MS

DS

P_E

MU

1

DS

P_T

DI

DS

P_E

MU

0

DS

P_T

RST

#

BR

D_R

ST

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

3.3V

3.3V

3.3V

3.3V

DG

ND

DG

ND

4.1V

_CB

T3

4.1V

_CB

T3

5V4.

1V_C

BT3

DG

ND

R65

0

R10

015

0

R87 33

R91

1K

R93

1.6K

R99

0

C97

0.1u

F

C96

0.1u

F

D6

Gre

en

U29

SN

74C

BT3

257

4

14

711

9 1213 12 1 5103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VC

C

GN

D

R86

NP

J7

TSW

-107

-14-

G-D

-006

1 3 5 7 9

2 4 8 1011

1213

14

U30

SN

74C

BT3

257

4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VC

C

GN

D

R85

33

D4 LM

4040

DC

IM3-

4.1

21


B-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Hie

rarc

haric

al B

lock

s

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

1214

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

US

B/E

mul

atio

n

US

B/E

mul

atio

n

5V

US

B_D

SP

_RS

T#

T_TD

O

T_TC

KT_

TMS

T_TR

STn

T_E

MU

0T_

EM

U1

T_TD

I

DG

ND

US

B_1

.6V

3.3V

PO

NR

Sn

GN

D

T_TC

K_R

ET

Anal

og

Anal

og

5V

DG

ND

CO

DE

C_C

LKC

OD

EC

_BIT

CLK

CO

DE

C_F

SC

OD

EC

_DIN

CO

DE

C_D

OU

T

CO

DE

C_M

CC

OD

EC

_MD

CO

DE

C_M

L

BR

D_R

ST#

CO

DE

C_S

YS

CLK

BR

D_R

ST#

CO

DE

C_D

INC

OD

EC

_FS

CO

DE

C_B

ITC

LK

CO

DE

C_M

DC

OD

EC

_ML

CO

DE

C_M

C

US

B_D

SP

_RS

T#

T_TD

IT_

TMS

T_TC

K

T_E

MU

0T_

EM

U1

T_TD

O

CO

DE

C_D

OU

T

CO

DE

C_C

LK

PO

NR

Sn

US

B-1

.6V

CO

DE

C_S

YS

CLK

T_TR

STn

T_TC

K_R

ET

DG

ND

5V5V

DG

ND

3.3V



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LINE IN

3.5 MM AUDIO JACK

LIN

E IN

& M

IC IN

MIC IN INSTALL FOR TABLE

TOP OPERATION

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

1314

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

VM

ID_A

UD

IO

LIN

E_I

N_R

LIN

E_I

N_L

VMID

_AU

DIO

VMID

_AU

DIO

VM

ID_A

UD

IO VMID

_AU

DIO

VMID

_AU

DIO

VM

ID_A

UD

IO

AS

HIE

LD

LIN

E_M

IC_I

N_L

LIN

E_M

IC_I

N_R

3.3V

A

AG

ND

3.3V

A

AG

ND

AG

ND

AG

ND

3.3V

A

3.3V

A

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

C7

NU

R33

200K

R19

10K

, 1%

R17

10K,

1%

R16

10K

, 1%

R35

10K

, 1%

- +

U3A

TLV2

444

321

4 11R

4230

1, 1

%

R32

10K

, 1%

R37

10K

, 1%

C46

1uF

C49 0.

01uF

R41

10K

, 1%

R12

10K

, 1%

R36

10K

, 1%

R10

10K,

1%

C45

0.1u

F

C50

47pF

, NP

O

J1

Mic

In

3 4 2 1

R10

90

R10

80

L3 Ferri

te C

hip

L2

Ferri

te C

hip

L1 Ferri

te C

hip

J2

Line

In

3 4 2 1

C8

1uF

R31

10K

, 1%

R18

10K,

1%

C9

220p

F

R7

5.11

K, 1

%

- +U3C

TLV2

444

1098

+C

T210

uF

R9

10K

, 1%

C22

47pF

, NP

O

R34

10K

, 1%

C2 NU

- +U2B

TLV

2444

567

- +U3B

TLV2

444

567

R1

0

- +U2C

TLV2

444

1098

C48

47pF

, NP

O

- +U2D

TLV2

444

121314

C5

1uF

R6

1K

R15

10K

, 1%

- +U3D

TLV2

444

121314

R20

10K,

1%

C20

1uF

C51 0.

01uF

R38

10K

, 1%

R14

10K,

1%

C6

220p

F

R8

10K,

1%

- +

U2A

TLV

2444

321

4 11

C47

47pF

, NP

O

C21

0.1u

F

R40

301,

1%

R39

10K

, 1%

R13

10K

, 1%

C19 220p

F

C10

NU

C23

0.1u

F

R11

1 00K

, 1%


B-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AU

DIO

CO

DEC

/OU

TPU

T

+5V & +5VA POWER

LINE OUT

3.5 MM AUDIO JACK

SPEAKER/HEADPHONE

OUT

3.5 MM AUDIO JACK

Ferri

te C

hip

Ferri

te C

hip

5060

02C

C54

16 D

SP

Sta

rter K

it

Spec

trum

Dig

ital I

ncor

pora

ted

B

1414

Wed

nesd

ay, M

arch

20,

200

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

Vco

m

Vco

m

Vco

m

AS

HIE

LD

LIN

E_R

LIN

E_L

SP

EA

K_L

SP

EA

K_R

LIN

E_M

IC_I

N_L

LIN

E_M

IC_I

N_R

DG

ND

3.3V

A

AG

ND

5VA

AG

ND

AG

ND

3.3V

A

AG

ND

DG

ND

DG

ND

5V

AG

ND

AG

ND

AG

ND

3.3V

A

AG

ND

AG

ND

AG

ND

3.3V

A

AG

ND

AG

ND

3.3V

DG

ND

AG

ND

AG

ND

AG

NDA

GN

D

3.3V

3.3V

DG

ND

AG

ND

R55

10K

C27

220p

F

L13

Ferri

te C

hip

R24

15K

, 1%

C29

1uF

+C

T310

uF

- +

U4A

OP

A23

40

321

8 4

U17 12

.288

MH

z

24 31

GN

D

VD

D

OU

TE/

D

C33

220p

F

C55

0.1u

F

+C

T147

uF

R44

10K

1%

C25

0.1u

F

C56

1uF

R21

100

1%

+

CT6

68uF

R23

3.83

K, 1

%C

5410

pF

R28

3.83

K, 1

%

L8 Ferri

te C

hip

C35

NU

C34

NU

L4

C11

NU

L5 C30

NU

C52

0.1u

F

R29

10K

1%

C16

NU

R11

10

R11

00

+C

T910

uF

L 9 Ferri

te C

hip

J3 Line

Out

3 4 2 1

U9

TPA3

02

1

23456 7

8Vo

utL

SH

TDW

NB

YB

ASS

Vin

RV

outR

VD

D

GN

D

Vin

L

R45

30.1

K, 1

%

C15

NU

+C

T747

uF

R43

30.1

K, 1

%

C75

0.1

L14

Ferri

te C

hip

C14

NU

R26

100

1%

R27

15K

, 1%

C12

NU

- +U4B

OP

A23

40

567

J4 Line

Out

3 4 2 1

R56

33

U8

PC

M30

02E

1 234 56 7 89 1011 12 1314 15 161718

19 20 21 22 2324

AV

CC

AV

CC

VinR

Vref

L

Vref

R

VinL

RS

T

ML

SYS

CLK

LRC

INBC

LKIN

DO

UT

DG

ND

VD

D

DIN

ZFLG

MD

MC

Vout

L

Vou

tR

Vco

m

AG

ND

AG

ND

AV

CC

C53

0.1u

F

C57

10pF

R25

3.83

K, 1

%

C28

0.1u

F

+C

T8

10uF

U1

TPS

7753

3D

3 45 6 7

2 18

Vin

Vin

Vou

tV

out

SE

NS

EE

N

GN

DR

ES

ET

C44

0.01

uF

+

CT5

68uF

C26

2200

pF

L7Ferri

te C

hip

+C

T410

uF

R22

3.83

K, 1

%

L6 Ferri

te C

hip

C31

2200

pF

C1

0.1u

F

C32

0.1u

F

C24

1uF

BR

D_R

ST#

CO

DE

C_C

LK

CO

DE

C_D

OU

T

CO

DE

C_B

ITC

LKC

OD

EC

_FS

CO

DE

C_D

IN

CO

DE

C_M

CC

OD

EC

_MD

CO

DE

C_M

L

5V

DG

ND

CO

DE

C_S

YSC

LK



C-1

Appendix C

TMS320VC5416 DSK List of materials

This appendix contains the list of materials for the TMS320VC5416 DSK.


C-2 TMS320VC5416 DSK Module Technical Reference

Table 1: TMS320VC5416 List of Materials

Item Qty Title Mfr Name PWB Ref # Mfr P/N

1 1 PWB,TMS320VC5416 USB DSK

SPECTRUM DIGITAL, INC.

2 1 LOGIC,TMS320VC5416 USB DSK

SPECTRUM DIGITAL, INC.

3 1 ASSY,EMBEDDED USB EMULATOR

SPECTRUM DIGITAL,INC.

4 1 FPGA ALTERA U18 EPM3128ATC144-10

5 1 IC,PQFP,TMS320VC5416PGE-160

TEXAS INSTRUMENTS U21 TMS320VC5416PGE-160

6 1 IC,TSOP44,SRAM,64K x 16,12nS

ISSI U12 IS61LV6416-12T

7 1 IC,TSOP48,FLASH,70nS ADVANCED MICRO DEVICES, INC

U7 AM29LV400BT-70EC

8 1 IC,TSSOP48,3.3V,16-BIT TRANSCEIVER

TEXAS INSTRUMENTS U11 SN74LVTH16245ADGGR

9 2 IC,TSSOP48,3.3V,16-BIT BUFFER/DRIVER

TEXAS INSTRUMENTS U5,U10 SN74LVTH16244ADGGR

10 1 IC,TSSOP56,3.3V,16-BIT TRANSCEIVER

TEXAS INSTRUMENTS U6 SN74LVTH16543DGGR

11 2 IC,TSSOP24,10-BIT FET BUS

SWITCH,74CBTS3384

TEXAS INSTRUMENTS U23,U27 SN74CBTS3384PW

12 1 IC,MSOP8,OP AMP BURR-BROWN CORPORATION

U4 OPA2340EA/250

13 6 IC,QSOP16,QUAD 2:1 MULTIPLEXER /

DEMULTIPLEXER

QUALITY SEMICONDUCTOR INC.

U14,U15,U25,U26,U29,U30

QS3257Q

14 1 IC,SSOP24,STEREO AUDIO CODEC

BURR-BROWN CORPORATION

U8 PCM3002E

15 1 IC,SO8,STEREO AUDIO POWER

AMPLIFIER,300mW

TEXAS INSTRUMENTS U9 TPA302D

16 2 IC,TSSOP14,OP AMP, LOW VOLTAGE

TEXAS INSTRUMENTS U2,U3 TLV2444CPWR

17 1 IC,SOIC,3.3V,1A LOW-DROPOUT VOLTAGE

REGULATOR,TPS76733

TEXAS INSTRUMENTS U31 TPS76733QD

18 1 IC,SOIC,3.3V,500mA LOW-DROPOUT

VOLTAGE REGULATOR,TPS77533

TEXAS INSTRUMENTS U1 TPS77533D

19 1 IC,SSOP28,DUAL LOW-DROPOUT VOLTAGE

REGULATOR

TEXAS INSTRUMENTS U24 TPS767D301PWP

20 1 IC,SO8,TRIPLE SUPERVI-SORY CIRCUIT,3.3V

TEXAS INSTRUMENTS U28 TPS3307-18D

21 1 IC,SOT23-5,SINGLE CMOS OR GATE

TEXAS INSTRUMENTS U13 SN74LVC1632DBBK

22 1 OSC,SMT,12.288 MHZ CTS ELECTRONICS CORPORATION

U17 CB3LV-3C-12.288T

23 1 OSC,SMT,16 MHZ CTS ELECTRONICS CORPORATION

U16 CB3LV-3C-16.000T


C-3

24 2 DIODE,SOT23,REFERENCE,4.1V

NATIONAL SEMICON-DUCTOR

D4,D5 LM4040CIM3-4.1

25 4 DIODE,SOT23,SWITCHING

ZETEX INC. D1,D2,D3,D17 BAS16TA

26 1 LED,SMT 1206,YELLOW LUMEX, INC. D8 SML-LX1206YC-TR

27 6 LED,SMT 1206,GREEN LITEON D6,D7,D9,D10,D11,D12

LTST-C150GKT

28 12 FERRITE BEAD,SMT 0805,600 OHMS

STEWARD L1,L2,L3,L4,L5,L6,L7,L8,L9,L13,L14,

L15

HZ0805E601R-00

29 2 CAP,CER,SMT 0603,10pF,50V,

+/-.5pF,NPO

PANASONIC C54,C57 ECU-V1H100DCV

30 4 CAP,CER,SMT 0603,47pF,50V,

+/-5%,NPO

PANASONIC C22,C47,C48,C50 ECU-V1H470JCV

31 2 CAP,CER,SMT 0603,2200pF,50V,

+/-10%,X7R

PANASONIC C26,C31 ECUV1H222KBV

32 6 CAP,CER,SMT 0603,220pF,50V,

+/-5%,NPO

PANASONIC C6,C9,C19,C27,C33,C87

ECU-V1H221JCV

33 4 CAP,CER,SMT 0603,.01uF,50V,

+/-10%,X7R

AVX CORPORATION C44,C49,C51,C104 06035C103KAT2A

34 63 CAP,CER,SMT 0603,.1uF,16V,

+/-10%,X7R

PANASONIC C1,C17,C18,C21,C23,C25,C28,C32,C36,C37,C38,C39,C40,C41,C42,C43,C45,C52,C53,C55,C58,C59,C60,C61,C62,C63,C64,C65,C66,C67,C68,C69,C70,C71,C72,C73,C74,C75,C76,C77,C78,C79,C80,C83,C84,C85,C86,C88,C89,C91,C92,C93,C94,C95,C96,C97,

C98,C99,C100,C101,C102,C103,

C105

ECJ-1VB1C104K

35 7 CAP,CER,SMT 0603,1uF,6.3V,X5R,

+/-10%

PANASONIC C5,C8,C20,C24,C29,C46,C56

ECJ-1VB0J105K

36 12 CAP,TANT,TEH SERIES,SMT

1206,10uF,6.3V

PANASONIC CT2,CT3,CT4,CT8,CT9,CT11,CT13,CT15,CT17,CT23,

CT24,CT25

ECS-TOJY106R

37 2 CAP,TANT,SMT 2816,68uF,6.3V

PANASONIC CT5,CT6 ECS-T0JY106R

38 5 CAP,TANT,SMT 2816,47uF,10V

PANASONIC CT1,CT7,CT12,CT14,CT16

ECS-T1AD476R

39 4 RES,SMT,1206 120 OHM, 5%, 1/4 WATT

PANASONIC R104,R105,R106,R107

ERJ-8GEYJ121V

40 3 RES,SMT 0603,100 OHM,1%,1/16 WATT

ROHM CORPORATION R21,R26,R103 MCR03F1000EZP





41 22 RES,SMT 0603,10K OHM,1%,1/16 WATT

KOA SPEER ELECTRONICS, INC.

R8,R9,R10,R12,R13,R14,R15,R16,R17,R18,R19,R20,R29,R31,R32,R34,R35,R36,R37,R38,

R39,R41,R44

RK73H1J1002F

42 1 RES,SMT 0603,100K OHM,1%,1/10 WATT

ROHM CORPORATION R11 MCR03F1003EZP

43 1 RES,SMT 0603,10.7K OHM,1%,1/16 WATT

PANASONIC R76 ERJ-3EKF1072V

44 2 RES,SMT 0603,200K OHM,1%,1/10 WATT

PANASONIC R43,R45 ERJ-3EKF2003V

45 2 RES,SMT 0603,301 OHM,1%,1/16 WATT


46 4 RES,SMT 0603,3.83K OHM,1%,1/10 WAT”

PANASONIC R22,R23,R25,R28 ERJ-3EKF3831V

47 1 RES,SMT 0603,30.1K OHM,1%,1/10 WATT


48 1 RES,SMT 0603,5.11K OHM,1%,1/10 WATT


49 2 RES,SMT 0603,15K OHM,1%,1/16 WAT”


50 1 RES,SMT 0603,732K OHM,1%,1/10 WATT


51 1 RES,SMT 0603,93.1K OHM,1%,1/10 WATT


52 8 RES,SMT 0603,0 OHM,1/10 WATT


R5,R65,R86,R99,R108,R109,R110,

R111

RM73Z1J000

53 4 RES,SMT 0603,1K OHM,5%,1/16 WATT


R6,R81,R91,R102 RM73B1JT102J

54 14 RES,SMT 0603,10K OHM,5%,1/16 WATT KOA SPEER

ELECTRONICS, INC.

R2,R3,R4,R30,R51,R54,R55,R59,R67,R68,R69,R70,

R71,R72

RM73B1JT103J

55 2 RES,SMT 0603,1.6K OHM,5%,1/16 WATT

PANASONIC R93,R94 ERJ-3GEYJ162V

56 6 RES,SMT 0603,150 OHM,5%,1/16 WATT

PANASONIC R95,R96,R97,R98,R100,R101

ERJ-3GEYJ151V

57 19 RES,SMT 0603,33 OHM,5%,1/16 WATT


R46,R47,R48,R49,R50,R52,R53,R56,R57,R58,R62,R63,R78,R79,R82,R83,

R85,R87,R89

RM73B1JT33RJ

58 2 RES,SMT 0603,4.7K OHM,5%,1/16 WATT


R60,R61 RM73B1JT472J

59 2 RES,SMT 0603,20K OHM,5%,1/16 WATT


R29,R44 RM73B1JT203J

60 3 RES,SMT 1206,0 OHM,1/8 WATT

XICON PASSIVE COMPONENTS

R1,R66,R90 263-0

61 1 POT,SMT,5mm SQ.,200K,1/4 WATT,

SINGLE TURNBOURNS

R33 3314J-1-204

62 5 RES,NETWORK,SMT,16 PIN,8 RES,10K

OHM,5%,1/16 WATT

CTS ELECTRONICS CORPORATION

RN1,RN2,RN3,RN4,RN5

742163103J




C-5

63 1 SWITCH,SMT,PUSHBUTTON,

MOMENTARY,.25 SQ.C&K/UNIMAX, INC.

S1 KT11P2JM

64 1 SWITCH,DIP,SMT,4 POSITION

CTS ELECTRONICS CORPORATION

S2 193-MS

65 1 HEADER,4 X 2,VERTICAL,PIN

SPECTRUM DIGITAL INC.

JP4



JP1



J7

68 1 CONN,JACK,RIGHT ANGLE,POWER,2.5mm

SWITCHCRAFT J6 RASM712

69 3 CONN,SMT,VERTICAL,

RECEPTACLE,40X2AMP INCORPORATED

P1,P2,P3 104652-8

70 4 CONN,SMT,JACK,STEREO,4 POS.,3.6mm

KYCON CABLE & CONNECTOR, INC.

J1,J2,J3,J4 ST-3500-4N

71 4 BUMPER,CYLINDRICAL,SELF-

STICK,BLACK,.88 DIA.

3M ELECTRONIC PRODUCTS DIV.

SJ-5009(BLACK)





D-1

Appendix D

TMS320VC5416 DSK Mechanical Information

This appendix contains the mechanical information about theTMS320VC5416 DSK produced by Spectrum Digital.


D-2 TMS320VC5416 DSK Module Technical Reference

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Printed in U.S.A., March 2002506005-0001 Rev. A

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