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1 | ©2014 Micron Technology, Inc. Todd Farrell Senior Member Technical Staff Computing and Networking BU [email protected]
1 | ©2014 Micron Technology, Inc.
Todd Farrell
Senior Member Technical Staff Computing and Networking BU
2 | ©2014 Micron Technology, Inc.
Demand Drivers
Insatiable need for bandwidth
Impact of the cloud
Global demand for mobility
Big data analytics challenge
April 28, 2014
Annual Data Center IP Traffic 2012-2017 CAGR: 25%
Source: Cisco Global Cloud Index 2013
SOCs & Microservers
High-Performance Computing
Acceleration & Co-Processing
Enterprise Computing
0
2,500
5,000
7,500
10,000
2012 2013 2014 2015 2016 2017
Data Center to User
Data Center to Data Center
Within Data Center
EB/Yr
3 | ©2014 Micron Technology, Inc.
0
15
30
45
60
75
90
2015 2014 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2001 2000 1999 1998 1997
Traditional Memory Designs Do Not Scale and Drive Exponential Complexity
Historical System Bandwidth, Cost, and Complexity
April 28, 2014
1-2 Memory Channels Up to 6.4GB/s
85 page specification <3 Yrs to Standardize
DDR
2 Memory Channels Up to 10.7GB/s
3 Speed Bins
DDR2
3-4 Memory Channels 240 Pins Per DIMM
Up to 59.7GB/s 5 Speed Bins
DDR3
4 Memory Channels 284 Pins Per DIMM
Up to 85GB/s 12 Speed Bins
6+ yrs to Standardize
DDR4
Bandwidth Per Memory Channel
2012–2017 CAGR: 12.3%
GB/s
4 | ©2014 Micron Technology, Inc.
Major Challenges to the Longevity of DRAM and NAND Technologies
Memory Process Nodes Over Time
Physical process limits?
Endurance
•Cycling capabilities
Shrink
•Physical limitations
Equipment capability
•Increasing equipment complexity
Cost
•Path of diminishing returns
-
0.020
0.040
0.060
0.080
0.100
0.120
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
DRAM Industry NAND Industry
New memory
April 28, 2014
5 | ©2014 Micron Technology, Inc.
HMC - A Revolutionary Shift
Increased Bandwidth
Greater Power Efficiency
Lower TCO
Reduced System Latency
Smaller, Scalable and
Flexible
April 28, 2014
6 | ©2014 Micron Technology, Inc.
High-Performance Memory Comparison
April 28, 2014
Requirements TCO Valuation
Bandwidth
Energy Efficiency
Board Footprint
Channel Complexity 90% simpler than DDR3L 88% simpler than DDR4
95% smaller than DDR3L 94% smaller than DDR4
66% greener than DDR3L 55% greener than DDR4
10.2X greater than DDR3L 8.5X greater than DDR4
Single-Link HMC vs. DDR3L-1600 and DDR4-2133 What does it take to support 60 GB/s?
0 250 500 750
HMC
DDR4
DDR3L
pins
0 3,000 6,000 9,000
HMC
DDR4
DDR3L
mm2
0 20 40 60
HMC
DDR4
DDR3L
pJ/b
0 300 600 900
HMC
DDR4
DDR3L
MB/pin
7 | ©2014 Micron Technology, Inc.
Innovative Design & Process Flow
Incorporates thousands of TSV sites per die to reduce signal lengths and power
Enables memory scalability through parallelism
Sophisticated Package Assembly
Provides higher component density and significantly improves signal integrity
Enabling Technologies
Memory Vaults vs. DRAM Arrays
Significantly improves bandwidth, quality, and reliability vs. traditional DRAM technologies
Logic Base Controller Reduces memory complexity and
significantly increases performance
Allows memory to scale with CPU performance
Abstracted Memory Management
Through-Silicon Via (TSV) Assembly
April 28, 2014
8 | ©2014 Micron Technology, Inc.
Traditional Host Processor Memory Management
HOST
DRAM Layer
DRAM Layer
DRAM Layer
DRAM Layer
TSV
TSV
TSV
TSV
TSV
TSV
TSV
TSV
Re-drive Layer
Si Interposer
Manufacturing Test
Burn-in
At-speed functional
Manage field maintenance and
self test
Manage all present and future DRAM scaling and process variation issues
Manage 100+ different DRAM timing parameters
Non-Managed DRAM (DDR, WIO2, HBM, etc.)
April 28, 2014
9 | ©2014 Micron Technology, Inc.
Simple HMC Memory Management
HOST
DRAM Layer
DRAM Layer
DRAM Layer
DRAM Layer
TSV
TSV
TSV
TSV
TSV
TSV
TSV
TSV
Re-drive Layer
Si Interposer
Manufacturing Test
Burn-in
At-speed functional
Manage field maintenance and
self test
Manage all present and future DRAM scaling and process variation issues
Manage 100+ different DRAM timing parameters
Simple memory requests and responses;
No DRAM timings or scaling issues to manage
Functions moved to HMC for management
Non-Managed DRAM (DDR, WIO2, HBM, etc.)
April 28, 2014
10 | ©2014 Micron Technology, Inc.
HMC Architecture
Vaults are managed to maximize overall device availability -
Optimized management of energy and refresh
Self test, error detection, correction, and repair in the logic base layer
3DI & TSV Technology
DRAM0 DRAM1
DRAM2
DRAM3 DRAM4
DRAM5
DRAM6 DRAM7
Logic Chip
Logic Base
Multiple high-speed local buses for data movement
Advanced memory controller functions
DRAM control at the memory rather than at distant host controller
Reduced memory controller complexity and increased efficiency
DRAM
Logic Base
Vault
Memory Control
Vault Control
DRAM Sequencer
Crossbar Switch
Write Buffer
Read Buffer
Refresh Controller R
equest
Write
Data
Read D
ata
DRAM Repair
TSV Repair
Detail of Memory Interface
Vault Control Vault Control Vault Control
Memory Control
Crossbar Switch
Link Interface Controller
Link Interface Controller
Processor Links
Link Interface Controller
Link Interface Controller
Logic Base
April 28, 2014
11 | ©2014 Micron Technology, Inc.
HMC Architecture Link Controller Interface
April 28, 2014
RX
TX
Host
TX
RX
HMC
16 Lanes
16 Lanes
8 or 16 Transmit Lanes
8 or 16 Receive Lanes
Example:
HMC-SR Options: 10 Gb/s, 12.5 Gb/s,
or 15 Gb/s Crossbar Switch
BIST
Processor Links
Link Interface Controller
Link Interface Controller
Logic Base
Vault Control Vault Control Vault Control Vault Control
Memory Control
Memory Control
Memory Control
Memory Control
12 | ©2014 Micron Technology, Inc.
Packet-Based Communication
Packets comprised of 128-bit (16-byte) FLITs
Packets include 1 to 9 FLITs, depending on command
Host issues requests & HMC issues responses
Each packet contains 64-bit header and 64-bit tail (1 FLIT)
April 28, 2014
Protocol NOT affected by any DRAM-related timings, nor is it
DRAM-specific!
Multiple data transfer sizes supported (16B to 128B)
Commands include reads, writes, atomics, error responses
Simultaneous READs and WRITEs supported
13 | ©2014 Micron Technology, Inc.
HMC Reliability Built-in RAS features
Logic / Interface
DRAM Array
Logic / Interface
DRAM Array
Logic / Interface
DRAM Array
Logic / Interface
DRAM Array
Host Vault data ECC-protected
Address/command parity for array
transactions
CRC protection on link interface
Link retry
Logic stability (DRAM controls in logic)
Reliable handshake (packet integrity verified before memory access)
April 28, 2014
14 | ©2014 Micron Technology, Inc.
RAS Feature System Comparison
April 28, 2014
15 | ©2014 Micron Technology, Inc. April 28, 2014
HMC Standard Packages
Standard BGA packaging solutions: Cost-effective packaging using existing ecosystems
MCM and In-Package options available
Up to 1.28 Tb/s memory bandwidth available TODAY!
16 | ©2014 Micron Technology, Inc.
HMC Maximum Bandwidth Configurations
April 28, 2014
All links between host CPU and HMC logic layer
▶Maximum bandwidth per GB capacity:
HPC/Server – CPU/GPU
Graphics
Networking systems
Test equipment
17 | ©2014 Micron Technology, Inc.
HMC Scalable Memory Solutions
April 28, 2014
Far Memory:
Some HMC links connect to host – some to other cubes
Scalable to meet system requirements
Available in module form or soldered-down
Building blocks for multiple application needs
Future Products May Include:
Higher-speed electrical (SERDES) VSR-30
Optical interfaces (align to industry stds.)
Higher stack count for greater capacity
Non-DRAM memory technologies
Additional Atomic Operations inside Cube
18 | ©2014 Micron Technology, Inc.
Hybrid Memory Cube
Micron Memory Innovation We’ve combined fast logic process technology and advanced DRAM designs to create an entirely new category of memory. Hybrid Memory Cube (HMC) technology provides a high-bandwidth, low-energy, high-density memory system that’s unlike anything on the market today. . Unprecedented Performance
HMC will provide a revolutionary performance shift that will enrich next-generation networking and enable exaflop-scale supercomputing:
Reduced Footprint 90% less space than today’s RDIMMs
Reduced Power Fraction of the energy per bit
* HMC SR-15G vs. DDR3-1333
Increased Bandwidth 15X the performance of DDR3*
April 28, 2014
19 | ©2014 Micron Technology, Inc.
“…like adding a turbocharger to your computer”
- datacenteracceleration.com
“…unprecedented levels of memory performance”
- Electronic News
Industry Validation
“…get ready for some serious bandwidth to hit us in
the near future”
- tweaktown.com
EE Times 40th Anniversary: “one of the top ten technologies expected
to redefine the industry”
April 28, 2014
20 | ©2014 Micron Technology, Inc.
Consortium Momentum
http://www.hybridmemorycube.org
April 28, 2014
21 | ©2014 Micron Technology, Inc.
Milestones
April 28, 2014
2 0 1 1 2 0 1 2
2/11 - Micron announces the
development of HMC technology
10/11 - Micron and Samsung launch the HMC Consortium with fellow developers Altera, Open-
Silicon, and Xilinx
12/11 - HMC wins Linley Group’s Analyst Award
for Best New Technology of 2011
12/11 - IBM joins the HMCC as a developer
9/11 - Micron and Intel demonstrate Micron’s HMC Gen1
device and an Intel MIC CPU memory interface at IDF 2011
9/13 – Micron sampling 2GB HMC device
5/12 - ARM and SK Hynix join the HMCC as
developers
9/13 - Micron and Altera demo industry’s first FPGA and HMC
interoperability
4/13 – HMCC releases final HMC Spec 1.0 to
public 5/12 - HMC Spec 1.0 released to adopters for
review
2 0 1 3 2 0 1 4
4/13 – HMC named Memory Product of the Year
2/14 - HMC Spec 2.0 released to adopters for
review
11/13 – HMC part of Fujitsu next-gen supercomputer
12/13 – HMCC Developer Group membership final – ARM, Altera, IBM,
Micron, Open-Silicon, Samsung, SK Hynix and Xilinx
10/13 – HMCC adopter membership
tops 120
4/14 - HMC Stratix V Team named Design
Team of the year
22 | ©2014 Micron Technology, Inc.
HMC - A Revolutionary Shift
Increased Bandwidth
Greater Power Efficiency
Lower TCO
Reduced System Latency
Smaller, Scalable and
Flexible
April 28, 2014
©2014 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS”
basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
23 | ©2014 Micron Technology, Inc.
Thank You!
