Top-down Design System Description Freehand Approach (recommended) Build system with Platform Creator Build software manually Build and run simulation in System Verifier Lab 15 Building a Top-down System Guided Approach (optional) Build system with Platform Creator Top Down Flow Wizard Use automated software build Build and run simulation from Platform Creator Lab 16 Building a Design with the Top-down Flow WizardSoftware rev: 2005.1.0Doc. rev: 22Apr05
To illustrate top down design, we will build a small system. This is the block diagram.Instructioni_AHBProcessorDataROMRAMi_ClockA simple system to perform shift operations on unsigned int data20 / 3232 / 3232 / 3220 / 320x0(0x100000)0x400 0000(0x100000)AddrBits / DataBitsi_ResetHardware PlatformSystem Specification(Application UT Description)appHW1Software BlockHardware Blockport_inSlaveMemory Location(Size)Tube1 / 80x8000 0000(0x2)port_outMasterport_inMasterport_outMasterport_inSlaveport_outSlaveappSW1Top
You are provided libraries, scripts and files for building the systemWorking directorySoftware/ARM_IPE_sw_driver.hboot.sARM_IPE_sw_driver.cppMakefileThe executable software imagetrainClass/peripherals/library/topdown/BuildAuxLib.tclAuxiliaryLib.xmlScripts for building the componentsSoftware source to run on the platformTop/Scripts/Auxiliary/include/src/BuildPeriphLib.tclPeripheralsLib.xmlinclude/src/BuildPlatform.tclBuildApplication.tclIPE/Boot/Platform/Auxiliary and Peripheral block libraries -clock, memory, displayBuildTopDownSystem.tclbuild/Application/simMakefile
Two alternative approaches will be shown to build and simulate the system
To build the system, you will perform these steps in Free-hand ApproachPlatform Creator:
1. Open the Platform2. Open or Import the System Specification3. Open the Scenario Library4. Partition blocks to software on the core5. Resolve abstract channels6. Create the Memory Map7. Check the design8. Export the design9. Save a project fileSystem Software:
10. Make the System Software
11. Build and run simulation
1. Open the platform project file.a. Select File->Openb. Navigate to topdown/Platform directoryc. Select the platform_ARM926.xml project filed. The platform blocks appear in the library drawer
2. Open and merge the system specificationa. Select File->Openb. Navigate to topdown/Application directoryd. Set checkbox to merge with current systemc. Select the application.xml project filee. The system blocks appear in the library drawer
For convenience, flatten the system specification by moving the blocks to the hardware top levelh. Position the system specification blocksappSW1appHW1top1 Delete if you wishf. Select the blockstop1platform
3. Open the Scenario Library in preparation for interface synthesisa. Select Library->Openb. Navigate to scenario library locationc. Select the AMBA HWSW libraryd. The scenario blocks become available in the library window
4. Partition the specification by assigning the appSW1 block to the software portion of the system When finished, the System Diagram will look like thisappSW1appHW1
As a result of the partitioning, the connections are broken and must be resolvedThe unresolved ports must be connected to the software block on the processor coreThe appSW1 block now appears under the SOFTWARE hierarchyInterface Synthesis produces a HW part and a SW part.
The HW part is bus specific. The block is a bridge between a specific bus node and a CoWare handshake protocol on the SW application side.
The SW part is core specific. The block contains the SW drivers.Two basic types of HW/SW Interface Synthesis to resolve the abstract channels: Memory mapped (MM) SW is the master Interrupt driven (ITR) HW is the masterappHW1
5. Platform Creator will resolve the abstract channels by using scenarios available from the scenario librarya. Select the port_inSlave port on the appHW1 blockb. Pop up the menu with the right mouse button and select the Enable Handshake scenarioappHW1
The result of the interface synthesis is the instantiation of a hardware interface block and the software device driverThe hardware interface block is instantiated and connected to the hardware port.The software device driver is instantiated and connected to the software port.appHW1
Interface synthesis for the master ports produces hardware and software blocks to implement an Interrupt-driven scenarioThe hardware interface blocks are instantiated and connected to the port_outMaster and port_inMaster ports.The software device drivers are instantiated and connected to the software ports.appHW1c. Select the Full Handshake Scenario for the port_outMaster and port_inMaster ports
Add an interrupt priority encoder from the scenario libraryd. From the scenario library, add an Interrupt Priority Encoder(IPE) block with two inputs.Note: In the diagram, we have repositioned the ports of the added block.appHW1
Connect the HW interface blocksg. Connect the HW interface blocks to their corresponding locations.AHB port, clk port, and reset port, respectivelyAHB clk resetnIRQ connection is externalized from the hierarchy of the core h. Check connections by selecting Check->Check Connections.appHW1
Configure template arguments on the hardware driver blockse. Select the appHW1_port_outMaster_driver block in the editing window and set the delay Template Argument to 100000Parameter Editorf. Set the delay for the appHW1_port_inMaster_driver block to 0appHW1
6. There are two ways to complete the Memory Map1. Create the memory map with Platform Creator Select the Memory Map Table tab in the Details Window2. Read in an existing memory map file Select Tools->Import Architecture File0x00x400 00000x4000 0400RAMROMByte addressableByte addressableAHB MapThis is the memory map for our example:The platform comes with a memory map specifying these addresses0x4000 00000x4000 08000x4000 0c00appHW1/port_inSlaveinMaster_driver/ p_AHBoutMaster_driver/ p_AHBhw_driver_2itr / p_AHB0x8000 0000i_Tube/pYou must add these targets and addresses to the memory map
Click on Memory Map Table to view the platform memory mapa. Click on Memory Map TableInitiatorsTargetsCellsInitiatorsTargetsappHW1This target is reachable by this initiator at the specified address
Add the application targets to the memory map tablec. Select Add to Memory Map Table. The target appears in the next row of the memory map table.b. Select target port. Click right mouse button to pop up the menu.appHW1
Enter addresses in the memory map table cellse. Double click on a cell. Enter the address and press the Enter key.d. Make these cells unreachable by the initiators. - Select the cell. - Click right mouse button to pop up the menu and select Remove LinkNote: To remove an unwanted address from a cell, select Remove Link and Set Unreachable from the pop up menu.appHW1
The exported memory map looks like thisdevice HARDWARE.appHW1.port_inSlave ram rw 0x1 litend 32;device HARDWARE.appHW1_port_inMasterMY_HW_SUFFIX.p_AHB ram rw 0x4 litend 32;device HARDWARE.appHW1_port_outMasterMY_HW_SUFFIX.p_AHB ram rw 0x4 litend 32;device HARDWARE.i_AHB_IPE_hw_priority_hw_driver_2itr.p_AHB ram rw 0x4 litend 32;device HARDWARE.i_Core.i_DTCM.DATA ram rw 0x4000 litend 32;device HARDWARE.i_Core.i_ITCM.DATA ram rw 0x4000 litend 32;device HARDWARE.i_RAM.p_AHB ram rw 0x100000 litend 32;device HARDWARE.i_ROM.p_AHB ram rw 0x100000 litend 32;device HARDWARE.i_Tube.p ram rw 0x2 litend 32;core HARDWARE.i_Core.i_ARM926IAHB HARDWARE.i_ROM.p_AHB 0x0 HARDWARE.i_RAM.p_AHB 0x4000000 HARDWARE.i_Tube.p 0x80000000 HARDWARE.appHW1.port_inSlave 0x40000000 HARDWARE.appHW1_port_outMasterMY_HW_SUFFIX.p_AHB 0x40000800 HARDWARE.appHW1_port_inMasterMY_HW_SUFFIX.p_AHB 0x40000400 HARDWARE.i_AHB_IPE_hw_priority_hw_driver_2itr.p_AHB 0x40000c00,DAHB HARDWARE.i_ROM.p_AHB 0x0 HARDWARE.i_RAM.p_AHB 0x4000000 HARDWARE.i_Tube.p 0x80000000 HARDWARE.appHW1.port_inSlave 0x40000000 HARDWARE.appHW1_port_outMasterMY_HW_SUFFIX.p_AHB 0x40000800 HARDWARE.appHW1_port_inMasterMY_HW_SUFFIX.p_AHB 0x40000400 HARDWARE.i_AHB_IPE_hw_priority_hw_driver_2itr.p_AHB 0x40000c00,ITCM_DATA HARDWARE.i_Core.i_ITCM.DATA 0x0,DTCM_DATA HARDWARE.i_Core.i_DTCM.DATA 0x0;mem_mapInitiatorsTargetsinstanceNametypeaccess size endianess portWidthCore Instance Name
7. Check the SystemThe occurrence of warnings or errors will cause a message window to open. You may or may not need to correct warnings, but you must correct errors.
8. Export the SystemSpecify a directory to output the files.
9. Save your work as a Project Filemem_mapSave: creates a System Project File (.xml) Export: writes out several files (SystemC source files, memory map and scripts) that will be used to build a simulation.system.xmlProject filesim.tclCwrModule_HARDWARE_i_AHB.cppHARDWARE.cppThe bus model exported by the bus library handlerThe top level block and sc_main functionThe memory architecture fileScripts for building the simulationSOFTWARE_ARM926EJS_AHB_Model.cppSystem specification software blocks and drivers
10. Make the System SoftwareSoftware/ARM_IPE_sw_driver.hMakefileLink to ...topdownSOFTWARE_ARM926EJS_AHB_Model/Makefile.includeSOFTWARE_ARM926EJS_AHB_Model.cppTop/Platform/. . .CwrModule_HARDWARE_i_AHB.cppHARDWARE.cppsim.tcl. . .. . .build/Makefile.includeSOFTWARE_ARM9Software exported by Platform Creatorb. Create links to exported softwarea. Check that boot.s has been compiled. If not, makeExisting ARM boot and initialization code.Boot/IPE/boot.sARM_IPE_sw_driver.cppHardware exported by Platform CreatorMakefilec. %makeThe executable software imagesim
The final step is to build and run the simulation. The key files are:.h & .cpp:design source filessim.tcl:simulation build scriptsim.fof:list of all .cpp filesmem_map:memory architecture file.scshrc:optional TCL fileSV/SDdbPostprocdesign filesmem_mapsim.tclsim.fofexportedFiles.cppexportedFiles.h.scshrcList of .cpp filesmemory architecture
11. Build and Run the SimulationIn UNIX:%cd ../../Top%scshIn SV:scsh>source sim.tcl (~ 2 minutes)scsh>set_maf mem_mapscsh>run
i_ARM926:load ../Software/build/simi_ARM926:go prints out data
In SV:scsh>quitThis simulation will print-out:
Top-Down Application (SW)=========================
enabling interrupts ...
Sending: 0x11111111 Receiving: 0x44444444 Replying: 0x11111110 This output was sent by the appSW block to the Tube block. The Tube block writes the data to the output stream and to file i_Tube.log. Compare to the data received and sent by the hardware block recorded in file appHW.log.
Before starting your lab work, here are some general comments and tips.By default, Platform Creator displays the HARDWARE portion of the system in the editing window.Going Up the hierarchy displays the three components that make up the total system.
The suffix for default HW and SW instance names can be specified in Preferences.Default valueClick to edit
Lab Exercise 15 Building a Top-down System
Guided Approach: To build the system, you will perform these stepsTop Down Flow Wizard:
1. Open Top Down Flow wizard2. Open the Platform3. Open the System Specification4. Partition blocks to software on the core5. Connect open clock/reset ports6. Open the Scenario Library7. Resolve abstract channels8. Connect scenario clock/reset ports9. Connect scenario memory ports 10. Set scenario memory ports addresses11. Connect scenario interrupt ports12. Select block encapsulation13. Export the design14. Exit Top Down Flow wizard
15. Make the System Software
1. Open Top Down Flow Wizard.Select Plugins > Wizards > Top Down Flow
2. Open the Platform.a. Push Browsec. Select the platform_ARM926.xml project file
3. Open and merge the system specification.a. Push Browse
4. Partition the specification by assigning the appSW1 block to the platform core.a. Click and select the core
5. Connect open clock/reset ports.a. Click and select the clock/reset master
6. Open the Scenario Library.a. Push Browse
7. Select the Scenario.a. Click and select the Enable Handshake scenariob. Select the Full Handshake Scenario for the port_outMaster and port_inMaster ports
8. Connect Scenario Clock and Reset ports.c. Select the i_Clock/clk master port for all scenario clock portsd. Select the i_Reset/rst master port for all scenario reset ports
9. Connect Scenario Memory ports to buses.e. Select the i_AHB bus for all scenario memory ports
10. Set Scenario Memory ports Addresses.f. Set address 0x40000000 for appHW1/port_inSlave 0x40000400 for appHW1/port_outMaster 0x40000800 for appHW1/por_inMaster
11. Connect Scenario Interrupt ports.g. Select i_Core/i_ARM926/nFIQ for appHW1/port_outMasteri_Core/i_ARM926/nFIQ for appHW1/port_inMaster
12. Select block encapsulations for simulation.a. Click to get a list of available encapsulations.Keep default encapsulations.
13. Select export directory.
14. Exit Top Down Flow wizard.
Necessary platform modification before starting Top Down Flow wizard
Automated Software buildIn UNIX:% cd ../Top/SOFTWARE_ARM926EJS_AHB_Model% make
Platform modification for Automated SW flow
15. Make the System SoftwareMakefiletopdownSOFTWARE_ARM926EJS_AHB_Model/Makefile.includeSOFTWARE_ARM926EJS_AHB_Model.cppTop/CwrModule_HARDWARE_i_AHB.cppHARDWARE.cppsim.tcl. . .. . .Software exported by Platform Creatorboot.sHardware exported by Platform Creator%makeThe executable software imagesimStartup code generated by Platform CreatorMakefile generated by Platform Creator
16. Build and Run the Simulation
Lab Exercise 16 Building a Design with the Top-down Flow Wizard
Welcome to Top Down Design. In this module you will be presented a description of the system to be built. This is followed by descriptions of two approaches. The freehand approach uses Platform Creator to build the system. The software is built manually and System Verifier is used to run the simulation. In the guided approach you use the Top Down Flow Wizard to construct the system. The output will include Makefiles to build the software. You will invoke the simulation from the Platform Creator console window. The lab exercises provide step-by-step instructions.To illustrate the steps in top down design, we will build this small system. We begin on the right with the system specification written at the untimed abstraction level. The system specification defines an application to shift integer data. We want to partition this system right down the middle so that one of the blocks will run as software on a processor while the other block will be implemented as hardware. On the left is the block diagram of a hardware platform containing a processor, memory and output blocks on which we can run the software portion of the application. The challenge is to implement the communication between the hardware and software components of the system specification.You are provided libraries, scripts and directories for building the system. The working directory will be top.To build the system, there are two different approaches that can be used. The first approach gives you the freedom to build the system in any order. During this process you still extend the platform as well as the application running on the core. The Makefile to create Software is written by the user, and the user has to perform a number of manual steps before building the software. The simulation is built and started with System Verifier outside the Platform Creator environment. The other approach helps you to go easily throughout the complete flow. The Top Down flow wizard makes sure that all necessary steps are executed. The order of steps is fixed and a possibility to extend the platform or the application is limited. The manual steps in creating Software are automated, the Makefile and all other necessary files are generated. The simulation can be built and started within Platform creator. You do not have to exit Platform creator and start other tools. Of course, both approaches can be mixed, so that you can find the way that best fits your requirements.Lets start with the Free-hand approach. It will help you better understand the complete top down flow.To build the system, you will use Platform Creator to perform the first nine steps. You will make the system software in the UNIX environment and then use System Verifier to build and run the simulation.The first step is to start Platform Creator and open the platform project file located in the Platform directory. The platform design appears in the editor and the blocks appear in the library drawer.The system specification is provided as a project file in the Application directory. The second step is then to open and merge the system specification with the platform. The system specification blocks appear in the library drawer.The system specification has one level of hierarchy. For convenience, flatten the system specification by moving the blocks to the hardware top level. You can delete the top1 block if you wish as it is now empty.The next step is to open the scenario library in preparation for interface synthesis. The scenario library contains components for creating connections. There are drivers for hardware and software blocks as well as software and hardware to implement both memory mapped and interrupt driven communication.You partition the specification by assigning the appSW1 block to the software portion of the system. This is done by dragging and dropping the blocks in the hierarchy tree window. This results in breaking the connections between the software and hardware components of the specification.The result is that now the appSW1 block appears under the SOFTWARE hierarchy and the appHW1 block ports now have small red rectangles indicating no connection. To resolve the communication the interface synthesis capability of Platform Creator will help you implement a memory-mapped scenario for the hardware slave ports and an interrupt-driven scenario for the hardware master ports.Platform creator uses the scenario library to present the possible protocols it can implement for the selected port.The result of our selection is the instantiation of a hardware interface block and the software device driver to implement a memory-mapped scenario. All we need to complete the communication for the port is to connect the interface block to a bus and define the memory map for the port.In similar fashion we select the master ports and choose a protocol from those available. Again the result is hardware interface blocks and software device drivers. However, this time the hardware interface blocks are designed to implement an interrupt-driven communication scenario. The hardware interface blocks contain a slave port for connection to a bus and a master port to drive an interrupt.Because there are two master ports that need to interrupt the processor, we add a two-input interrupt priority encoder from the scenario library.We now complete all the connections for the added hardware blocks. We have hidden the clock and reset lines so the diagram is not so cluttered. In this example, the processor has another level of hierarchy and only the address, data, clock, and reset ports were brought out at this top level. In order to connect to the interrupt pin of the processor the nIRQ connection was externalized from the lower hierarchy.All that is left to complete the communication between the hardware and software components is to configure the newly instantiated blocks and set the memory map. You use the parameter editor to examine the blocks and set appropriate values.The next step is to complete the memory map. You have two ways to do this. First, use the Platform Creator menu commands. Second, create a text version and read in the file. In our example, the platform comes with a memory map specifying the addresses of the platform components. So you will use the Platform Creator menu commands to add the targets and addresses for the newly added hardware components.The memory map table tab displays the memory map of the platform. The memory map consists of an array of cells with initiators representing the columns and the targets representing the rows. The address in a particular cell represents the memory address where a specific initiator can reach the specified target.There are four additional target addresses for the added hardware of the system specification that must be added to the memory map. The targets are specified by selecting the appropriate port, right clicking, and selecting Add to memory map table from the popup menu.Not all the cells in a row represent addresses that can be reached by the initiators. First, mark those cells as unreachable by the initiator. Second, double click in the appropriate cells to enter the memory address.The memory map file exported by Platform Creator contains a description of the initiators, targets and their associated target addresses. This file will be used in the running of the simulation.Before the design can be exported it should be checked for errors. Error checks include memory map errors (e.g.: an unallocated device) or other type of checks (e.g.: open port). All checks are invoked automatically upon design export, but can also be called manually. The occurrence of warnings or errors will cause a message window to pop up.The next step is to export the system. This creates several files that are shown on the next slide. We will export the design to the working directory.Dont confuse saving with exporting. Saving a project file results in an XML file containing all the information in your SYSTEM_LIBRARY workspace. This file can be opened to continue your work at a later time. Exporting writes out the SystemC source files, memory map and scripts that are used to build a simulation of the system. For our example, Platform Creator exports the source code for the bus model, the top-level block, the memory architecture file, the software drivers and scripts for building the simulation.
Here is the directory structure where the software components reside. On the right is the Top directory containing the hardware exported by Platform Creator and the software exported by Platform Creator. On the left is the ARM specific software for boot and initialization of the processor. In the build directory is a makefile for creating an executable image that combines the ARM boot and initialization code with the software exported from Platform Creator. First, verify that the boot code has been compiled. Second, create links from the build directory to the software exported by Platform Creator. Third, make the software image.The final step is to build and run the simulation. The key files are the .h and .cpp source files, the simulation build script, sim.tcl, a file-of-files, sim.fof, the memory architecture file, mem_map, and the System Verifier initialization file, .scshrc. These are all the inputs used by System Verifier to build the simulation executable. The running of the simulation will produce a database that can be examined for analysis.
The commands used to build and run the simulation begin with starting System Verifier followed by sourcing the sim.tcl build script. After the simulation is built, the memory map file is defined and the simulation is started. The ARM command line debugger will open a window in which we load the application software and start its execution. The simulation proceeds and completes.Before starting your lab work, we want to make some comments about the system you are editing. The total system can contain hardware, software, and subsystem components. By default, Platform Creator displays the HARDWARE portion of the system in the editing window. Going up the hierarchy will display the topmost three components of the system.One way of customizing the Platform Creator user interface is through setting preferences. One of those preferences is the setting of the suffix for the HW and SW instance names. Click in the value column to set to your choice.Now that you have an overview of the steps, it is your turn to go through the process of building the example top-down system. Many of the details of the steps were omitted in the overview presentation but are described in the step-by-step instructions.The guided approach uses the Platform Creator Top Down flow wizard to perform the first steps. You will make the system software in the UNIX environment and then use System Verifier to build and run the simulation.The first step is to start Platform Creator and to start Top Down Flow wizard from the menu.The first step in the wizard is to load the existing platform project file located in the Platform directory. The platform design appears in the editor and the blocks appear in the library drawer. The wizard is modal which means that other Platform Creator windows are inactive and you cannot view or modify the platform if the wizard is active. Since the platform cannot be modified, the platform must contain ports to which added scenario hardware block ports will be connected. This is the case for connecting interrupt sources to either core interrupt ports or to IPE ports. The platform must contain as many interrupt ports (core ports or IPE ports) as needed for connecting all interrupt sources. These ports must be open and not stubbed. In case the platform does not contain enough free interrupt ports after the platform is loaded, you have to exit the wizard, modify the platform to add additional IPE, and restart the wizard. After you restart the wizard, you skip the platform loading step.The system specification is provided as a project file in the Application directory. The second step is then to open and merge the system specification with the platform. The system specification blocks appear in the library drawer.
You can partition the specification by assigning the appSW1 block to the core. This is done by selecting a core from the list of all available platform cores. This results in breaking the connections between the software and hardware components of the specification. To keep a block in hardware, keep or select the dash in the Partition column.After you have decided which blocks will stay in hardware, you may create connections to clock and reset masters. The wizard shows the list of all unconnected clock and reset ports. You can select the clock or reset master from the list of all clock and reset masters instantiated on the platform.The next step is to open the scenario library in preparation for interface synthesis. The scenario library contains components for creating connections. There are drivers for hardware and software blocks as well as software and hardware to implement both memory mapped and interrupt driven communication.The wizard shows you a list of all abstract connections. The abstract connection is represented by the hardware port of the connection. Platform creator uses the scenario library to present the possible protocols (scenarios) it can implement for the selected port.You may connect scenario clock and reset ports to platform clock and reset masters. The wizard provides you a list of all platform clock and reset masters from which you can select.You may connect scenario memory ports to platform buses. The wizard provides you a list of all platform busses from which you can select.You may specify address locations of scenario memory ports in the memory map. The address is relative to the bus to which the scenario port is connected.For inserted interrupt scenarios you may create connections to core or IPE interrupt ports. The wizard shows the list of all core and IPE interrupt ports. You can select the interrupt port to which you want to connect from the list of all control ports. For non interrupt scenarios keep or select the dash.
The next step is selecting block encapsulations for simulation. This can be done for any instance in the platform.If you made all settings and you do not need to modify the platform, you may export the system from the wizard. You must specify the export directory. If the Export Directory field is empty the system will not be exported.The last step is to exit the wizard. If you want to exit the wizard and save all settings you select the Finish button. In case you want to change some settings you can push the Back button. This will undo the last settings made in the previous window and puts you back to the previous window. Press the Cancel button to exit the wizard and undo all changes to the system made in the wizard.It may be the case that the initial platform does not contain enough interrupt ports to connect all interrupt sources coming from interrupt scenarios. If needed, modify the platform with the IPE interrupt sources before you start the Top Down flow wizard. The other possibility is to interrupt the Top Down flow wizard and instantiate the IPE and to restart the Top Down Flow wizard again. The steps performed in the wizard before connecting the interrupt ports are skipped when you resume the wizard.During the export, Platform creator calls generators to generate the startup code and the complete Makefile for creating an executable image that combines the ARM boot and initialization code with the software exported from Platform Creator. The generators are specified in the processor support package. You can influence the generation by setting SOFTWARE parameters. The minimum is to set code and data base addresses and stack position and sizes in RAM. The creation of the image is then reduced to invoking make in the exported software directory.In the case you want to make use of automated software build to create the startup code and the Makefile to compile and link the software image, you need to setup the parameters of the SOFTWARE subsystem corresponding to the platform core. These parameters are used to influence the Makefile and startup code generation.Make sure the Code Base and Data Base correspond to the location of ROM and RAM in the memory map. Core stacks must be located in RAM and must have defined size. You can specify other compilation and linking flags.In case the interrupts must be enabled, set IntEnableFlag to true otherwise set it to false. Detailed description of all parameters can be found in the PSP documentation.After exporting the system in the Top directory, the Top directory contains the hardware exported by Platform Creator and the software exported by Platform Creator. The ARM specific software for boot and initialization of the processor as well as the makefile are generated. The only manual step is to call make to create the software image.You can build and run the simulation in Platform Creator. Platform creator understands all SV commands. The SV commands must be prefixed by scsh::. To build the simulation, source the sim.tcl build script. After the simulation is built, the memory map file is defined and the simulation is started. The ARM command line debugger will open a window in which we load the application software and start its execution. The simulation proceeds and completes.Now that you have an overview of the steps, it is your turn to go through the process of building the example top-down system. Many of the details of the steps were omitted in the overview presentation but are described in the step-by-step instructions.
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