Top-down design of a switched-current video filter

J.B.Hughes

Abstract: A case study for the design of switched-current filters is presented. While the emphasis is on the step-by-step numerical design of a video filter, the design flow is applicable to any switched- current filter. The chosen design example is a low pass elliptic ladder filter with the following specification: passband 0.5dB equiripple, stop-band attenuation > 30dB, -3dB frequency of 8MH2, sampling frequency of 80MHz, signal-to-noise ratio of 60dB. All aspects of the design are covered from filter specification, through filter synthesis, circuit definition and finally transistor sizing for CMOS implementation.

1 Introduction

Over the past ten years, the switched-current (SI) sampled analogue circuit technique has become a viable alternative to switched-capacitors (SC) for all but the most demanding applications. Its strongest claim is in mixed signal systems where total integration in digital CMOS [I] is required for low cost, or where bandwidth is key.

SI filter architectures have, for the most part, been devel- oped from their SC counterparts and often have the same signal flow graphs. However, because of the different nature of their signals (current against voltage), the circuit structures are very different. Most importantly, the SI memory transistor naturally buffers its own gate oxide memory capacitance, whereas the SC circuit needs separate op amps to buffer its capacitors. Consequently, while the design flow of SI filters parallels that of SC filters as far as the generation of the signal flow graph, the electrical design flows are quite different. The SI technique produces transis- tor-only circuits and, by the same token, the electrical design flow must also be at transistor level right from the outset.

CAD systems have been made which integrate expert knowledge, software tools and simulators [2]. While these enable rapid and accurate design, they are not generally available, and it is the purpose of this paper to provide a practical alternative for designers who may have only a simple set of tools

The design flow presented is in two main phases. In the first phase, the filter architecture is derived. A passive LCR ladder prototype is used, network equations are derived and a signal flow graph established. This enables an appro- priate architecture based on the bilinear z-transform inte- grator structure to be identified. This design is then adjusted to optimise dynamic range.

In the second phase, the transistors in the filter's integra- tors are designed. A set of memory transistor parameters is derived which satisfies the filter signal-to-noise ratio. Then,

0 IEE, 2000 IEE Proceedings online no. 20000014 DOI: 10.1049/ipcds:20000014 Paper fmt received 13th May and in revised form 9th September 1999 The author is with Philips Research Laboratories, Redhill, Surrey, RH I 5HA, UK

the transistor sizes and bias conditions which produce these parameters are found.

2 Derivation of the filter architecture

In this Section, we derive the switched-current architecture from first principles. Starting with a suitable LCR proto- type filter, we develop network equations and derive signal flow graphs. These are then transformed to make them suitable for implementation with double-sampling bilinear z-transform integrators. Finally, the coefficients are adjusted to optimise dynamic range.

I I I 0- 0

.___ ..

31.19dB

-LLi;;\

I * I ' , a , .

1 2 R,rod/s b

Fig. 1 LCR prototype filter U Topology Rs = RL = 1 C ; = C; = 1.44483 C; = 0.20718 L > = 0.93666 b Normalised response

2. I Prototype filter The chosen filter specification for this case study is as fol- lows: passband 0.5dB equiripple, stop-band attenuation > 30dB, -3dB frequency of 8MHz, sampling frequency of XOMHz, signal-to-noise ratio of 60dB. From any suitable

73 IEE Proc.-Circuits Devices Syst., Vol. 147, No. 1. Fehruirry 2000

filter tables such as [3], we find that the required stopband attenuation of 30dB and passband ripple of 0.5dB can be achieved with a double-terminated thxd-order elliptic LCR ladder filter. The parameters of the prototype (1 rads, 1Q terminations) are as shown in Fig. 1. Note that the pass- band gain is 4 d B (due to the double-termination) whereas the switched-current filter will be designed for OdB pass- band gain.

2.2 Frequency scaling This prototype filter has a normalised cut-off frequency of 1 rads, a normalised stopband frequency of 2 rads and a stopband attenuation of 3 1.19dB below the passband gain of 4 d B .

The next step is to scale it to give a -3dB cut-off fre- quency of 8MHz. We intend to use bilinear z-transform integrators in the final filter and so we must pre-warp the response to compensate for the distortion introduced by the transform (s H 2(1 - z?)/TS(1 + z-I)). The pre-warped cut-off frequency cop found by substituting z = d"Ts, is given by [4]:

w p = - 2 tan ( wcoTs T) TS

where T, is the sampling interval and coco is the specified cut-off frequency. For our example, T, = 12.511s (SOMHz sampling) and mco = 16nMrads (8MHz). Substituting these values gives cop = 51.9872Mrads.

Now, because the prototype filter of the elliptic fdter is for a cut-off frequency defined at the -0.5dB level rather than the -3dB level, we must make a correction for ths. Simulation of the prototype filter (e.g. with Spice) shows that w4.5dB = 1 rads and w 3 d B is 1.1379 rads.

c2

0 1 I 0

Fig. 2 Scaled and pre-warped prototype filter with state variables

lor

Vout

-701 I

105 106 107 108 frequency, Hz

Fig. 3 Frequency responses ofprototype filter k state variables - x VcC!)

So, the final fdter should be derived from a prototype with a pre-warped 4 S d B cut-off frequency of mpco = 51.9872A.1379 = 45.687Mradh (7.2713MHz). This can be achieved by scaling the components of the 1 rads proto- type filter as follows:

C; 0.20718 = 4.5348 n F (3)

c2 wpco = 45.687106

C3 = C1 = 31.625 nF (4)

L - '!2 0'93666 = 20.502 nH (5) - wpco = 45.687106

The scaled and pre-warped prototype filter is shown in Fig. 2 and the responses of this prototype filter's state-vari- ables (vl, i2 and v,) are shown in Fig. 3.

2.3 Signal flow graphs We can write down the prototype filter's network equations with reference to Fig. 3.

(7)

These equations are represented by the signal flow graph in Fig. 4.

1 R c -1 -

V1 1 -1 v3 Vout Fig. 4 Signalfrow graph ofprototype fdter

Q21 ' 2 a23 v1nllT3 p13(+)

v1 a12 a32 V3 a34 Vout Fig. 5 ModijEd signalJlow gruph

Next, this signal flow graph is manipulated by setting Rs = R, = 1 and making the value of each of the branches ter- minating in a state variable (v,, i2, v3) equal to 2/sTs so that it can be used later to derive an integrator-based fdter structure. It is achieved by multipying the v1 branch by the factor 2(C1 + C2)ITS and all its input signals by the factor TJ2(C1 + C2), the i2 branch by the factor 2&/T, and all its input signals by the factor T42L2 and finally the v3 branch by the factor 2(C2 + C3)/T, and all its input signals by the factor TJ2(C2 + C,). The overall transfer function is unaf- fected by multiplying each branch output by a factor and its input by the inverse factor. The moddied signal flow graph is shown in Fig. 5, and the coefficients are given by:

c - '' = 31.625 nF ( 2 ) - wpco = 45.687106

m

14 IEE Proc-Circuits Devices Syst., Vol. 147, No. I . February 2000

a34 = 1.000 (12)

= 0.1254 (14) Ca

(Cl + C2) P31 =

The signal flow graph manipulation given above differs from that usually adopted for switched-capacitors. This is because arrangements of Euler integrators are more com- monly used and because the method for dealing with the floating capacitor C, is different. The reader is referred to [4] for more detail.

2.4 Filter architecture W e the design is not yet complete (we have not yet opti- mised the dynamic range), it is useful to see the SI architec- ture corresponding to this signal flow graph. The integrator/summer [5] whch performs bilinear mapping (s I+ 2(1 - z-')/Ts(l + z-I)) and implemented with basic S21 memory cells is shown in Fig. 6. These memory cells are actually composite memories in which the so-called 'coarse' nmos transistor stores the signal with errors and the 'fine' pmos transistor stores the errors, and the output achleves a large degree of error cancellation. The cell also creates a 'virtual earth' at its inputs and this controls signal impair- ments whch might otherwise arise from output conduct- ance gd and drain-gate overlap capacitance Cdg without having to resort to cascoding techniques. The reader is referred to [6] for more detail. The integrator/su"er uses balanced signals and has two types of input and two types of output. The I inputs and A outputs provide an integra- tion path while the S input and B output provide a feedfor- ward path (i.e. with gain but no integration). In filter systems, I inputs are only driven from A outputs and S

"dd a P 1

inputs are only driven from B outputs. The input changeo- ver switches ensure that only differential signals are inte- grated, giving the integrator inherent common-mode rejection without the need for specific common-mode feed- back. The integrator coefficients 01 and B are defined by the current mirror ratios between the transistors in the integra- tor core and those at the outputs. The transistors in the integrator cores may be segmented so that the precision of the complete coefficient set for the whole filter is optimised. The cell operates with double-sampling as it samples on both phases q5, and & and this brings considerable per- formance advantages.

a

S /IT\?) B

b Fig. 7 I n t e g r u t o r / m r signalflow gruphs

The z-plane signal flow graph for the integrator/summer is shown in Fig. 7a. By applying inverse bilinear mapping, the s-plane signal flow graph of Fig. 7b is derived. Now, by observing the fdter signal flow graph of Fig. 5, specific

1 P a

P 1 1 P a

Fig. 6 Bilinear z - t r m f o m i n t e g r u t o r / m r

IEE Proc.-Circuits Devices Syst., Vol. 147, No. I , Februury 2000 75

instances of the integrator/summer cell can be identified and the filter architecture of Fig. 8 is readily formed.

a12 “32 a3L Fig. 8 PreliminuryjZter architecture

2.5 Dynamic range optimisation Next, we consider the signal levels in the filter (Fig. 8). Because we have used bilinear mapping, the signal ampli- tudes in each of the integrators will be the same as those of the prototype fiter’s state-variables (Fig. 3). This shows that, at low frequencies, each integrator has the same signal level. The peak level in the core of the third integrator (state-Variable v3), like that at the final filter output, is the same as its low frequency value. However, the peak level in the core of the first integrator (state-variable v l ) reaches a peak level of +2.866dB (i.e. it has a peak gain GI of 1.3909 times its low frequency gain) and that of the second inte- grator (state-variable i2) reaches +6.271dB (i.e. it has a peak gain G2 of 2.0585 times its low frequency gain). The maximum signal which may be transmitted through the filter is determined by the second integrator which will be the first to limit. This situation results in sub-optimal sig- nal-to-noise ratio and can be improved by optimisation.

Dynamic range optimisation involves adjusting the inte- grator coeficients so that all integrator cores peak at the same signal level. This is achieved in our filter by lowering the signal response in the core of the first integrator by 2.866dB and in the second integrator by 6.271dB while leaving that of the third integrator unchanged. This, and setting the passband gain to OdB, is achieved by scaling the integrator coeflicients as follows:

/ 01

G3 = 1 (27)

Note that the coefficient values define the relative aspect ratios W/L of the transistors in the output and core of each of the integrator’s half circuits and negative coefficients are effected merely by crossing-over the signal pairs. In the case of the input coeflicient ql this sets the relative aspect ratio of the transistors in the sample-and-hold circuit used to drive the filter.

The final architecture defined above is modelled in Figs. 9-1 1. Note that this is an idealised model in which the memory cell is represented by an ideal transconductor of value 1 S with capacitance at its input and an ideal switch, and the integrator output mirrors are ideal transconductors with value aij. For ideal modelling it is not necessary to model the whole S2Z cell. This network was simulated using a switching network analyser slrmlar to Scnap4 [7] and the result is shown in Fig. 12. The low frequency responses of integrators 1 and 2 have been reduced below that of integrator 3 and the peak signal responses of all integrators is the same, as required for an optimised dynamic range.

lspll

p’,3 a;2 a;1 a‘ll a’12 a;,

p i 3 a;2 4 1 I I Fig. 9 Ideal model of$lter architecture: integrator 1

IEE ProcCircuits Devices Syst., Vol. 147, No. 1 . February 2000 16

15p21 . 91

a’21 a‘23 I I

a;3 ‘T;1 1 I Fig. 10 Ideul model of filter circhiiectirre: integrator 2

I

‘1.54 G l ‘1.32 a33 Fig. 1 1 Ideal model ofjilter urchitecture: integrutor 3

-16 -11 - 7

104 106 1 o7 108 frequency, Hz

Fig. 12 Frequency response ujkr dynumic rurge opthimtion

m

w -2% D

-32 a

E, I -Lot

-16 - m

w -2%- D

U 3 ._

-32 - a

E, - L O -

-18 -

-56 -

104 106 1 o7 108 frequency, Hz

Fig. 12 Frequency response ujkr dynumic rurge opthimtion

3 Transistor level design

The final fdter architecture described above resulted in each of its integrators having the same peak signal amplitude. This feature allows integrators to be designed with an iden-

tical core (i.e. the same transistors and bias conditions) with only the output transistors differing according to the required sets of coefficients. This is extremely convenient as it allows the design to focus on the memory cell of just one the integrators. This will be the most heavily loaded inte- grator (i.e. the one with the greatest sum of coefficients), which, in this design, is the third integrator. The other two integrators can be given dummy gate capacitors suficient to make good their shortfall in total capacitance to produce a set of integrators which perform almost identically in all respects. The task in this phase of the design is to size the transistors in the integrators’ memories and switches, and their operating bias, to produce the specified filter perform- ance (signal-to-noise ratio and dynamic behaviour). This is a complex task which is best undertaken with a special pur- pose CAD package [2] with means for designing with accu- rate transistor models and extracted IC interconnect capacitances. So, the following ‘manual design’ is necessar- ily approximate and serves mainly to illustrate a possible design process.

3. I Signal-to-noise ratio decomposition The first step is to reduce the design problem from that of the whole filter to just that for the memory cell. To do this we must find the signal-to-noise ratio of the memory cell (SNR,, in dB) which produces the specified signal-to-noise ratio of the filter (SNR1, in dB). Put another way, we need to find what we might call the signal-to-noise margin

IEE Proc-Circuits Devices Syst., Vol. 147, No. 1. February 2000 77

(SNM, in dB) where:

S N M = S N R , - S N R f (28) I memory output

’I gm = a’

assume square law saturated transistor behaviour. It

g,, = g,) so that both transistors contribute equal noise. The gate overdrive voltages are then equal to Vgt given by:

(35) 2 J Sm

vgt = -

and the memory cell signal-to-noise ratio may be alterna- tively expressed [I] as:

Suppose the noise power produced at the fdter output is (A2) and the peak output signal i (A), then the filter signal- to-noise ratio is given by:

S N R f = 10 log ($) For our design (with a’34 = 0.5) the peak current in the memories of the third integrator’s core is also i. We can expect thermally generated ‘white’ noise to dominate and so the noise power produced by the memory is S d W , where S, is the noise power spectral density (A2&) and B W, is the memory cell’s noise bandwidth. So, the memo- ries have a signal-to-noise ratio given by:

and the signal-to-noise margin, SNM, is given by:

S N M = lolog (L) SmBWn

The memory cell’s noise bandwidth is given by:

(32) Qm sw, = -

4Ctd where g, is the memory transistor transconductance and C,, is the total capacitance associated with the memory cell. The ratio Cjo,/gm = z, is the memory time constant and determines the memory’s settling behaviour. We may allow six time constants in the sampling period (Ts) to give settling accuracy better than 0.1% which is sufficient for most video applications. So, the time constant and noise bandwidth may be expressed as:

(33)

(34) 1 3

47, 2Ts BW - -= - n -

The signal-to-noise margin, SNM, is a characteristic parameter of the filter being designed and embraces both archtectural detail and the memory cell’s bandwidth. This makes it virtually impossible to derive analytically and so we simply make use of a switchmg circuit simulator which can analyse noise such as Scnap4 [8]. For this simulation, the same ideal network used for the frequency response simulation may be used again (Figs. 9-1 1). The noise band- width of the memory cells is set by choosing memory gate capacitance as Ti6 which for 8OMHi samphg gives 2.083nF and a noise bandwidth of 3f2Ts = 120MHz. Noise current sources of S, = 1A2/Hz are connected to the out- put of each memory cell and a; (A2/HZ) to each of the integrator’s output mirror transistors, as indicated in Fig. 13. Simulation of this network produces the output noise power spectrum, and integration of this over a-suita- ble frequency band (say 20MHz) yields the value of i2 for S, = 1A2/HZ and BW, = 120MHz and hence SNM. For our fdter, the noise simulation gave a value of is 400MA2 and SNM = 5.23dB. So, to produce a filter signal-to-noise ratio of 60dB, the memory cell should be designed with a signal-to-noise ratio SNR, of 65.23dB.

78

where mi is the modulation index (i1.Q mth is a process con- stant relating a transistor’s actual to theoretical noise power, k is Boltzmann’s constant and TJ is the chp tem- perature. For m a x i “ signal-to-noise ratio, Vgt should be made as large as possible without causing loss of saturated operation of the memory transistors. Saturated operation is guaranteed so long as [l]:

For Vh = -Vtp = 0.8V, and mi = 0.75 (which gives reason- able linearity for balanced operation), Vgj s 0.97V. Best common mode behaviour in the $1 memory is achieved when the sum of the pmos and nmos ‘diode’ voltages equals the supply rail:

v d d = &, - K p + 2 v g t (38) For V, = 3.3V, this gives Vgt = 0.85V which is within the limit for saturated operation and so we will take this as the design value. Using eqn. 36 with SNR, = 65.23dB, V,, = 0.85V, mth = 2.25, k = 1.38 x l@23, TJ = 300K we can find that Ctot = 815.2s. From eqn. 32, adequate settling behav- iour will result if the transconductances are given the value:

(39)

which gives g, = 391.3pS. From eqn. 35, the bias current is:

J = - V g t g m 2

whch gives J = 166.3pA.

IEE Proc-Circuits Devices Syst., Vol. 147, No. 1, February 2000

The power consumption for the three integrators is given by:

p = d V d d J ( 3 + IQi11 + I a i 2 1 + lalll + + IQLI + IQLI + IQLI + IPLI + IPLI)

(41) which for V, = 3.3V gives P = 1l.lmW.

3.3 Memory transistor sizing Having just established the memory transistor parameters km, C,, and s), the next task is to find the transistor sizes (W and L) whch produce those parameters. From the sat- urated transistor square law equations, the memory transis- tor aspect ratios are given by:

(43)

where pSy = yCor For psp = 1 3 0 w and psqp = 40w this gives wJ1, = 3.541 and wJ6 = 11.508.

Before we proceed with the design, we inspect the capac- itances which contribute to Cl,, as shown in Fig. 14.

'd d I I

i ' 1 I -

vss ' I I I I Fig. 14 Model of S21memovy cell in mtegrator showing Capactive badkg

The coarse and fine memory transistors have been designed so far with equal transconductance and we must design them with equal capacitance at the memory gates (C, = C = Cg) to ensure that C,, is substantially unchangefon both coarse and fine phases of operation. C, models the switch and interconnect strays, Cdg,is the sum of the coarse and fine memory diffusion capacitances and C,, is the sum of the diffusion capacitances of the memory in the other half of the integrator and that of the output transistors of the driving integrator. So:

where (for the third integrator):

and the total memory capacitance is:

The capacitance at the gate is given by:

c g = n g c g s (47) where Cgs is the gate-source capacitance of both the coarse and fine memories and ng (for the third integrator) is given by:

(48) n g = 1 + 1 4 2 1 + IQLI + b L 4 I + IP6iI

Now, if we define C, as the gate oxide capacitance per unit area (assumed equal for nmos and pmos), the areas of the coarse and fine memory transistors are given by:

c9 - C t o t - c s - (1 + n d ) C d i f f A = % = - - Cgu ngCgu n 9 G u

(49) and:

wn Ctot - cs - (1 + n d ) C d z f f

(50)

w p C t o t - cs - (1 f n d ) C d z f f

(51) If CA is the drain diffusion capacitance per unit width (again assumed equal for nmos and pmos), the diffusion capacitance is given by:

c d i f f = (wn + w p ) c d u (52) Substituting for w, and wp gives:

where C, is given by:

(56) Using the previously calculated values of C,, = 815.2fF,

w,,ll,, = 3.541, wJ$, = 11.508, and taking CA = lfF/pn and C'= 3fF/pn2, we can make a calculation of the memory transistors. To do this we first estimate that C, = 0.2CtOt (this is a guess and may need to be revised later). Eqns. 45 and 48 give nd = 2.308 and ng = 1.9465. Then using eqn. 54 we get C, = 4.76fF. Using eqn. 53, cdiff = 48.4fF. Then, from eqn. 49, the transistor area is A = 8 4 . 2 5 ~ ~ giving w, = 1 7 . 2 7 ~ , I,, = 4 . 8 8 ~ and wp = 31.14p-1, 6 = 2 . 7 1 ~ .

At this point, before proceeding with the remaining design, it is worthwhile using transistor level simulators such as Spice to trim the n- and p-memory transistor sizes to make a closer match to the required transistor parame- ters. One approach is to define a network comprising thep- and n-memory transistor connected between the supply rails with drains and gates connected to a common node (so that each transistor is effectively a 'diode'). DC analysis gives the operating point information including the bias current, transconductance and capacitance values. If the widths and lengths of each transistor are changed by small amounts, the bias current and transconductances can be tuned without disturbing the requirement that the gate- source voltages sum to the supply rail. If the sizes are changed while maintaining the gate areas (by making equal and opposite adjustments to the gate widths and lengths), the total capacitance will change very little. The actual parameters and capacitance values can then be used for the remainder of the design though, for the purposes of this text. we will continue with the calculated values.

IEE Proc.-Circuits Devices Syst., Vol. 147, No. I, February 2000 I 9

3.4 Switch transistor sizing The final stage in the memory design is to size the memory switches (i.e. the switch connecting to the memory transis- tor gate) and the input switches. The memory switch size must be chosen so that the closed loop formed when the switch closes gives the memory cell monotonic settling behaviour. The closed memory loop is shown in Fig. 15.

Q S aT1 C Q f -

Fig. 15 Closed loop of memory trmistor

This shows a second-order loop in which Cg is the total capacitance at the memory gate, Cd is the total capacitance at the memory drain, g, is the memory transconductance and g,, is the memory switch on-conductance. It can be shown that this loop has a Q-factor given by:

(57)

where Cd is the s u m of the stray and diffusion capacitances given by:

c d = c s + (1 + nd)Cdiff (58) For critical damping (Q = 0.5), the memory switch on-con- ductance is therefore:

(59)

Putting Cl, = O.2CI,, = 163fF, nd = 2.308 and cdifr = 48.4fF gives Cd = 323.2fF and Cg = C,, - Cd = 492fF. With g, = 391.3@, the memory switch conductance for critical damp- ing is gSm = 374.5@. If we take the unit switch on-conduct- ance, g,, = lOOpSS/pm where:

(60) W s m

Ssm = Ssu- 1S,

The dimensions w,~, and 1, are the memory switch's chan- nel width and length. The memory switch length should be as small as possible to minimise switch area and hence the charge injection. So, putting 1, = lmi, where lmi, is the min- imum transistor channel length, whch we will take as O S p m , gives w,, = 1 . 8 7 ~ and Ism = 0.5pm.

The size of the input switches (wsJlsi) is a compromise between the on-conductance and the capacitance it contrib- utes to Clot. A reasonable engineering compromise is that the voltage drop on the switch when the peak signal i flows should be around 10% of the memory Vg,. So, as the input switches may conduct up to nd - 1 units of the signal cur- rent (remember that the signal current from the integrator's other memory does not flow in the input switch), the input switch on-conductance is given by:

For our design, i =124.7pA, nd = 2.308 and Vgr = 0.85V and this gives gsi = 1919pS. Again, we make lSi = lmi, to minimise the switch's capacitance and using g, = loo@ this gives wsi = 9 . 6 0 ~ and lsi = 0 . 5 ~ .

80

This completes the design of the integrator memory cell for the assumed value of the interconnect and switch strays C, = 0.2CIo, (= 1631%). C, can be expressed as:

c s = Cznt + c s ,

where C,,, is the interconnect capacitance which can only be determined after layout and C,, is the capacitance of all the switches connected to the integrator core. In the simple 9 Z integrator (Fig. 6) this comprises the input switch pair and four memory switches. It is found by summing the dif- fusion capacitances from the switches' sources and drains and the channel capacitances. So, C,, (assuming no sharing of drain contacts) is given by:

cs, = (4wsz + 8wsm)Cdu. + (2wszlst + 4 w s m ~ s m ) c g u

This gives C,, = 93 .4s and leaves C,, = 69.6fF. If, after layout, it is found that the actual value of C,,, is different then the design may be repeated with updated values of C, until a converged design results or, if less than the assumed value at the start of the design, extra capacitance can be added to make good the shortfall.

All that now remains to complete the design is to calcu- late the integrator output transistors and the dummy tran- sistor capacitors to be connected to the gates of the memories of integrators 1 and 2 so as to make good the shortfall of C,, due to the lower sum of coefficients. The output transistors are given the same channel lengths as the memory transistors (1, or $,), and their widths are found by multipying the memory transistor widths (w, or wp) by the appropriate coefficient value. For greater coefficient accu- racy, the memory transistors may be divided into a number of equal width segments plus one different segment with all connected in parallel to make up the total required width. The segment width is chosen to optimise overall accuracy of the coefficient set.

The dummy capacitances that should be added to the gates of integrators 1 and 2 are:

C d u d = Ctot-(ngiC,,+C~+(l+ndl)CdzSf) (64)

(62)

(63)

where:

n91 = I&l + 2 (1411 + IP;,I)

n d 1 = 1 + 1Qk2 I + [P i s 1 (65)

(66) and:

Cdum2 = C t o t - ( n g 2 C i s + C s f ( 1 + 7 2 d 2 ) C d z f f ) (67) where:

7292 = 2 ( l 4 2 l + 1 4 2 1 ) (68)

n d 2 1 + lahl I f la131 (69) This gives ngl = 1.3317, ndl = 1.0933 and Cdm, = 214.2fF, and ng2 = 1.6116, na = 0.7092 and Cdm, = 162.05fF. These can be implemented by appropriately sized nmos or pmos gate oxide capacitors.

3.5 Summary of design flow A step-by-step procedure has been described in which the memory transistor parameters (transconductance, bias cur- rent, capacitances) are first derived from the memory's specification (signal-to-noise ratio and clock frequency) and the need to maintain saturated operation under extreme signal conditions. Next, these parameters are used to calcu- late the sizes of the memory transistors and associated switches. It was necessary to assume square-law saturated

IEE Proc -Circuifs Devices Sysr.. Vol. 147, No I , February 2000

MOS behaviour and this gives some inaccuracy, especially when the memory channel lengths are small (usually in high bandwidth designs). The accuracy can be improved by interrupting the calculation at this stage and using simula- tion with accurate MOS models to optimise the parameters of the calculated transistors. Continuing the design flow, the switch sizes are next calculated and th s completes the first pass of the design. As the calculation was based on estimated parasitic capacitance, this must be checked from the layout of the memory cell. If necessary, the extracted parasitics can be incorporated in a new design cycle or, as this is a tedious process, dummy capacitance can be added to make good any shortfall. The whole process can be given improved accuracy and reduced design time if special purpose CAD tools with integrated simulators are availa- ble. Such a CAD system was used to design a video filter with a specification very close to that used in our case study [2]. The reader is also referred to [2] for the measured performance of the integrated filter

4 References

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(Peter Peregrinus Ltd, 1993)

NETT, J., REDMAN-WHITE, W., BRACEY, M., and SOIN, R.S.: ‘Automated design of switched-current filters’, IEEE J. Solid-Stute Circuits, 1996, 31, (7), pp. 898-907

3 STEPHENSON, F.W.: ‘RC active filter design handbook‘ (John Wiley)

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