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Delft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science Department Microelectronics and Computer Engineering Circuits & Systems Group Digital Design Flow For EDA tools: Mentor Modelsim Synopsys Design Compiler Cadence SoC Encounter Tutorial - 2010 Version - 2.2 Ir. A.C. de Graaf Ing. H.J. Lincklaen Arriëns Dr.ir. T.G.R. van Leuken March, 2010
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Delft University of TechnologyFaculty of Electrical Engineering,Mathematics and Computer ScienceDepartment Microelectronics and Computer EngineeringCircuits & Systems Group

Digital Design FlowFor EDA tools:

Mentor ModelsimSynopsys Design CompilerCadence SoC Encounter

Tutorial - 2010

Version - 2.2

Ir. A.C. de GraafIng. H.J. Lincklaen ArriënsDr.ir. T.G.R. van LeukenMarch, 2010

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Table of Contents

1 Preface 4

2 Introduction 52.1 Top-down design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Design project organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 EDA tools and design kit configuration . . . . . . . . . . . . . . . . . . . . 102.4 Installation of the FARADAY design kit . . . . . . . . . . . . . . . . . . . . 102.5 VHDL example: Adder-subtractor . . . . . . . . . . . . . . . . . . . . . . . 122.6 Text editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.7 Design flow steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 VHDL and Verilog simulation 193.1 Starting the Modelsim graphical environment . . . . . . . . . . . . . . . . . 193.2 Simulation of (pre-synthesis) RTL VHDL models . . . . . . . . . . . . . . . 203.3 Simulation of the post-synthesis VHDL model with timing data . . . . . . . 233.4 Simulation of the post-route Verilog model with timing data . . . . . . . . . 24

4 Logic synthesis 284.1 Starting the Design Vision graphical environment . . . . . . . . . . . . . . . 284.2 RTL VHDL model analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.3 Design elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.4 Design environment definition . . . . . . . . . . . . . . . . . . . . . . . . . . 304.5 Design constraint definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 314.6 Design mapping and optimization . . . . . . . . . . . . . . . . . . . . . . . 334.7 Report generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.8 VHDL/Verilog gate-level netlist generation and post-synthesis timing data

(SDF) extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.9 Design constraints generation for placement and routing . . . . . . . . . . . 424.10 Design optimization with tighter constraints . . . . . . . . . . . . . . . . . . 444.11 Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Standard cell placement and routing 495.1 Starting the Encounter graphical environment . . . . . . . . . . . . . . . . . 495.2 Design import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515.3 Floorplan Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525.4 Power ring/stripe creation and routing . . . . . . . . . . . . . . . . . . . . . 545.5 Global net connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.6 Operating conditions definition . . . . . . . . . . . . . . . . . . . . . . . . . 575.7 Core cell placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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5.8 Post-placement timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . 625.9 Clock tree synthesis (optional) . . . . . . . . . . . . . . . . . . . . . . . . . 635.10 Design routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675.11 Post-routing timing optimization and analysis . . . . . . . . . . . . . . . . . 685.12 Filler cell placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705.13 Design checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705.14 Report generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.15 Post-route timing data extraction . . . . . . . . . . . . . . . . . . . . . . . . 755.16 Post-route netlist generation . . . . . . . . . . . . . . . . . . . . . . . . . . 765.17 GDS2 file generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.18 Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6 Appendix A: Design Metrics 85

3 Digital Design Flow Tutorial

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1 PrefaceThis document describes the top-down design flow of the implementation a SoC design.Starting from a example HDL description the designer is guided through all the design stepsto tapeout GDS2 layout description.This tutorial is derived from "Top-Down digital design flow" version 3.1 (November 2006)by Alain Vachoux, Microelectronic Systems Lab EPFL, Lausanne, Switzerland.

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2 IntroductionThis document details the typical steps of a top-down digital VHDL/Verilog design flowwith the help of one simple design example.The following tools are considered in this document:

• Modelsim v6.3a or higher, from Mentor Graphics.

• Design Compiler and Design Vision 2007.03 or higher from Synopsys.

• Encounter 7.1 and IC 5.1.41 or higher from Cadence Design Systems.

The design kit used is from Faraday. The process is the 90 nm 9-metal CMOS called L90_SP.Each of the next chapters in this document is addressing a specific set of tasks. Chapter3 is about VHDL and Verilog simulation, chapter 4 is about logic synthesis and chapter5 is about place and route. Steps in these chapters are not necessarily to be done in thegiven sequence. Go to “2.7 Design flow steps” to get a typical sequence of steps supportinga top-down approach.

2.1 Top-down design flow

Figure 1: Top-down design flow

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Figure 1 illustrates the top-down flow that includes the following steps:

VHDL RTL model creationThe goal here is to develop synthesizable VHDL models at the RTL level (RTL meansRegister-Transfer Level). Such models usually define a clear separation between controlparts (e.g. finite state machines-FSM) and operative parts (e.g. arithmetic and logicunits). Registers are used to store small size data between clock cycles. RAM/ROMmemories are used to store large amounts of data or program code. Blocks such asFSMs, ALUs, registers are usually described as behavioral models that do not implyany particular gate-level implementation. Tools used at this step can range fromsimple text editors to dedicated graphical environments that generate VHDL codeautomatically.

RTL simulationThe VHDL RTL models are validated through simulation by means of a number oftestbenches also written in VHDL.

RTL synthesisThe synthesis process infers a possible gate-level realization of the input RTL descrip-tion that meets user-defined constraints such as area, timings or power consumption.The design constraints are defined outside the VHDL models by means of tool-specificcommands. The targeted logic gates belong to a library that is provided by a foundryor an IP company as part of a so-called design kit. Typical gate libraries includea few hundreds of combinational and sequential logic gates. Each logic function isimplemented in several gates to accommodate several fan-out capabilities or drivestrengths. The gate library is described in a tool-specific format that defines, for eachgate, its function, its area, its timing and power characteristics and its environmentalconstraints.

The synthesis step generates several outputs: a gate-level VHDL netlist, a Verilog gate-level netlist, and a SDF description. The first netlist is typically used for post-synthesissimulation, while the second netlist is better suited as input to the place&route step.The SDF description includes delay information for simulation. Note that considereddelays are at this step correct for the gates but only estimated for the interconnections.

Post-synthesis gate-level simulationThe testbenches used for RTL model validation can be reused (with possibly somemodifications to use the VHL gate-level netlists). The gate-level simulation makesuse of VHDL models for the logic gates that are provided in the design kit. TheseVHDL models follow the VITAL modeling standard to ensure proper back-annotationof delays through the SDF files generated by the synthesis or the place&route step.

Standard cell place and routeThe place&route (P&R) step infers a geometric realization of the gate-level netlist so-called a layout. The standard cell design style puts logic cells in rows of equal heights.

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As a consequence, all logic gates in the library have the same height, but may havedifferent widths. Each cell has a power rail at its top and a ground rail at its bottom.

The interconnections between gates are today usually done over the cells since currentprocesses allow several metal layers (i.e. 9 metal layers for the Faraday L90_SP pro-cess). As a consequence, the rows may be abutted and flipped so power and groundrails are shared between successive rows.

The P&R step generates several outputs: a geometric description (layout) in GDS2format, a SDF description and a Verilog gate-level netlist. The SDF description nowincludes interconnect delay. The Verilog netlist may be different from the one readas input as the P&R step may make further timing optimizations during placement,clock tree generation and routing (e.g. buffer insertion).

Post-layout gate-level simulation

The Verilog gate-level netlist can be simulated by using the existing VHDL testbenchesand the more accurate SDF data extracted from the layout.

System-level integrationThe layout description is then integrated as a block in the designed system. This stepis not covered in this document.

2.2 Design project organisation

First we have to setup a proper work environment. The toolscripts need the CSH shell ascommand shell while the standard shell after login is the Bash shell. So first we take carethat the CSH shell is our default command shell by:

cp /opt/eds/Designlab/bin/dot.bashrc ~/. bashrc

Now close the current terminal window and start a new terminal. Then add the DesignLabscript directory to our PATH by:

source /opt/eds/Designlab/bin/dlab.csh

Given the number of EDA tools and files used in the flow, it is strongly recommended toorganize the working environment in a proper way. To that end, the create_eda_projectscript can be used to create a directory structure in which design files will be stored.The use of the script is as follows:

create_eda_project <project -name >

where <project-name> is the name of the top-level directory that will host all design filesfor the projects.For example, to create the project directory called ADDSUB that will be used to do thetasks presented in the rest of this document, execute the following command:

student@tango > create_eda_project ADDSUBstudent@tango > cd ADDSUB

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The ADDSUB top-level directory hosts the configuration files for logic simulation (Mod-elsim), logic synthesis (Synopsys DC) and standard cell place and route (Cadence SoCEncounter). As a consequence, it is required that the tools are always started from thatpoint. One exception is full-custom layout tools (Cadence IC) that must be started from thesubdirectory LAY, which hosts different configuration files.Figure 2 gives the proposed directory structure and the role of each subdirectory. The actualuse of the subdirectories and files will be explained while going throughout the tutorial inthis document.

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<project-name> # project directory home|-- .synopsys_dc.setup # setup file for Synopsys tools|-- modelsim.ini # setup file for Modelsim tool|-- DOC # documentation (pdf, text, etc.)|-- HDL # VHDL/Verilog source files| |-- GATE # gate-level netlists| |-- RTL # RTL descriptions| ‘-- TBENCH # testbenches|-- IP # external blocks (e.g., memories)|-- LAY # full-custom layout files|-- LIB # design libraries| |-- MSIM # Modelsim library (VHDL, Verilog)| ‘-- SNPS # Synopsys library (VHDL, Verilog)|-- PAR # place & route files| |-- BIN # commands, scripts| |-- CONF # configuration files| |-- CTS # clock tree synthesis files| |-- DB # database files| |-- DEX # design exchange files| |-- LOG # log files| |-- RPT # report files| |-- SDC # system design constraint files| |-- TEC # technology files| ‘-- TIM # timing files|-- SIM # simulation files| |-- BIN # commands, scripts| ‘-- OUT # output files (e.g., waveforms)‘-- SYN # synthesis files

|-- BIN # commands, scripts|-- DB # database files|-- LOG # log files|-- RPT # report files|-- SDC # system design constraint files‘-- TIM # timing files

Figure 2: Design project structure.

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2.3 EDA tools and design kit configuration

In order to use the EDA tools and the design kit, a file called edadk.conf must exist in thedirectory from which the tools are launched (the top-level project directory.

The edadk.conf file must include the following lines (order is not important):

mgc msim 6.3asnps syn B-2008.09-SP1-1cds soce 7.1dk Faraday L90_SP

2.4 Installation of the FARADAY design kit

To install the files required by the FARADAY design kit, execute the tech_setup script inthe top-level project directory as follows:

tech_setup -t <toolset >

where: -t select toolsetRunning the command without arguments displays a short help.To install the 90 nm CMOS called L90_SP for logic simulation and synthesis, use:

student@tango -ADDSUB > tech_setup -t synopsys_dc

The command produces the following output:

IMPORTANT NOTICE

Al l FARADAY documentation and des ign f i l e s made av a i l a b l e with t h i scommand

are sub j e c t to non−d i s c l o s u r e agreements between Europract ice , FARADAYand TU Del f t , and hence must be cons ide r ed as s t r i c t l y c o n f i d e n t i a l .For more in fo rmat ion :

Alexander de Graaf , EEMCS−ME−CAS, a . c . deg raa f@tude l f t . n l .

−− Conf igurat ion parameters :FARADAY Design KitProcess : L90_SPTool : synopsys_dc−− Conf igurat ion log :F i l e " . / . synopsys_dc . setup " crea tedF i l e " . / modelsim . i n i " c r ea tedDi rec tory " ./LIB/SNPS" createdSynopsys l i b r a r y l i n k " ./LIB/SNPS/techmap" crea tedSynopsys l i b r a r y l i n k " ./LIB/SNPS/ a l ib −52" crea tedDi rec tory " ./LIB/MSIM" createdModelsim l i b r a r y LIB/MSIM/work createdModifying modelsim . i n iModelsim l i b r a r y WORK mapped to . / LIB/MSIM/work

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The command creates configuration files for Modelsim and Synopsys as well as the requireddesign libraries for hosting compiled VHDL/Verilog models and for simulation.To install the same design kit for standard cell place and route, use:

student@tango -ADDSUB > tech_setup -t cadence_soce

The command produces the following output:IMPORTANT NOTICE

Al l FARADAY documentation and des ign f i l e s made av a i l a b l e with t h i scommand

are sub j e c t to non−d i s c l o s u r e agreements between Europract ice , FARADAYand TU Del f t , and hence must be cons ide r ed as s t r i c t l y c o n f i d e n t i a l .For more in fo rmat ion :

Alexander de Graaf , EEMCS−ME−CAS, a . c . deg raa f@tude l f t . n l .

−− Conf igurat ion parameters :FARADAY Design KitProcess : L90_SPTool : cadence_soce−− Conf igurat ion log :F i l e "PAR/BIN/ f i l l c o r e . t c l " c r ea tedF i l e "PAR/BIN/ f i l l p e r i . t c l " c r ea tedF i l e "PAR/CONF/L90_SP_std . conf " c rea tedF i l e "PAR/CONF/pads . i o " c rea tedF i l e "PAR/DEX/gds2 .map" crea ted

The command creates files in specific locations in the PAR (place and route) subdirectory.The tech_setup command also creates a script file with the necessary PATHs to the tools.Add these PATHs by executing:

student@tango -ADDSUB > source edadk.csh

For information on the FARADAY design kits, find the FARADAY documentation in/opt/eds/DesignLab/tech/Faraday/L90_SP/docs.

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2.5 VHDL example: Adder-subtractor

The adder-subtractor example will be used as the reference design throughout the topdownflow. Listing 1 gives the VHDL model of a generic N bit adder-subtractor. The modelis deliberately quite abstract to show how the synthesiser will be able to infer differentadder architectures ripple carry or carry look-ahead architectures) depending on the givenconstraints. We will call this model the Core.

Listing 1: RTL synthesisable model of a N bit adder-subtractor.l ibrary i e e e ;use i e e e . std_logic_1164 . a l l ;use i e e e . numeric_std . a l l ;

entity addsub i sgeneric (NBITS : natura l := 4) ;port (

c lk , r s t , add : in s td_log i c ;a , b : in unsigned (NBITS−1 downto 0) ;z : out unsigned (NBITS−1 downto 0) ) ;

end entity addsub ;architecture d f l of addsub i s

signal a_reg , b_reg , z_reg : unsigned (NBITS−1 downto 0) ;begin

process ( r s t , c l k )begin

i f r s t = ’1 ’ thena_reg <= ( others => ’0 ’ ) ;b_reg <= ( others => ’0 ’ ) ;z <= ( others => ’0 ’ ) ;

e l s i f c lk ’ event and c l k = ’1 ’ thena_reg <= a ;b_reg <= b ;z <= z_reg ;

end i f ;end process ;

z_reg <= a_reg + b_reg when add = ’1 ’ elsea_reg − b_reg ;

end d f l ;

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However, to design a real chip we have to add IO and PAD cells around the Core to create aDie design. For this purpose we will make use of technology independent generic componentsfor IO and Memory cells defined in the library techmap.Listing 2 gives the code for the toplevel cell addsub_top.

Listing 2: RTL top model of a N bit adder-subtractor.l ibrary i e e e ;use i e e e . std_logic_1164 . a l l ;use i e e e . numeric_std . a l l ;

l ibrary techmap ;use techmap . gencomp . a l l ;use techmap . fod0a_b25_t25_generic_io_dummy_pkg . a l l ;

entity addsub_top i sgeneric (NBITS : natura l := 8 ;

padtech : i n t e g e r := faraday ) ;port (

c lk , r s t , add : in s td_log i c ;a , b : in s td_log ic_vector (NBITS−1 downto 0) ;z : out s td_log ic_vector (NBITS−1 downto 0) ) ;

end entity addsub_top ;

architecture fa r l90_sp of addsub_top i s

component addsub i sgeneric (NBITS : natura l := 4) ;port (

c lk , r s t , add : in s td_log i c ;a , b : in unsigned (NBITS−1 downto 0) ;z : out unsigned (NBITS−1 downto 0) ) ;

end component addsub ;

signal clk_s , rst_s , add_s : s td_log i c ;signal a_s , b_s : s td_log ic_vector (NBITS−1 downto 0) ;signal z_s : unsigned (NBITS−1 downto 0) ;

begin−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− IO + Core P/G−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−io_pg : entity work . addsub_top_pg ( far l90_sp ) ;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− IO S i gna l C e l l s

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−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−io_clk : inpad generic map ( tech => padtech , l im i t =>

core_l imited )port map ( c lk , clk_s ) ;

i o_rst : inpad generic map ( tech => padtech , l im i t =>core_l imited )port map ( r s t , rst_s ) ;

io_add : inpad generic map ( tech => padtech , l im i t =>core_l imited )port map ( add , add_s ) ;

io_a : inpadv generic map ( width => NBITS , tech => padtech ,l im i t => core_l imited )

port map ( a , a_s ) ;io_b : inpadv generic map ( width => NBITS , tech => padtech ,

l im i t => core_l imited )port map (b , b_s) ;

io_z : outpadv generic map ( width => NBITS , tech => padtech ,l im i t => core_l imited )

port map ( z , s td_log ic_vector ( z_s ) ) ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Core Ins tance−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−addsub_1 : entity work . addsub ( d f l )

generic map (NBITS => NBITS

)port map (

c l k => clk_s ,r s t => rst_s ,add => add_s ,a => unsigned (a_s ) ,b => unsigned (b_s) ,z => z_s

) ;end fa r l90_sp ;

To install the VHDL model and its associated testbenches in the project directory, enter thefollowing command in the top-level project directory ADDSUB:

student@tango -ADDSUB > install_design addsub

The following files are copied:HDL/RTL/addsub−d f l . vhd crea tedHDL/RTL/addsub_top_pg . vhd crea ted

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HDL/RTL/addsub_top . vhd crea tedHDL/TBENCH/tb_addsub_top_mapped . vhd crea tedHDL/TBENCH/tb_addsub_top_par . vhd crea tedHDL/TBENCH/tb_addsub_top_rtl . vhd crea tedSYN/BIN/addsub_syn . t c l c r ea tedPAR/BIN/addsub_par . t c l c r ea tedPAR/CONF/addsub_nbits8 . conf c r ea tedPAR/CONF/addsub_nbits8 . i o c r ea tedPAR/CONF/addsub_nbits8 . fp c rea ted

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Listing 3 gives the testbench for the RTL model with N=8 (file tb_addsub_top_rtl.vhd). Itis by far not complete as it only checks one addition and one subtraction. The testbenches forthe mapped design (file tb_addsub_top_mapped.vhd) and for the simulation of the placedand routed Verilog netlist (file tb_addsub_top_par.vhd) only differs by the instantiationof the component under test. The addsub_nbits8.io file defines the positions of the IO pinsfor place and route.

Listing 3: VHDL testbench for the RTL model with N=8.

l ibrary i e e e ;use i e e e . std_logic_1164 . a l l ;use i e e e . numeric_std . a l l ;

entity tb_addsub_top_rtl i s end ;

architecture bench of tb_addsub_top_rtl i sconstant CLK_PER: time := 20 ns ;constant NBITS : natura l := 8 ;signal c l k : s td_log i c := ’ 0 ’ ;signal r s t , add : s td_log i c ;signal a , b , z : s td_log ic_vector (NBITS−1 downto 0) ;

beginUUT: entity work . addsub_top ( far l90_sp )

generic map (NBITS=>NBITS)port map ( c lk , r s t , add , a , b , z ) ;

c l k <= not c l k after CLK_PER/2 ;r s t <= ’0 ’ , ’ 1 ’ after CLK_PER/4 , ’0 ’ after 3∗CLK_PER/4 ;add <= ’1 ’ , ’ 0 ’ after 11∗CLK_PER/4 ;

s t imulus : processbegin

wait for 3∗CLK_PER/4 ;a <= std_log ic_vector ( to_unsigned (31 , a ’ l ength ) ) ;b <= std_log ic_vector ( to_unsigned (12 , b ’ l ength ) ) ;wait ;

end process s t imulus ;end architecture bench ;

The file addsub_syn.tcl in directory SYN/BIN is a Tcl script that performs synthesis of theVHDL model in batch mode. The file addsub_par.tcl in directory PAR/BIN is a Tcl scriptthat performs the placement and routing of the synthesized Verilog netlist in batch mode.

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2.6 Text editing

The edt alias calls the nedit text editor which provides syntax highlighting. It is also possibleto use any other convenient editor such as vi, vim, emacs, xemacs, etc. The Modelsimgraphical environment has its own text editor with syntax highlighting.

2.7 Design flow steps

Here are the main steps of the top-down design flow with references to the sections in thedocument that give more details.

Step 1) VHDL model editing (tool: text editor)

Step 2) Pre-synthesis VHDL simulation (tool: Modelsim)

2.1 Compilation of the RTL VHDL model and related testbench [3.2]

2.2 Simulation of the RTL VHDL model

Step 3) Logic synthesis (tool: Synopsys Design Compiler)

3.1 RTL VHDL model analysis [4.2]

3.2 Design elaboration (generic synthesis) [4.3]

3.3 Design environment definition (operating conditions, wire load model) [4.4]

3.4 Design constraint definitions (area, clock, timings) [4.5]

3.5 Design mapping and optimization (mapping to gates) [4.6]

3.6 Report generation [4.7]

3.7 VHDL gate-level netlist generation [4.8]

3.8 Post-synthesis timing data (SDF) generation for the VHDL netlist [4.8]

3.9 Verilog gate-level netlist generation [4.8]

3.10 Design constraints generation for placement and routing [4.9]

Step 4) Post-synthesis VHDL simulation (tool: Modelsim) [3.3]

4.1 Compilation of the VHDL/Verilog netlist and related testbench

4.2 Simulation of the post-synthesis gate-level netlist with timing data

Step 5) Placement and routing (tool: Cadence Encounter)

5.1 Design import (technological data + Verilog netlist) [5.2]

5.2 Floorplan specification [5.3]

5.3 Power ring/stripe creation and routing [5.4]

5.4 Global net connections definition [5.5]

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5.5 Operating conditions definition [5.6]

5.6 Core cell placement [5.7]

5.7 Post-placement timing analysis [5.8]

5.8 Clock tree synthesis (optional) [5.9]

5.9 Design routing [5.10]

5.10 Post-route timing optimization and analysis [5.11]

5.11 Filler cell placement [5.12]

5.12 Design checks [5.13]

5.13 Report generation [5.14]

5.14 Post-route timing data extraction [5.15]

5.15 Post-route netlist generation [5.16]

5.16 GDS2 file generation [5.17]

Step 6) Post-layout VHDL/Verilog simulation (tool: Modelsim) [3.4]

6.1 Compilation of the Verilog netlist and related testbench

6.2 Simulation of the post-synthesis or post-PaR gate-level netlist with PaR timingdata

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3 VHDL and Verilog simulationThis chapter presents the main steps to perform the logic simulation of VHDL and Verilogmodels with the Modelsim tool.

3.1 Starting the Modelsim graphical environment

To start the Modelsim environment, enter in the vsim command in the Unix shell:

student@tango -ADDSUB > vsim &

Figure 3: Modelsim console window

The modelsim.ini file actually defines the mapping between logical design libraries andtheir physical locations. Note that the Help menu on the top right allows one to access thecomplete documentation of the tool.

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3.2 Simulation of (pre-synthesis) RTL VHDL models

The task here is to validate the functionality of the VHDL model that will be synthesized.The first step is to compile the VHDL model and its associated testbench. There are twoways to compile VHDL models. One way is to execute the vcom command from the commandline of the Modelsim window:

ModelSim > vcom HDL/RTL/addsub_dfl.vhdModelSim > vcom HDL/RTL/addsub_top_pg.vhdModelSim > vcom HDL/RTL/addsub_top.vhdModelSim > vcom HDL/TBENCH/tb_addsub_top_rtl.vhd

The other way is to left-click on the Compileicon , to select the files to compile in theHDL/RTL and HDL/TBENCH directories, clickon Compile and finally close the window (clickDone).The compiled modules are stored in the logicallibrary WORK which is mapped to the physicallocation LIB/MSIM. Once VHDL (or Verilog)models have been successfully compiled in thedesign library, it is possible to create a make file that can be used to recompile only therequired files. The vmake command can only be run from a Unix shell and creates the makefile:

student@tango -ADDSUB > vmake > Makefile

The created file Makefile now defines the design unit dependencies and the compilationcommands to recompile only those source files that have been modified or that depend onmodified files. To rebuild the library, run the make command in the Unix shell

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To simulate the RTL model, select the mainmenu itemSimulate -> Start simulation...to get the simulation dialog window. Selectthe architecture of the testbench and a reso-lution of ns. Then click OK.

The main window now changes a bit to show the simulation hierarchy, the list of signals inthe testbench and the simulation console (with now the VSIM number> prompt).Left clicking twice on an instance in the simulation hierarchy pane displays the correspondingVHDL source in the right pane.

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The next step is to select the signals to display in simu-lation. Right click in the Objects (top center) pane, thenselect Add to Wave -> Signal in Region.Note that the appropriate hierarchy level is selected in thesimulation hierarchy window. Selecting another level, e.g.uut, will display all the signals visible in this scope. Youmay want to add selected signals from inner levels (localsignals).The selected signals are displayed in a new window calledwave. The wave pane is by default located on the top right(as a new tab on the source windows). You can click on

the Undock icon to make the wave pane separate.To start the simulation, it is either possible to enter runcommands in the simulation console such as:

VSIM 7> run 100 ns

or to click on the Run icon in the main window or in the wave window.The signal waveforms are then visible in the wave window. To change the radix of thedisplayed signals, select the signals (press shift left-click for multiple selection), then selectthe wave menu item Format -> Radix -> Unsigned.

Note that the command run -all runs the simulation until there is no more pending event inthe simulation queue. This could lead to never ending simulation when the model, like thetestbench loaded here, has a continuously switching signal such as the clock signal clk. It is

however possible to stop the current simulation by clocking the Break icon in the mainwindow or in the wave window.If you make any modification to the VHDL source, you need to recompile the sources (man-ually or using the vmake command described earlier in this section), and then restart thesimulation in the same environment (e.g., the same displayed waveforms or the same simu-lation breakpoints) with the restart -f command.

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3.3 Simulation of the post-synthesis VHDL model with timing data

This step occurs after the RTL model has been synthesized into a gate-level netlist. Thetiming information about the design is stored in a SDF file. See -4.8 VHDL/Verilog gate-levelnetlist generation and post-synthesis timing data (SDF) extraction.Compile the VHDL gate-level netlist generated by the logic synthesis and its testbench:

ModelSim > vcom HDL/GATE/addsub_top_nbits8_mapped.vhdl...ModelSim > vcom HDL/TBENCH/tb_addsub_top_mapped.vhd...

To simulate the RTL model, select the main menu item Simulate -> Start simulation...to get the simulation dialog window. Select the architecture of the testbench and a resolutionof 100ps. Click the Libraries tab to add the gate libraries fsd0a_a_generic_core andfod0a_b25_t25_generic_io, then click the SDF tab.In the SDF dialog window, add the file SYN/TIM/addsub_top_nbits8_mapped.sdf andspecify the region UUT, which is the label of the instance in the testbench that will beannotated with timing data.Note that the Reduce SDF errors to warnings box must be checked. This is requiredto avoid the simulation to stop prematurely due to errors such as F̈ailed to find port ´a(7)´̈.These are not really errors here as they are related to interconnect delay data in the SDFfile that are not used in the simulation (they are actually all set to zero).

Then click OK in the remaining Start Simulation dialog box to load the mapped netlist.

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Clock to output delays of the order of 500ps to 1ns should be visible in the wave window.

3.4 Simulation of the post-route Verilog model with timing data

This step occurs after the design has been placed and routed. See "5.15 Post-route timingdata extraction" and "5.16 Post-route netlist generation". This steps involves the simulationof a Verilog gate-level netlist with a VHDL testbench.Before compiling the Verilog netlist and the associated VHDL testbench, it is necessary toprepare the design library. The vdir -r command gives the content of the design library:

student@tango -ADDSUB > vdir -r

Library Vendor : Model TechnologyMaximum Unnamed Designs : 3OPTIMIZED DESIGN _optOPTIMIZED DESIGN _opt1OPTIMIZED DESIGN _opt2ENTITY addsub

ARCH d f lENTITY addsub_nbits8

ARCH syn_dflENTITY addsub_top

ARCH far l90_spENTITY addsub_top_nbits8

ARCH syn_farl90_spENTITY addsub_top_pg

ARCH far l90_spPACKAGE conv_pack_addsub_top_nbits8. . .ENTITY tb_addsub_top_mapped

ARCH benchENTITY tb_addsub_top_rtl

ARCH bench

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The ENTITY and ARCHITECTURE keywords denote VHDL design units. The problem isthat the modules in the Verilog netlist have the same names as in the VHDL post-synthesismodels (actually they only differ in the case of some name parts). To allow the VHDLtestbench HDL/tb_addsub_par.vhd to instantiate a Verilog model, the direct instantiationstatement cannot include the architecture name. Therefore, a default mapping is consideredand the design library must only contain the required compiled units. As a consequence,some existing units must be deleted from the library with the vdel command:

student@tango -ADDSUB > vdel addsub_nbits8_dw01_addsub_0

student@tango -ADDSUB > vdel addsub_top_nbits8

Note that this could also be done from within the Modelsim GUI.Now you can compile the Verilog netlist and the VHDL testbench:

student@tango -ADDSUB > vlog HDL/GATE/addsub_top_nbits8 -routed.vstudent@tango -ADDSUB > vcom HDL/TBENCH/tb_addsub_top_par.vhd

To simulate the placed and routed netlist with timing data, select the item Simulate ->Start simulation... in the main menu to get the simulation dialog window. Select thearchitecture of the testbench and a resolution of 100ps. Then click the Libraries tab toadd the gate libraries fsd0a_a_generic_core and fod0a_b25_t25_generic_io, and load theSDF timing file PAR/TIM/addsub_nbits8-routed.sdf.Note that the Reduce SDF errors to warnings box must be checked. This is required toavoid the simulation to stop prematurely due to errors such as “Failed to find matchingspecify timing constraint”. These are not really errors here as they are related to removal(asynchronous) timing constraints generated by Encounter that are not supported in theVerilog models of the gates.

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Then click OK in the remaining Start Simulation dialog box to load the mapped netlist.Clock to output delays of the order of 800ps to 1000ps should be visible in the wave window.

More accurate values for the delays can be obtained using a smaller time unit in simulation(e.g., 10ps or less).

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4 Logic synthesisThis chapter presents the main steps to perform the logic synthesis of the VHDL RTLmodel with the Synopsys Design Vision and Design Compiler tools. The sold alias displaysthe complete Synopsys documentation set. Manual pages are available by executing thecommand “snps man command” (e.g., snps man design_vision).

4.1 Starting the Design Vision graphical environment

To start the Synopsys Design Vision environment, enter the design_vision command in anew shell:

student@tango -ADDSUB > design_vision

The command line is also echoed in the terminal shell from which the tool has been started,so it is possible to enter DC commands from there as well(the shell has the design_vision> prompt). It is still possible to execute some Unix com-mands from here.

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4.2 RTL VHDL model analysisThe analysis phase compiles the VHDL modeland checks that the VHDL code is synthesizable.Select File -> Analyze... in the main menu.Use the Add... button to add all the VHDLsources you need to analyze.In the case you have more than one VHDL file toanalyze, be careful to list the files in the correctanalysis order.Click OK.

4.3 Design elaborationThe elaboration phase performs a genericpre-synthesis of the analyzed model. Itessentially identifies the registers thatwill be inferred.Select File -> Elaborate... in themain menu.The DEFAULT library is identical tothe WORK library. Specify the valuefor the NBITS generic parameter to 8.Click OK.The console now displays the inferredregisters and the kind of reset (hereasynchronous reset - AR: Y).

Note the name addsub_top_NBITS8 given to the elaborated entity.

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It is possible to display the elaborated schematic by selecting the entity addsub_NBITS8in the hierarchy window and then clicking the Create Design Schematic icon . Notethat the symbols merely indicate generic components that do not yet represent any real logicgate.

4.4 Design environment definition

Before a design can be optimized, you must define the environment in which the design isexpected to operate. You define the environment by specifying operating conditions, wireload models, and system interface characteristics. Operating conditions include temperature,voltage, and process variations. Wire load models estimate the effect of wire length ondesign performance. System interface characteristics include input drives, input and outputloads, and fanout loads. The environment model directly affects design synthesis results.Here we will only deal with operating conditions and wire load models. To define theoperating conditions, select the main menu item Attributes -> Operating Environment-> Operating Conditions...Select the WCCOM condition, which defines a temperature of 85˚C, a voltage of 1V (theL90_SP process is a 1V process), and a slow process. Each cell library defines its own setof operating conditions and may use different names for each set.

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Click OK.Wire load models allow the tool to estimate the effect of wire length and fanout on theresistance, capacitance, and area of nets. The FARADAY design kit defines a number ofwire load models. It also defines an automatic selection of the wire load model to useaccording to the design area, which is actually considered here.To get the definitions of the available operating conditions (and on the cell library), executethe report_lib command in the tool command line:report_lib fsd0a_a_generic_core_wcThe report_design command summarizes the definitions of the design environment.

4.5 Design constraint definitions

Many kinds of constraints may be defined on the design. Here only constraints on the areaand the clock will be defined. To define the clock attributes, i.e. its period and duty cycle,select the entity addsub_NBITS8 in the hierarchy window and then click the Create Symbol

View icon.

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In the symbol view, select the clk pin and then select themain menu item Attributes -> Specify Clock.... Definea clock period of 10 ns with 50% duty cycle. Time unit is notspecified here. It is defined in the cell library and is usuallyns.Click OK. The console now includes the command line equiv-alent of the clock definition:create_clock -name "clk" -period 10-waveform { 0 5 } { clk }

To define an area constraint, select in the main menu theitemAttributes -> Optimization Constraints -> DesignConstraints....A max area constraint set to zero is not realistic but it willforce the synthesizer to target a minimum area.Click OK. The console now includes the command lineequivalent of the constraint definition:set_max_area 0

It is a now good idea to save the elab-orated design so it will be possible torun several optimization steps fromthat point.Select the entity addsub_top_NBITS8in the hierarchy window and then themain menu item File -> Save As....Save the elaborated design under thename addsub_top_nbits8_elab.ddcin the SYN/DB directory.The selection of the option Save all design in hierarchy is relevant for hierarchical designs.The console includes the equivalent command line:write -hierarchy -format ddc -output .../ADDSUB/SYN/DB/addsub_top_nbits8_elab.ddcTo read back an elaborated design, select the main menu item File -> Read... and thenselect the file to read.

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4.6 Design mapping and optimizationThe optimization phase, also called herecompilation phase, is technology depen-dent. It performs the assignment of logicgates from the standard cell library to theelaborated design in such a way the de-fined constraints are met.Select the main menu itemDesign -> Compile Ultra....For a first run there is no need to changethe default settings.Click OK. The console and the Unix shellnow include the progress of the work.

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The equivalent command line is: compile_ultra -map_effort medium -area_effortmedium

The mapped design schematic is now hierarchical as it includes one instance of a 8 bit adderand one instance of a 8 bit subtractor. Also, the cells are now real gates from the cell library.The inferred 8 bit adder has a ripple-carry architecture and uses the available FA1X standardcell that implements a 1 bit full adder.The inferred 8 bit subtractor also uses a riple-carry architecture.

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Note that the default resource allocation and implementation for operative parts is based ontiming constraints.This means that resource sharing is used so that timing constraints are met or not worsened.In our case, a single adder has been inferred for both adder and subtractor operations.The mapped design can now be saved. Select the entity addsub_top_NBITS8 in the hier-archy window and then the main menu item File -> Save As.... Save the mapped designunder the name addsub_top_nbits8_mapped.ddc in the directory SYN/DB.

4.7 Report generation

It is possible to get many reports on various synthesis results. Here only reports on the areaused, critical path timing and the resources used will be generated.To get a report of the area used by the mapped design, select the main menu item Design> Report Area....Save the report in the fileSYN/RPT/addsub_top_nbits8_mapped_area.rpt as well as in the report viewer. ClickOK. A new window and the console now display the report:

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

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Report : areaDesign : addsub_top_NBITS8Vers ion : B−2008.09−SP1−1Date : Tue Apr 28 08 : 57 : 15 2009∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

Library ( s ) Used :

fsd0a_a_generic_core_wc ( F i l e : / opt/ eds /Des ignKits /Faraday/L90_SP/Core/fsd0a_a /2007Q1v1 .7/GENERIC_CORE_1D0V/FrontEnd/ synopsys /fsd0a_a_generic_core_wc . db)

fod0a_b25_t25_generic_io_ss0p9v125c ( F i l e : / opt/ eds /DesignKits /Faraday/L90_SP/IO/fod0a_b25/2007Q3v1 .3/T25_GENERIC_IO/FrontEnd/ synopsys /fod0a_b25_t25_generic_io_ss0p9v125c . db )

Number o f por t s : 27Number o f net s : 54Number o f c e l l s : 7Number o f r e f e r e n c e s : 7

Combinational area : 209763.000000Noncombinational area : 88560.000000Net In t e r connec t area : undef ined (Wire load has zero net area )

Total c e l l area : 298323.000000Total area : undef ined

The area unit depends on the standard cell library. Here all area figures are in squaremicrons. The net interconnect area is estimated with the use of a wire load model that hasbeen automatically selected from the design area.To get a report on the most critical timing path in the mapped design, select the main menuitem Timing -> Report Timing PathSave the report in the fileSYN/RPT/addsub_top_nbits8_mapped_timing.rpt as well as in the report viewer.Click OK. A new window and the console now display the report:

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗Report : t iming

−path f u l l−delay max−max_paths 1−sort_by group

Design : addsub_top_NBITS8Vers ion : B−2008.09−SP1−1Date : Tue Apr 28 09 : 07 : 40 2009∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

Operating Condit ions : WCCOM Library : fsd0a_a_generic_core_wcWire Load Model Mode : enc l o s ed

Sta r tpo in t : add ( input port )

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Endpoint : addsub_1/z_reg [ 7 ]( r i s i n g edge−t r i g g e r e d f l i p −f l o p c locked by c l k )

Path Group : c l kPath Type : max

Des/Clust /Port Wire Load Model Library−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−addsub_top_NBITS8 enG100K fsd0a_a_generic_core_wcaddsub_NBITS8 enG5K fsd0a_a_generic_core_wc

Point Inc r Path−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−c l o ck ( input port c l o ck ) ( r i s e edge ) 0 .00 0 .00input ex t e rna l de lay 0 .00 0 .00 radd ( in ) 0 .00 0 .00 rio_add/pad ( inpad_25_0_3_0_8_1_17) 0 .00 0 .00 rio_add/x0/ ip /O (UYNGB) 0 .64 0 .64 rio_add/o ( inpad_25_0_3_0_8_1_17) 0 .00 0 .64 raddsub_1/add (addsub_NBITS8) 0 .00 0 .64 raddsub_1/U35/O (INVX1) 0 .12 0 .76 faddsub_1/U33/O (MUX2X1) 0 .18 0 .93 faddsub_1/U26/O (MAO222X1) 0 .16 1 .09 faddsub_1/U19/O (MAO222X1) 0 .16 1 .26 faddsub_1/U12/O (MAO222X1) 0 .16 1 .42 faddsub_1/U5/O (MAO222X1) 0 .15 1 .57 faddsub_1/DP_OP_11_296_6182/U4/CO (FA1X1) 0 .14 1 .70 faddsub_1/DP_OP_11_296_6182/U3/CO (FA1X1) 0 .12 1 .82 f

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addsub_1/DP_OP_11_296_6182/U1/O (XOR2X1) 0 .10 1 .92 faddsub_1/z_reg [ 7 ] /D (QDFFRBX1) 0 .00 1 .92 fdata a r r i v a l time 1 .92

c l o ck c l k ( r i s e edge ) 10 .00 10 .00c l o ck network de lay ( i d e a l ) 0 .00 10 .00addsub_1/z_reg [ 7 ] /CK (QDFFRBX1) 0 .00 10 .00 rl i b r a r y setup time −0.14 9 .86data r equ i r ed time 9 .86−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−data r equ i r ed time 9 .86data a r r i v a l time −1.92−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−s l a ck (MET) 7 .94

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All times are expressed in ns (the time unit is defined in the cell library). The slack definesthe time margin from the clock period. A positive slack means that the latest arriving signalin the path still arrives before the end of the clock period. A negative slack means that thetiming constraint imposed by the clock is violated.The timing delays that are accounted for are the internal gate delays (from the cell library)and the estimated interconnect delays (from the cell library and the wire load model in use).To highlight the critical path on the schematic, select the addsub_top_NBITS8 entity inthe hierarchy window and then the Select menu item Paths From/Through/To... . Youcan see that the path goes through the addsub_1 component so you can also select thecomponent and do the same to visualize the critical path inside the component.

Another useful report is the list of resources used. A resource is an arithmetic or comparisonoperator read in as part of an HDL design. Resources can be shared during execution of thecompile command.To get a report on the resources used, select the main menu item Design -> ReportDesign Resources....Save the report in the fileSYN/RPT/addsub_top_nbits8_mapped_resources.rpt as well as in the report viewer.Click OK.

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A new window and the console now displaythe report:

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗Report : r e s ou r c e sDesign : addsub_top_NBITS8Vers ion : B−2008.09−SP1−1Date : Tue Apr 28 09 : 40 : 06 2009∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗Design : addsub_NBITS8∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

Resource Report f o r t h i s h i e ra r chy in f i l e/mnt/ tango/md2/ use r s / sander /tmp/ADDSUB/HDL/RTL/addsub−d f l . vhd

=============================================================================| Ce l l | Module | Parameters | Contained Operat ions |

=============================================================================| DP_OP_11_296_6182 | | || | DP_OP_11_296_6182 | | |

=============================================================================

Datapath Report f o r DP_OP_11_296_6182==============================================================================| Ce l l | Contained Operat ions |

==============================================================================| DP_OP_11_296_6182 | add_29 sub_29 |

==============================================================================

==============================================================================| | | Data | | || Var | Type | Class | Width | Express ion |

==============================================================================| I1 | PI | Signed | 8 | || I2 | PI | Signed | 8 | || I3 | PI | Unsigned | 1 | || O1 | PO | Signed | 8 | addsub ( I1 , I2 , I3 ) |

==============================================================================

No implementat ions to r epor t

No mu l t i p l exo r s to r epor t

You can see that the inferred arithmetic component is implemented as a ripple-carry (rpl)architecture. The tool uses the so-called DesignWare library which contains a number ofpredefined HDL models of blocks (arithmetic, etc.) with several possible architectures foreach block. The best architecture is selected to meet the design constraints.

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4.8 VHDL/Verilog gate-level netlist generation and post-synthesistiming data (SDF) extraction

This step generates a VHDL model of the mapped design for simulation and a Verilog modelof the same design to be used as input to the placement and routing tool. It also generatesa SDF (Standard Delay Format) file that includes the gate delays. Care should be taken touse the right naming scheme when generating the SDF file, otherwise the back-annotation ofthe delays onto the VHDL or Verilog netlists for simulation will fail. Here we only considerthe back-annotation of VHDL netlists.Before generating the VHDL netlist, it is required to apply some VHDL naming rules to thedesign. This is done by entering the following command in the console (be sure that theentity addsub_top_NBITS8 is selected in the hierarchy window):change_names -hierarchy -rules vhdl -verbose

Save the mapped design in the fileaddsub_top_nbits8_mapped.vhdl in the directory HDL/GATE.Note: the dialog window creates HDL files with the .vhdl extension rather than .vhd as usedso far.

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Click Save. The console now echoes the equivalent command line:write -hierarchy -format vhdl -output .../ADDSUB/HDL/GATE/addsub_top_nbits8_mapped.vhdl

To generate the SDF file, enter the following command in the consolewrite_sdf -version 3 SYN/TIM/addsub_top_nbits8_mapped.sdfInformation: Annotated ’cell’ delays are assumed to include load delay.The informational message says that the estimated interconnect delays are actually includedin the SDF file as part of the cell delays. The generated SDF file actually includes a list ofinterconnect delays of zero values.Before generating the Verilog netlist, it is better to reload the database and apply specificVerilog naming rules to the design. This is done by selecting File -> Remove All Designsfrom the main menu, then reading the database file ./SYN/DB/addsub_top_nbits8_mapped.ddc,and entering the following command in the console (be sure that the entity addsub_top_NBITS8is selected in the hierarchy window):change_names -hierarchy -rules verilog -verbose

Save the mapped design in the file addsub_top_nbits8_mapped.v in the directory HDL/-GATE.Click Save. The console now echoes the equivalent command line:write -hierarchy -format verilog-output .../ADDSUB/HDL/GATE/addsub_dfl_nbits8_mapped.v

4.9 Design constraints generation for placement and routing

Both design environment and design constraint definitions may be stored in a format thatcan be read by other Synopsys tools such as PrimeTime or other EDA tool such as CadenceSoc Encounter.

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The following command creates a new file that includes the design constraints that havebeen defined for synthesis in Tcl format:write_sdc -nosplit SYN/SDC/addsub_top_nbits8_mapped.sdcIt is important to do that step after the Verilog naming rules have been applied to the mappeddesign (see 4.8), otherwise there could be discrepencies on port/signal names between thenetlist and the constraint file.

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4.10 Design optimization with tighter constraints

It is possible to let the synthesizer infer another faster adder architecture, e.g., a carry look-ahead architecture, by shortening the clock period. The goal here is to redo some steps inthis chapter and to compare the results with the ones obtained with the initially s̈lowc̈lock.

1. Read the elaborated design. It is not necessary to re-analyze the VHDL sources.

2. Specifiy the clock with a 5 ns period.

3. Save the new elaborated entity in the file SYN/DB/addsub_top_nbits8_5ns_elab.db.

4. Map and optimize the design.

5. Save the mapped design in the file SYN/DB/addsub_top_nbits8_5ns_mapped.db.

6. Get the new area, timing and resources reports. Compare with the reports you got forthe 10 ns clock period.

7. Generate the VHDL gate-level netlist in

HDL/GATE/addsub_top_nbits8_5ns_mapped.vhdl

and the associated SDF timing data file in

SYN/TIM/addsub_top_nbits8_5ns_mapped.sdf.

8. Do a post-synthesis simulation.

9. Generate the Verilog gate-level netlist in HDL/GATE/addsub_top_nbits8_5ns_mapped.v.

10. Save the design constraints for placement and routing in the file

SYN/SDC/addsub_top_nbits8_5ns_mapped.sdc

4.11 Using scripts

It is much more convenient to use scripts and to run the synthesis tool in batch mode whenthe design complexity increases. Scripts also conveniently capture the synthesis flow andmake it reusable. Synopsys Design Compiler supports the Tcl language for building scripts.An example of such a script for the synthesis of the adder-subtrator design has been installedin the SYN/BIN directory (see “2.5 VHDL example: Adder-subtractor”). The script mustbe run from the project top directory and it assumed a directory organization as describedin “1.2 Design project organisation”. To run the Tcl script, execute the following commandin a Unix shell:

student@tango -ADDSUB > dc_shell -f SYN/BIN/addsub_syn.tcl

When the script finishes executing, the dc_shell environment is still active so you can enterother dc_shell commands. Enter quit or exit to return to the Unix shell.The script is given below. It may be modified to define design information and constraintsand to control the flow to some extent.

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## Synopsys DC s h e l l script for adder− sub t rac tor .## Proces s : Faraday 90 nm CMOS (L90_SP)##−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# I t i s assumed t ha t a p r o j e c t d i r e c t o r y s t r u c t u r e has a l r eady been# crea t ed us ing ’ crea te_pro jec t ’ and t ha t t h i s s y n t h e s i s script i s# execu ted from the p r o j e c t roo t d i r e c t o r y $PROJECT_DIR#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set PROJECT_DIR [pwd ]#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Design r e l a t e d in format ion ( can be changed )#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set VHDL_ENTITY addsub_topset VHDL_ARCH far l90_spset NBITS 8set CLK_NAME c lk# a l l time va l u e s are in nsset CLK_PERIOD 10 ;set INPUT_DELAY 2 ;set OUTPUT_DELAY 2 ;set OPERATING_COND WCCOM#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Flags t ha t d r i v e the script behav ior ( can be changed )## DB_FORMAT ( db | ddc )# i f db , use the o ld DB format to s t o r e des i gn in format ion# i f ddc , use the new XG format to s t o r e des i gn in format ion ( recommended )# SHARE_RESOURCES (0 | 1)# i f 1 , f o r c e the t o o l to share re source s as much as p o s s i b l e# i f 0 , no resource shar ing# COMPILE_SIMPLE (0 | 1)# i f 1 , on ly do a s i n g l e compi le wi th default arguments# i f 0 , do a two−step compi la t ion wi th ungrouping in between# OPT ( string )# can be used to have d i f f e r e n t mapped f i l e names#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set DB_MODE ddcset SHARE_RESOURCES 1set COMPILE_SIMPLE 1set OPT "" ;# to denote the 10ns clock per iod case#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Fi l e names#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set SOURCE_FILE_NAME ${VHDL_ENTITY}

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set ROOT_FILE_NAME ${VHDL_ENTITY}_nbits$ {NBITS}set VHDL_SOURCE_FILE_NAME ${SOURCE_FILE_NAME} .vhdset ELAB_FILE_NAME ${ROOT_FILE_NAME}_elabset MAPPED_FILE_NAME ${ROOT_FILE_NAME}${OPT}_mappedset DB_ELAB_FILE_NAME ${ELAB_FILE_NAME}.$DB_MODEset DB_MAPPED_FILE_NAME ${MAPPED_FILE_NAME}.$DB_MODEset VHDL_NETLIST_FILE_NAME ${MAPPED_FILE_NAME} .vhdset VLOG_NETLIST_FILE_NAME ${MAPPED_FILE_NAME} .vset SDF_FILE_NAME ${MAPPED_FILE_NAME} . s d fset SDC_FILE_NAME ${MAPPED_FILE_NAME} . sd cset RPT_AREA_FILE_NAME ${MAPPED_FILE_NAME} _area . rptset RPT_TIMING_FILE_NAME ${MAPPED_FILE_NAME}_timing.rptset RPT_RESOURCES_FILE_NAME ${MAPPED_FILE_NAME} _re sou r c e s . rp tset RPT_REFERENCES_FILE_NAME ${MAPPED_FILE_NAME} _re f e r en c e s . r p tset RPT_CELLS_FILE_NAME ${MAPPED_FILE_NAME} _c e l l s . r p tset RPT_POWER_FILE_NAME ${MAPPED_FILE_NAME}_power.rpt#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Abso lu te paths#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set VHDL_SOURCE_DIR ${PROJECT_DIR}/HDL/RTLset VHDL_SOURCE_FILE ${VHDL_SOURCE_DIR}/${VHDL_SOURCE_FILE_NAME}set VHDL_NETLIST_FILE ${PROJECT_DIR}/HDL/GATE/${VHDL_NETLIST_FILE_NAME}set VLOG_NETLIST_FILE ${PROJECT_DIR}/HDL/GATE/${VLOG_NETLIST_FILE_NAME}set DB_ELAB_FILE ${PROJECT_DIR}/SYN/DB/${DB_ELAB_FILE_NAME}set DB_MAPPED_FILE ${PROJECT_DIR}/SYN/DB/${DB_MAPPED_FILE_NAME}set SDF_FILE ${PROJECT_DIR}/SYN/TIM/${SDF_FILE_NAME}set SDC_FILE ${PROJECT_DIR}/SYN/SDC/${SDC_FILE_NAME}set RPT_AREA_FILE ${PROJECT_DIR}/SYN/RPT/${RPT_AREA_FILE_NAME}set RPT_TIMING_FILE ${PROJECT_DIR}/SYN/RPT/${RPT_TIMING_FILE_NAME}set RPT_RESOURCES_FILE ${PROJECT_DIR}/SYN/RPT/${RPT_RESOURCES_FILE_NAME}set RPT_REFERENCES_FILE ${PROJECT_DIR}/SYN/RPT/${RPT_REFERENCES_FILE_NAME}set RPT_CELLS_FILE ${PROJECT_DIR}/SYN/RPT/${RPT_CELLS_FILE_NAME}set RPT_POWER_FILE ${PROJECT_DIR}/SYN/RPT/${RPT_POWER_FILE_NAME}#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Analyze RTL source#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−analyze −format vhdl − l ib WORK ${VHDL_SOURCE_DIR}/ addsub−dfl .vhdanalyze −format vhdl − l ib WORK ${VHDL_SOURCE_DIR}/addsub_top−pg.vhdanalyze −format vhdl − l ib WORK $VHDL_SOURCE_FILEcurrent_des ign ${VHDL_ENTITY}#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Elabora te des i gn#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−e l abo ra t e $VHDL_ENTITY \−arch $VHDL_ARCH \− l ib DEFAULT −update \

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−param [ set NBITS $NBITS ]#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Define environment#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set_dont_touch [ l i s t addsub_far_pads addsub_far_pg ]#set_dont_touch [ l i s t VCCKGB GNDKGB VCC2IOGB GND2IOGB CORNERGB PAD9M126G]#se t_opera t ing_cond i t ions − l i b rary fsd0a_a_generic_core_wc $OPERATING_COND#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Define c on s t r a i n t s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−create_c lock −name $CLK_NAME −period $CLK_PERIOD [ get_ports $CLK_NAME]set_input_delay $INPUT_DELAY −clock $CLK_NAME [ l i s t [ a l l_ input s ] ]set_output_delay $OUTPUT_DELAY −clock $CLK_NAME [ l i s t [ a l l_outputs ] ]set_max_area 0set_fix_mult iple_port_nets −all#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Set resource a l l o c a t i o n and implementat ion#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set_resource_implementat ion use_fa s t e s ti f { $SHARE_RESOURCES } {se t_re sour c e_a l l o ca t i on area_only} else {s e t_re sour c e_a l l o ca t i on none}#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Save e l a b o ra t e d des i gn and con s t r a i n t s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wr i t e −hierarchy −format $DB_MODE −output $DB_ELAB_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Map des i gn to ga t e s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−i f { $COMPILE_SIMPLE } {compi le_ultra} else {compi le_ultra −map_effort medium −area_ef fort mediumungroup −all − f l a t t encompi le_ultra − incremental −map_effort high}#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Save mapped des i gn#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wr i t e −hierarchy −format $DB_MODE −output $DB_MAPPED_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Generate r epo r t s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−report_area −nosp l i t −hierarchy > $RPT_AREA_FILE

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report_power −nosp l i t −hier −hier_leve l 2 > $RPT_POWER_FILEreport_timing −path f u l l \−delay max \−nworst 1 \−max_paths 1 \− s i g n i f i c an t_d i g i t s 2 \−nosp l i t \−sort_by group \> $RPT_TIMING_FILErepor t_re source s −nosp l i t −hierarchy > $RPT_RESOURCES_FILErepo r t_re f e r ence −nosp l i t > $RPT_REFERENCES_FILErepo r t_ce l l −nosp l i t > $RPT_CELLS_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Generate VHDL n e t l i s t#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−change_names −rule vhdl −hierarchy −verbosewr i t e −format vhdl −hierarchy −output $VHDL_NETLIST_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Generate SDF data#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−write_sdf −version 3 $SDF_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Generate Ver i l o g n e t l i s t## The des i gn i s re l oaded from sc ra t ch to avoid p o t e n t i a l naming problems# when us ing the n e t l i s t for placement and rou t ing#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−remove_design −allr e ad_ f i l e −format $DB_MODE $DB_MAPPED_FILEchange_names −rule v e r i l o g −hierarchy −verbosewr i t e −format v e r i l o g −hierarchy −output $VLOG_NETLIST_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Save system con s t r a i n t s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−write_sdc −nosp l i t $SDC_FILE

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5 Standard cell placement and routingThis chapter presents the main steps to perform the placement and the routing of thesynthesized gate-level netlist using standard cells from the FARADAY design kit. The toolused here is Cadence Encounter. The cdsdoc on-line command gives access to the Cadencedocumentation. The tool also has a Help menu.

5.1 Starting the Encounter graphical environment

To start the Encounter environment, enter the encounter command in a new Unix shell:

student@tango -ADDSUB > encounter -log PAR/LOG/encounter -overwrite

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that includes all commands entered in the session. If the -overwrite switch is not used, bothlog and command files are incremented at each new session. The Unix shell from which thetool is started is called the Encounter console. The console displays the encounter> prompt.This is where you can enter all Encounter text commands and where the tool displaysmessages. If you use the console for other actions, e.g., Unix commands, the Encountersession suspends until you finish the action.The main window includes three different design views that you can toggle dur-ing a session: the Floorplan view, the Amoeba view, and the Physical view.The Floorplan view displays the hierarchical module and block guides, connec-tion flight lines, and floorplan objects, including block placement, and pow-er/ground nets. The Amoeba view displays the outline of the modules andsubmodules after placement, showing physical locality of the module. ThePhysical view displays the detailed placements of the module’s blocks, stan-dard cells, nets, and interconnects.The main window includes a satellite window, which identifies the location of the currentview in the design display area, relative to the entire design. The chip area is identified by ayellow box, the satellite view is identified by the pink crossbox. When you display an entirechip in the design display area, the satellite crossbox encompasses the chip area yellow box.When you zoom and pan through the chip in the design display area, the satellite crossboxidentifies where you are relative to the entire chip.

• To move to an area in the design display area, click and drag on the satellite crossbox.

• To select a new area in the design display area, click and drag on the satellite crossbox.

• To resize an area in the satellite window, click with the Shift key and drag a corner ofthe crossbox.

• To define a chip area in the satellite window, right-click and drag on an area.

There are a number of binding keys available (hit the key when the Encounter GUI is active):

b display the list of binding keys

d (de)select or delete objects

f zoom the display to fit the core area

k create a ruler

K remove last ruler displayed

q display the object attribute editor form for the selected object; click the left-button mouseto select an object, Shift-click to select or deselect an object

u undo last command

U redo last command

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z zoom-in 2x

Z zoom-out 2x

Arrows pan the display.

Hit CTRL-R to refresh the display.

5.2 Design import

Importing the design into Encounter involves specifying the following setup information:Design libraries and files. This in-cludes information on the technologicalprocess and the cell library in the LEF(Layout Exchange Format) format. LEFfiles provides information such as metaland via layers and via generate ruleswhich is used for routing tasks. They alsoprovide the minimum information on celllayouts for placement and routing.Gate-level netlist. This relates to the(Verilog) netlist to be placed and routed.Timing libraries. This includes infor-mation on the cell timings (delays, se-tup/hold times, etc.).To start the design import, select Design -> Design Import... in the main menu. Then,click on the Load... button and load the file PAR/CONF/L90_SP_std.confThis file defines a basic import configuration.There is a number of additions and changes to bring to the initial configuration. The newconfiguration will then be saved for future uses.The first information to add is the netlist. Click on the ... button on the right of the VerilogFiles field. You get a new dialog window with only one pane. Click on the top-right icon toget the full window. Remove the VERILOG/none line in the left pane.Select the Verilog netlist file HDL/GATE/addsub_top_nbits8_mapped.v (or the Verilognetlist you want to place and route), add it to the left pane and close the window. It isassumed here that the imported netlist is the one generated for the 10 ns clock period.In the Design Import window, select the Auto Assign box to let the tool extract the topcell name from the file. If the Verilog file includes more than one design (more than one topmodule name), you need to give the name of the top module to use explicitly.In the Timing Constraint File Field:Select the file that has been generated during logic synthesis (4.6 Design mapping and opti-mization): SYN/SDC/addsub_top_nbits8_mapped.sdc Only timing information inthe constraint file is actually used by Encounter.In the IO Assignment File Field:Select the PAR/CONF/addsub_nbits8.io file

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In the Advanced tab select in the left pane the Power tag, you can keep only the VCCand GND power nets. The names of power and ground nets must be the same as the onesused in the LEF file that describes the standard cells.You can now save the updated configuration in the filePAR/CONF/addsub_nbits8.conf by clicking on the Save... button.Finally, click on OK. The configuration is then read in.To reload a configuration, select Design -> Design Import... in the main menu. Then,click on the Load... button and load the configuration file from the PAR/CONF directory.

5.3 Floorplan Specification

The floorplan defines the actual form, or aspect ratio, the layout will take, the global anddetailed routing grids, the rows to host the core cells and the I/O pad cells (if required), andthe location of the corner cells (if required).Select Floorplan -> Specify Floorplan... in the main menu.In order to be able to add PAD cells and IO cells we need to specify exact locations forDie/IO/Core so click this button and fill in the following coordinates:Die LL: 0.0 0.0 UR: 1133.72 1133.72IO LL: 219.8 219.8 UR: 913.92 913.92

Core LL: 303.8 303.8 UR: 829.92 829.92Click OK.If you want to change the coordinates you will need the metrics of the core , IO and padcells. These metrics are described in Appendix A.Now the gaps between the IO cells must be filled with IO-filler cells.Execute the fillperi.tcl script by the following command on the command line:encounter> source PAR/BIN/fillperi.tcl

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The display design area pane now shows the defined floorplan with the required number ofrows.

It is a good idea to save the design at that stage to allow restarting here quickly withoutneeding to redo all the previous steps.Select Design -> Save Design... in the main menu and save the current state in the filePAR/DB/addsub_top_nbits8-fplan.enc.The data are actually saved in the directory PAR/DB/addsub_top_nbits8-fplan.enc.dat.To restore design data, select Design -> Restore Design... in the main menu and selectthe .enc file to read in the PAR/DB directory.

5.4 Power ring/stripe creation and routing

This step generates the VCC and ground power rings around the core and optionally adds anumber of vertical and/or horizontal power stripes across the core. Stripes ensure a properpower distribution in large cores. They are not strictly required here as the design is small.Select Floorplan -> Power Planning -> Add Rings... in the main menu.The Net(s) field defines the number and the kinds of rings from the core. In our case, therewill be first a ground ring around the core and a VCC ring around the ground ring. The netnames should be consistent with the power net names in the cell LEF file.The ring configuration should define ring widths of 2.8 micron spaced by 1.12 micron.The rings will be placed in the center of the channel between the core and the chip boundary(or the IO pads, if any). Check the Center in channel box in the Ring Configuration part.It is possible to extend the ring segments to reach the core boundary.Click on the Advanced tab and click on the segments you’d like to extend.Other power and ground side trunks can be defined by selecting only horizontal or verticalsegments.Click OK to generate the rings.

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To add power stripes, select Floorplan -> Power Planning -> Add Stripes... in themain menu.

The Net(s) field defines the pattern. Here a single pattern will be generated (select Numberof sets and insert 1). Each stripe will be 2.8 micron wide and the space between them willbe 1.12 micron.Check Relative from core or selected area and enter the value 260 (micron) in the X fromleft field. The two stripes will be vertically placed near the center of the core.It is possible to measure sizes by using the ruler

(or hit the k binding key). Hit K to remove the last ruler or press ESC to remove all rulers.Click OK to generate the stripes. It is possible to remove the stripes by selecting them andhitting the Delete key.

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Additionally, the command Floorplan -> Clear Floorplan... allows you to delete all orparts of the floorplan objects.

5.5 Global net connections

This step assigns pins or nets to global power and ground nets. The imported Verilog netlistdoes not mention any power and ground connections. However, the cells that will be placeddo have power/ground pins that will need to be routed to the global power/ground netsdefined for the block.Select Floorplan -> Connect Global Nets... in the main menu.

The left pane (Connection List) is initially empty. For each VCC and ground net:Check the Pins field and enter the pin name (VCC or GND).Under Scope, select Apply All Fill the To Global Net field with either VCC or GND.Click on Add to List. The left pane now includes the related global net connection.Click on Apply and then on Close.Now, it is possible to route the power grid. Select Route -> SRoute... in the main menu.All default values are fine. Click OK to do the routing. The design now looks like below:It is recommended to save the new stage of the design. SelectDesign -> Save Design... inthe main menu and save the current state in the file PAR/DB/addsub_top_nbits8-pring.enc.

5.6 Operating conditions definition

The operating conditions define the temperature, process and voltage conditions for thedesign. They impact the timing calculations and optimizations.Select the Timing -> Analysis Condition -> Specify Operating Condition/PVT...in the main menu.

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In the max tab, select the WCCOM operating condition. In the min tab, select the BCCOMoperating condition.Click OK.The max operating conditions will be used to meet setup timing constraints, while the minoperating conditions will be used to meet hold timing constraints.The Encounter console summarizes the settings:

Set Min operating condition for timing library group ’min ’ to ’BCCOM ’defined in Timing Library ’fsd0a_a_generic_core_bc ’

Process: 1.00 Temperature: -40.000 Voltage: 1.100Set Max operating condition to ’WCCOM ’ defined in Timing Library ’fsd0a_a_generic_core_wc ’

Process: 1.00 Temperature: 125.000 Voltage: 0.900*** Calculating scaling factor for min libraries using operating condition:

Name: BCCOM Process: 1.00 Temperature: -40.000 Voltage: 1.100*** Calculating scaling factor for max libraries using operating condition:

Name: WCCOM Process: 1.00 Temperature: 125.000 Voltage: 0.900

Running the following command in the Encounter console gives the active operating condi-tions:

encounter 1> getOpCond -vmin: BCCOM proc: 1.0000 volt: 1.1000 temp: -40.0000max: WCCOM proc: 1.0000 volt: 0.9000 temp: 125.0000

5.7 Core cell placement

This step places the cells of the imported Verilog netlist in the rows.Select Place -> Standard Cells... in the main menu.By clicking the Mode button one can specify placement options. By default it will run inTiming Driven Placement Mode. Stick to the default options and click OK.The Timing Driven Placement Mode option will optimize the placement of the cellsthat are on the critical path. Some cell instances may be replaced with cells having lowerdriving capabilities (downsizing) or stronger driving capabilities (upsizing). Buffers may bealso added or deleted. The Encounter console notifies such changes.Click OK to do the placement. It may take some time to complete, especially when theplacement is timing driven and a high effort level is used .The placement should then look like below:

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It is recommended to save the new stage of the design. Select Design -> Save Design...in the main menu and save the current state in the file PAR/DB/addsub_top_nbits8-placed.enc.

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5.8 Post-placement timing analysis

The timing analysis engine in Encounter can now be run to get a relatively good idea ofthe timing performances of the design. It actually performs a trial routing and a parasiticextraction based on the current cell placement.Select Timing -> Analyze Timing... in the main menu. Define the path for the slackreport file. Click OK.In the Encounter console window you get a summary of the timing analysis:# generated on Thu May 7 11 :21 :43# Top Ce l l : addsub_top_NBITS8

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−t imeDesign Summary

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+| Setup mode | a l l | r eg2reg | i n2 r eg | reg2out | in2out | c l kga t e |+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+| WNS ( ns ) : | 4 .978 | 8 .455 | 5 .906 | 4 .978 | N/A | N/A || TNS ( ns ) : | 0 .000 | 0 .000 | 0 .000 | 0 .000 | N/A | N/A || V io l a t i ng Paths : | 0 | 0 | 0 | 0 | N/A | N/A || Al l Paths : | 56 | 8 | 47 | 8 | N/A | N/A |+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+

+−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+| | Real | Total || DRVs +−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−|| | Nr | Worst Vio | Nr |+−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−+| max_cap | 0 | 0 .000 | 0 || max_tran | 0 | 0 .000 | 0 || max_fanout | 0 | 0 | 0 |+−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−+

Dens i ty : 0 .254%Routing Over f low: 0 . 00% H and 0 .00% V−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

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The design is not critical as the slack is positive (4.978 ns).To get more details on the critical path, selectTiming -> Debug Timing... in the main menu.Another way to do a timing analysis is to execute the following commands in the Encounterconsole:encounter 16> reportTAThe following report is then displayed in the console:Path 1 : MET Late External Delay Asse r t i onEndpoint: z [ 7 ] (^) checked with l ead ing edge o f ’ c lk ’Beg inpo in t : addsub_1/z_reg_7_/Q (^) t r i g g e r e d by l ead ing edge o f ’ c lk ’Other End Arr i va l Time 0 .000− External Delay 2 .000+ Phase Sh i f t 10 .000= Required Time 8 .000− Arr i va l Time 3 .914= Slack Time 4 .086

Clock Rise Edge 0 .000= Beginpoint Ar r i va l Time 0 .000+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+| Ins tance | Arc | Ce l l | Delay | Ar r i va l | Required || | | | | Time | Time ||−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−+−−−−−−−−−−+−−−−−−−+−−−−−−−−−+−−−−−−−−−−|| | c l k ^ | | | 0 .000 | 4 .086 || io_clk /x0_ip | I ^ −> O ^ | UYNGB | 0 .696 | 0 .696 | 4 .782 || addsub_1/z_reg_7_ | CK ^ −> Q ^ | QDFFRBX1 | 0 .635 | 1 .331 | 5 .417 || io_z/x0_7/x0_op | I ^ −> O ^ | VYA4GSGB | 2 .583 | 3 .914 | 8 .000 || | z [ 7 ] ^ | | 0 .000 | 3 .914 | 8 .000 |+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+

5.9 Clock tree synthesis (optional)

As the paths that will propagate the clock signal in the design are not necessarily balanced,some registers may receive the active clock edge later than others (clock skew) and maytherefore violate the assumed synchronous design operation. For example, the original clocktree we can get from the previously placed design is shown below.

To create a balanced clock tree, you have first to create a clock tree specification file. En-counter can create a first draft version of the file you can then edit to include design specificdata.

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SelectClock -> Design Clock... in the main menu. In the Synthesize Clock Tree popupmenu change the Results Directory to PAR/CTS and click on the Gen Spec... button toget the Genererate Clock Spec menu. Select the BUFCKX* and INVCK* cells forfootprints and save the specification in the file PAR/CTS/addsub_top_nbits8-spec.cts.

Click OK to generate the specification file. You can then edit the file to change timingvalues such as the maximum allowed clock skew (300ps by default).The next step is to load the clock tree specification file.SelectClock -> Specify Clock Tree ... in the main menu and select the file PAR/CTS/addsub_nbits8-spec.cts that has been previously created (and possibly edited).To create the clock tree, selectClock -> Synthesize Clock Tree ... in the main menu.Define the result directory as PAR/CTS and the base file name as addsub_nbits8_cts.Click OK to create the clock tree.To display the generated clock tree, select

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Clock -> Display -> Display Clock Tree ... in the main menu.

The clock paths have been balanced according to the clock tree specifications.

To get a report on the clock tree synthesis, enter the following command at the encounterprompt.

encounter 1> reportClockTree -report PAR/RPT/addsub_top_nbits8.ctsrpt

The following report is also displayed in the Encounter console:

Redoing spec i fyClockTree − c l k f i l e PAR/CTS/addsub_nbits8−spec.cts . . .

reportClockTree Option :∗∗∗ Look For Reconvergent Clock Component ∗∗∗The clock t r e e c l k has no reconvergent c e l l .

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## Mode : Setup# Library Name : fod0a_b25_t25_generic_io_ss0p9v125c# Operating Condit ion : fod0a_b25_t25_generic_io_ss0p9v125c/%NOM_PVT# Process : 1# Vol tage : 0 .9# Temperature : 125#∗∗∗∗∗∗∗∗∗∗ Clock c l k Pre−Route Timing Ana lys i s ∗∗∗∗∗∗∗∗∗∗Nr. o f Subtrees : 2Nr. o f S inks : 24Nr. o f Buf f e r : 0Nr. o f Leve l ( i n c l ud ing gate s ) : 1Root Rise Input Tran : 0 . 1 ( ps )Root Fa l l Input Tran : 0 . 1 ( ps )Max t r i g . edge de lay at s ink (R) : addsub_1/z_reg_0_/CK 770 . 4 ( ps )Min t r i g . edge de lay at s ink (R) : addsub_1/a_reg_reg_2_/CK 768( ps )

( Actual ) ( Required )Rise Phase Delay : 768~770 . 4 ( ps ) 0~10000( ps )Fa l l Phase Delay : 564 . 4 ~566 . 8 ( ps ) 0~10000( ps )Tr i g . Edge Skew : 2 . 4 ( ps ) 300( ps )Rise Skew : 2 . 4 ( ps )Fa l l Skew : 2 . 4 ( ps )Max. Rise Buf f e r Tran. : 31( ps ) 400( ps )Max. Fa l l Buf f e r Tran. : 31( ps ) 400( ps )Max. Rise Sink Tran. : 101 . 1 ( ps ) 400( ps )Max. Fa l l Sink Tran. : 85 . 6 ( ps ) 400( ps )Min. Rise Buf f e r Tran. : 31( ps ) 0( ps )Min. Fa l l Bu f f e r Tran. : 31( ps ) 0( ps )Min. Rise Sink Tran. : 101( ps ) 0( ps )Min. Fa l l Sink Tran. : 85 . 6 ( ps ) 0( ps )

Generating Clock Ana lys i s Report addsub_top_NBITS8.ctsrpt . . . .Clock Ana lys i s (CPU Time 0 : 0 0 : 0 0 . 0 )

∗∗∗ End reportClockTree ( cpu=0 :00 :00 .0 , r e a l=0 : 0 0 : 0 0 . 0 , mem=347.5M) ∗∗∗

Several clock report files are also available in the PAR/CTS directory.

It is recommended to save the new stage of the design. SelectDesign -> Save Design... inthe main menu and save the current state in the file PAR/DB/addsub_top_nbits8-cts.enc.

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5.10 Design routing

This steps generates all the wires required to connect the cells according to the importedgate-level netlist.

To route the design, selectRoute -> Nanoroute... in the main menu, check the TimingDriven box and a maximum effort.Click OK to do the routing.You now get the routed design:

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It is recommended to save the new stage of the design. Select Design -> Save Design...in the main menu and save the current state in the filePAR/DB/addsub_top_nbits8-routed.enc.

5.11 Post-routing timing optimization and analysis

A final timing optimization may be done on the routed design. SelectTiming -> Optimize... in the main menu. Select the postRoute box.Click OK.

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The results of the optimization is displayed in the Encounter console:

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−I n i t i a l Summary

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+| Setup mode | a l l |+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+| WNS ( ns ) : | 4 .086 || TNS ( ns ) : | 0 .000 || V i o l a t i ng Paths : | 0 || A l l Paths : | 56 |+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+

+−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+| | Real | Total || DRVs +−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−|| | Nr | Worst Vio | Nr |+−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−+| max_cap | 0 | 0 .000 | 0 || max_tran | 0 | 0 .000 | 0 || max_fanout | 0 | 0 | 0 |+−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−+

Dens i ty : 0 .254%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−∗∗optDesign . . . cpu = 0 : 0 0 : 0 0 , r e a l = 0 : 0 0 : 0 0 , mem = 349.6M ∗∗∗∗∗ Timing I s met∗∗∗ Check timing (0 : 0 0 : 0 0 . 0 )∗∗∗ Setup timing i s met ( t a r g e t s l a ck 0 . 0n s )Reported t iming to d i r . / t imingReports∗∗optDesign . . . cpu = 0 : 0 0 : 0 0 , r e a l = 0 : 0 0 : 0 0 , mem = 349.6M ∗∗

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−optDesign Fina l Summary

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+| Setup mode | a l l | r eg2reg | i n2 r eg | reg2out | in2out | c l kga t e |+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+| WNS ( ns ) : | 4 .086 | 8 .426 | 6 .669 | 4 .086 | N/A |N/A || TNS ( ns ) : | 0 .000 | 0 .000 | 0 .000 | 0 .000 | N/A |N/A || V io l a t i ng Paths : | 0 | 0 | 0 | 0 | N/A |N/A |

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| A l l Paths : | 56 | 8 | 47 | 8 | N/A |N/A |+−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+−−−−−−−−−+

+−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−+| | Real | Total || DRVs +−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−|| | Nr | Worst Vio | Nr |+−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−+| max_cap | 0 | 0 .000 | 0 || max_tran | 0 | 0 .000 | 0 || max_fanout | 0 | 0 | 0 |+−−−−−−−−−−−−−−−−+−−−−−−−−−+−−−−−−−−−−−−+−−−−−−−−−+

Dens i ty : 0 .254%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−∗∗optDesign . . . cpu = 0 : 0 0 : 0 1 , r e a l = 0 : 0 0 : 0 0 , mem = 349.6M ∗∗−core {} # s t r i n g , de fau l t= ""∗∗∗ Fin i shed optDesign ∗∗∗

5.12 Filler cell placement

Filler cells will fill remaining holes in the rows and ensure the continuity of power/groundrails and N+/P+ wells in the rows. To fill the holes with filler cells, select Place -> Filler-> Add Filler... in the main menu.Select the cells FILLER64E, FILLER32E, FILLER16E, FILLER8E, FILLER4E, FILLER3,FILLER2 and FILLER1 and click OK to place the filler cells.

5.13 Design checks

The Verify menu has a number of items to check that the design has been properly placedand routed.Select Verify -> Verify Connectivity... in the main menu. Define the report file asPAR/RPT/addsub_top_nbits8-conn.rpt.

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Click OK.The console displays the results:

∗∗∗∗∗∗∗∗ S t a r t : VERIFY CONNECTIVITY ∗∗∗∗∗∗∗∗

Star t Time: Thu Dec 1 18 : 5 2 : 0 0 2005Design Name: addsub{\_}NBITS8Database Un i t s : 1000Design Boundary: (0 . 0 0 0 0 , 0 .0000 ) (153 . 0 5 0 0 , 136 .9000 )Error Limit = 1000 ; Warning Limit = 50Check a l l net sBegin SummaryFound no problems or warn ings .End SummaryEnd Time: Thu Dec 1 18 : 5 2 : 0 0 2005

∗∗∗∗∗∗∗∗ End: VERIFY CONNECTIVITY ∗∗∗∗∗∗∗∗

Ve r i f i c a t i o n Complete : 0 V i o l s . 0 Wrngs.

Select Verify -> Verify Geometry... in the main menu. In the Advanced tab, definethe report file asPAR/RPT/addsub_nbits8-geom.rpt.Click OK.

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The console displays the results:

∗∗∗ Sta r t i ng Ver i f y Geometry (MEM: 222 . 2 )VERIFY GEOMETRY . . . . . . S t a r t i ng V e r i f i c a t i o nVERIFY GEOMETRY . . . . . . I n i t i a l i z i n gVERIFY GEOMETRY . . . . . . De l e t ing Ex i s t ing V i o l a t i on sVERIFY GEOMETRY . . . . . . Creat ing Sub−AreasVERIFY GEOMETRY . . . . . . SubArea : 1 o f 1VERIFY GEOMETRY . . . . . . C e l l s : 0 V i o l s .VERIFY GEOMETRY . . . . . . SameNet : 0 V i o l s .VERIFY GEOMETRY . . . . . . Wiring : 0 V i o l s .VERIFY GEOMETRY . . . . . . Antenna : 0 V i o l s .VERIFY GEOMETRY . . . . . . Sub−Area: 1complete 0 V i o l s . 0 Wrngs.Begin Summary . . .C e l l s : 0SameNet : 0Wiring : 0Antenna : 0Short : 0Overlap : 0End Summary

Ve r i f i c a t i o n Complete : 0 V i o l s . 0 Wrngs.

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5.14 Report generation

A number of reports have been already generated in the previous steps. They should belocated in the PAR/RPT directory. The Tools menu includes some additional reports:Design -> Report-> Netlist Statistics gives the following output in the console:

encounter 2> ∗∗∗ S t a t i s t i c s for net l i s t addsub_top_NBITS8 ∗∗∗Number o f c e l l s = 338Number o f nets = 166Number o f t r i−net s = 8Number o f degen nets = 0Number o f p ins = 466Number o f i / os = 27

Number o f nets with 2 terms = 114 (68 . 7%)Number o f nets with 3 terms = 21 (12 . 7%)Number o f nets with 4 terms = 28 (16 . 9%)Number o f nets with >=10 terms = 3 (1 . 8%)

∗∗∗ 21 Pr im i t i v e s used :Pr imi t ive VCCKGB (1 i n s t s )Pr imi t ive GNDKGB (1 i n s t s )Pr imi t ive VCC2IOGB (5 i n s t s )Pr imi t ive GND2IOGB (6 i n s t s )Pr imi t ive EMPTY1GB (44 i n s t s )Pr imi t ive CORNERGB (4 i n s t s )Pr imi t ive EMPTY16GB (44 i n s t s )Pr imi t ive EMPTY8GB (44 i n s t s )Pr imi t ive EMPTY4GB (44 i n s t s )Pr imi t ive VYA4GSGB (8 i n s t s )Pr imi t ive UYNGB (19 i n s t s )Pr imi t ive QDFFRBX1 (24 i n s t s )Pr imi t ive XOR2X1 (5 i n s t s )Pr imi t ive TIE1X1 (27 i n s t s )Pr imi t ive TIE0X1 (27 i n s t s )Pr imi t ive MXL2XLP (13 i n s t s )Pr imi t ive MUX2X1 (1 i n s t s )Pr imi t ive MAO222X1 (4 i n s t s )Pr imi t ive INVX1 (2 i n s t s )Pr imi t ive INVCKX1 (13 i n s t s )Pr imi t ive FA1X1 (2 i n s t s )∗∗∗∗∗∗∗∗∗∗∗∗

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Design -> Report -> Gate Count... gives the following output in the console:

Gate area 2 .3520 um^2[ 0 ] addsub_top_NBITS8 Gates=297 Cells=118 Area=698.5 um^2

Finally, Design -> Report -> Summary... displays the following window:

summaryReport −outdir summaryReportCreat ing d i r e c t o r y summaryReport.S ta r t to c o l l e c t the des ign i n f o rmat i on .Bui ld n e t l i s t in fo rmat ion for Ce l l addsub_top_NBITS8.F in i sh to c o l l e c t the des ign in f o rmat i on .Generating standard c e l l s used in the des ign r e p o r t .Generating IO c e l l s used in the des ign r e p o r t .Analyze l ibrary . . .Analyze n e t l i s t . . .Analyze t iming . . .Analyze f l o o r p l a n /placement . . .Ana lys i s Routing . . .Report saved in f i l e summaryReport/addsub_top_NBITS8.main.htm.ascii .

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5.15 Post-route timing data extraction

This step generates the post-route SDF file that includes both the actual interconnect andcell timing delays.

The parasitics must be first extracted.Select Timing -> Extract RC... in the main menu.The generated Cap file includes the wired capacitance, pin capacitance, total capacitance,net length, wire cap per unit length and the fanout of each net in the design. The generatedSPEF (Standard Parasitics Exchange Format) file includes RC values in a SPICE-like format.

The SDF file may be then generated by selectingTiming -> Calculate Delay... in the main menu. The checked Ideal Clock switch meansthat flip-flops are considered as having 0ps rising and falling transition times.

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5.16 Post-route netlist generation

This steps generates a Verilog netlist of the routed design. The netlist may be different fromthe imported netlist as cells may have been added or replaced during clock tree synthesisand timing-driven optimizations.

Select Design -> Save -> Netlist... in the main menu. Do not select Include Leaf CellDefinition as they are provided in a separate library.The generated file should go into the HDL/GATE directory.

5.17 GDS2 file generation

The placed and routed design can be exported in different formats for further processingoutside the Encounter tool. The GDS2 binary format is a standard format for integratingthe block in the top-level layout, doing DRC/LVS checkings, or delivering the layout to thefoundry. To export the design in the GDS2 format, select Design -> Save -> GDS...in the main menu. The GDS map file has been copied by the tech_setup script in thePAR/DEX directory. The generated GDS2 file is written in the same directory.

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5.18 Using scripts

As for the synthesis step, it is much more convenient to capture the placement and routingflow in a script. Cadence Encounter also support sthe Tcl language for building scripts.An example of such a script for placement and routing of the adder-subtractor design hasbeen installed in the PAR/BIN directory (see “2.5 VHDL example: Adder-subtractor”). Thescript must be run from the project top directory and it assumes a directory organization asdescribed in “2.2 Design project organisation”. To run the Tcl script, execute the followingcommand in a Unix shell:

encounter -log PAR/LOG/encounter -overwrite -init PAR/BIN/addsub_par.tcl -win

The script is given below. It may be modified to define design information and to controlthe flow to some extent. Note that a configuration file must exist before running the script.The configuration file name is in the PAR/CONF directory and its name is defined in thescript.The script does a bit more than the steps described earlier. For example, it uses an I/O pinplacement definition as provided by a PAR/CONF/*.io file.

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## Cadence Encounter Tcl script for adder− sub t rac tor .## Proces s : Faraday 90nm CMOS (1P9M)##−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# I t i s assumed t ha t a p r o j e c t d i r e c t o r y s t r u c t u r e has a l r eady been# crea t ed us ing ’ crea te_pro jec t ’ and t ha t t h i s s y n t h e s i s script i s# execu ted from the p r o j e c t roo t d i r e c t o r y $PROJECT_DIR#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set PROJECT_DIR [pwd ]#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Design r e l a t e d in format ion ( can be changed )#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set DESIGN addsub_nbits8set TIM_LIBRARY fsd0a_a_generic_coreset TIM_OC_MAX WCCOM ;# TYPICAL | WORST | WORST−INDset TIM_OC_MIN BCCOM ;# TYPICAL | BEST | BEST−IND# Floorp lan s e t t i n g s#set FP_ASPECT_RATIO 1set FP_ROW_DENSITY 0 .85 ;# percentset FP_CORE2IO 21 ;# micron# Power r ing and s e t t i n g s#set PR_WIDTH 2 .8 ;# micronset PR_SPACING 1 .68 ;# micronset PR_LAYER_TB METAL9 ;# top and bottom l a y e rset PR_LAYER_LR METAL8 ;# l e f t and r i g h t l a y e r# Power s t r i p e s e t t i n g s#set ST_NUM_SETS 1 ;# number o f s e t sset ST_SPACING 1 ;# micronset ST_LAYER_V $PR_LAYER_LRset ST_WIDTH 1 .4 ;# micronset ST_XOFS_R 12 ;# micronset ST_XOFS_L 0 ;# micron# Placement s e t t i n g s#set PL_EFFORT −highEf fort ;# −low | −medium | −high# Clock t r e e s yn t h e s i s s e t t i n g s#set CTS_BUFFER BUFCKX1 BUFCKX2 BUFCKX1P BUFCKX12 BUFCKX16 BUFCKX20set CTS_INV INVCKX1 INVCKX2 INVCKX1P INVCKX12 INVCKX16 INVCKX20 INVCKX3 INVCKX4 INVCKX6 INVCKX8#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Flags t ha t d r i v e the script behav ior ( can be changed )

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## ADD_STRIPES (0 | 1)# i f 1 , add s t r i p e s# PLACE_TIMING (0 | 1)# i f 1 , do a t iming dr i ven placement# CLOCK_TREE (0 | 1)# i f 1 , c r ea t e a clock t r e e# CTS_CREATE_SPEC (0 | 1)# i f 1 , c r ea t e a clock t r e e s p e c i f i c a t i o n f i l e with default va l u e s# ROUTE_TIMING (0 | 1)# i f 1 , do a t iming dr i ven rou t ing# OPT ( string )# can be used to have d i f f e r e n t genera ted f i l e names#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set ADD_STRIPES 1set PLACE_TIMING 1set CLOCK_TREE 1set CTS_CREATE_SPEC 0set ROUTE_TIMING 1set OPT "_cts"#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Fi l e names#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set CONF_FILE_NAME ${DESIGN} . c on fset IO_FILE_NAME ${DESIGN} . i oset DESIGN_NAME ${DESIGN}${OPT}set SAVE_DESIGN_FP_NAME ${DESIGN_NAME}− fp lan .encset SAVE_DESIGN_PR_NAME ${DESIGN_NAME}−pring.encset SAVE_DESIGN_PL_NAME ${DESIGN_NAME}−placed.encset SAVE_DESIGN_PF_NAME ${DESIGN_NAME}−p la c ed_f i l l ed . encset SAVE_DESIGN_CT_NAME ${DESIGN_NAME}−cts . encset SAVE_DESIGN_RO_NAME ${DESIGN_NAME}−routed.encset TIM_RCDB_NAME ${DESIGN_NAME} . rcdbset SDF_FILE_NAME ${DESIGN_NAME}− routed . sd fset SPEF_FILE_NAME ${DESIGN_NAME}− routed . spe fset RPT_CHECK_TA_NAME ${DESIGN_NAME}−checkta . rptset RPT_REPORT_TA_NAME ${DESIGN_NAME}−ta . rptset RPT_SLACK_NAME ${DESIGN_NAME}− s l a ck . rp tset RPT_GATE_COUNT_NAME ${DESIGN_NAME}−gate_count.rptset RPT_NOTCH_NAME ${DESIGN_NAME}−notch.rptset RPT_CONN_NAME ${DESIGN_NAME}−conn.rptset RPT_GEOM_NAME ${DESIGN_NAME}−geom.rptset RPT_DENSITY_NAME ${DESIGN_NAME}−dens i ty . rptset VLOG_NETLIST_SIM_NAME ${DESIGN_NAME}−routed.vset VLOG_NETLIST_LVS_NAME ${DESIGN_NAME}−routed_lvs.vset CTS_SPEC_NAME ${DESIGN_NAME}− spec . c t s

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set CTS_RGUIDE_NAME ${DESIGN_NAME}−gu ide . c t sset CTS_RPT_NAME ${DESIGN_NAME}−c t s . rp tset GDS_FILE_NAME ${DESIGN_NAME} .gds#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Abso lu te paths#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−set CONF_FILE ${PROJECT_DIR}/PAR/CONF/${CONF_FILE_NAME}set IO_FILE ${PROJECT_DIR}/PAR/CONF/${IO_FILE_NAME}set SAVE_DESIGN_FP_FILE ${PROJECT_DIR}/PAR/DB/${SAVE_DESIGN_FP_NAME}set SAVE_DESIGN_PR_FILE ${PROJECT_DIR}/PAR/DB/${SAVE_DESIGN_PR_NAME}set SAVE_DESIGN_PL_FILE ${PROJECT_DIR}/PAR/DB/${SAVE_DESIGN_PL_NAME}set SAVE_DESIGN_PF_FILE ${PROJECT_DIR}/PAR/DB/${SAVE_DESIGN_PF_NAME}set SAVE_DESIGN_CT_FILE ${PROJECT_DIR}/PAR/DB/${SAVE_DESIGN_CT_NAME}set SAVE_DESIGN_RO_FILE ${PROJECT_DIR}/PAR/DB/${SAVE_DESIGN_RO_NAME}set SDF_FILE ${PROJECT_DIR}/PAR/TIM/${SDF_FILE_NAME}set SPEF_FILE ${PROJECT_DIR}/PAR/TIM/${SPEF_FILE_NAME}set TIM_RCDB_FILE ${PROJECT_DIR}/PAR/TIM/${TIM_RCDB_NAME}set RPT_CHECK_TA_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_CHECK_TA_NAME}set RPT_REPORT_TA_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_REPORT_TA_NAME}set RPT_SLACK_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_SLACK_NAME}set RPT_GATE_COUNT_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_GATE_COUNT_NAME}set RPT_NOTCH_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_NOTCH_NAME}set RPT_CONN_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_CONN_NAME}set RPT_GEOM_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_GEOM_NAME}set RPT_DENSITY_FILE ${PROJECT_DIR}/PAR/RPT/${RPT_DENSITY_NAME}set VLOG_NETLIST_SIM_FILE ${PROJECT_DIR}/HDL/GATE/${VLOG_NETLIST_SIM_NAME}set VLOG_NETLIST_LVS_FILE ${PROJECT_DIR}/HDL/GATE/${VLOG_NETLIST_LVS_NAME}set CTS_SPEC_FILE ${PROJECT_DIR}/PAR/CTS/${CTS_SPEC_NAME}set CTS_RGUIDE_FILE ${PROJECT_DIR}/PAR/CTS/${CTS_RGUIDE_NAME}set CTS_RPT_FILE ${PROJECT_DIR}/PAR/RPT/${CTS_RPT_NAME}set GDS_FILE ${PROJECT_DIR}/PAR/DEX/${GDS_FILE_NAME}set GDS_MAP_FILE ${PROJECT_DIR}/PAR/DEX/gds2.map#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Procedures#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# make_clock_tree#proc make_clock_tree create_spec {global CTS_BUFFER CTS_INV CTS_SPEC_FILE CTS_RGUIDE_FILE CTS_RPT_FILEi f { $create_spec | | ! [ f i l e exists $CTS_SPEC_FILE] } {createClockTreeSpec \−bufFootprint $CTS_BUFFER \− invFootprint $CTS_INV \−output $CTS_SPEC_FILE}spec i fyC lockTree − c l k f i l e $CTS_SPEC_FILE

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ckSynthes i s \−rguide $CTS_RGUIDE_FILE \−report $CTS_RPT_FILEoptDesign −postCTS −setup −drv −outDir PAR/RPT} ;# make_clock_tree#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Load con f i g u r a t i on f i l e#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−l oadConf ig $CONF_FILE 0commitConfig#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Load IO f i l e#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−l o ad I oF i l e $IO_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Set opera t ing cond i t i on s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−setOpCond \−maxLibrary $TIM_LIBRARY −max $TIM_OC_MAX \−minLibrary $TIM_LIBRARY −min $TIM_OC_MIN#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Set user g r i d s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−s e tP r e f e r en c e ConstraintUserXGrid 0 . 1s e tP r e f e r en c e Constra intUserXOffset 0 . 1s e tP r e f e r en c e ConstraintUserYGrid 0 . 1s e tP r e f e r en c e Constra intUserYOffset 0 . 1s e tP r e f e r en c e SnapAllCorners 1s e tP r e f e r en c e BlockSnapRule 2#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Define global Power ne t s − make global connec t ions#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−c l ea rGloba lNet sglobalNetConnect VCC −type pgpin −pin VCC − inst ∗ −module {} −verboseglobalNetConnect GND −type pgpin −pin GND − inst ∗ −module {} −verbose#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# I n i t i a l i z e f l o o r p l a n#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−f l o o rP l an −r $FP_ASPECT_RATIO \$FP_ROW_DENSITY \$FP_CORE2IO $FP_CORE2IO $FP_CORE2IO $FP_CORE2IOf i tsaveDesign $SAVE_DESIGN_FP_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Add CAP c e l l s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

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#addEndCap −preCap ENDCAPL −postCap ENDCAPR −pre f ix ENDCAP#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Create and route power r i n g s and power s t r i p e s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−addRing \−around core \−nets { GND VCC } \−width_bottom $PR_WIDTH −width_top $PR_WIDTH \−width_left $PR_WIDTH −width_right $PR_WIDTH \−spacing_bottom $PR_SPACING −spacing_top $PR_SPACING \−spac ing_le ft $PR_SPACING −spacing_right $PR_SPACING \−layer_bottom $PR_LAYER_TB −layer_top $PR_LAYER_TB \− l ayer_le f t $PR_LAYER_LR − layer_right $PR_LAYER_LR \−center 1 \−tl 1 −tr 1 −bl 1 −br 1 − lt 1 −lb 1 −rt 1 −rb 1 \−stacked_via_bottom_layer MET1 −stacked_via_top_layer MET9 \−threshold 0 . 7i f { $ADD_STRIPES } {addStr ipe \−nets { GND VCC } \−number_of_sets $ST_NUM_SETS \−spacing $ST_SPACING \− layer $ST_LAYER_V \−width $ST_WIDTH \−x l e f t_o f f s e t $ST_XOFS_L}s route \− jogControl { preferWithChanges d i f f e r e n tLay e r } \−nets { GND VCC }saveDesign $SAVE_DESIGN_PR_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Core c e l l p lacement#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−i f { $PLACE_TIMING } {setPlaceMode $PL_EFFORT −t imingdriven −doCongOpt − ignoreScan − ignoreSparep laceDes ign} else {setPlaceMode $PL_EFFORT −doCongOpt − ignoreScan − ignoreSparep laceDes ign}setDrawMode p lacesaveDesign $SAVE_DESIGN_PL_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Create clock t r e e ( op t i ona l )#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−i f { $CLOCK_TREE } {

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make_clock_tree $CTS_CREATE_SPECsaveDesign $SAVE_DESIGN_CT_FILE}#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Add f i l l e r c e l l s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−addF i l l e r −ce l l FILL25 FILL10 FILL5 FILL2 FILL1 −pre f ix FILLERsaveDesign $SAVE_DESIGN_PF_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Route des i gn (Nanoroute )#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−i f { $ROUTE_TIMING } {setNanoRouteMode −quiet −timingEngine CTEsetNanoRouteMode −quiet −routeWithTimingDriven truesetNanoRouteMode −quiet −routeTdrEffort 0}g loba lDeta i lRouteoptDesign −postRoute −setup −drv −outDir PAR/RPTsaveDesign $SAVE_DESIGN_RO_FILEsetDrawMode p lace#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Ver i f i c a t i o n s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−f i l l N o t c h −report $RPT_NOTCH_FILEve r i f yConne c t i v i t y \−type a l l \−error 1000 \−warning 50 \−report $RPT_CONN_FILEveri fyGeometry \−al lowSameCel lViols \−allowRoutingBlkgPinOverlap \−al lowRoutingCel lBlkgOverlap \−report $RPT_GEOM_FILEver i fyMeta lDens i ty \−deta i l ed \−report $RPT_DENSITY_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Extrac t p a r a s i t i c s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−setExtractRCMode \−deta i l \−rcdb $TIM_RCDB_FILE \−relative_c_t 0 .01 \−total_c_t 5 . 0 \−reduce 5

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extractRC#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Generate RC and t iming f i l e s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−rcOut −spef $SPEF_FILEdelayCal −sdf $SDF_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Generate r epo r t s#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−reportGateCount −ou t f i l e $RPT_GATE_COUNT_FILE# Timings#setCteReportsetAnalysisMode −setup −async −skew −noClockTree −sequentialConstPropreportAnalys isModebuildTimingGraphcheckTA −verbose > $RPT_CHECK_TA_FILEreportTA \−format { hpin arc c e l l de lay a r r i v a l r equ i r ed s lew fanout load } \− late \−max_points 10 \−net \> $RPT_REPORT_TA_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Save n e t l i s t#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−s a v eNe t l i s t −exc ludeLeafCel l $VLOG_NETLIST_SIM_FILEsav eNe t l i s t −physical $VLOG_NETLIST_LVS_FILE#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−# Save GDS2#−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−streamOut $GDS_FILE \−mapFile $GDS_MAP_FILE \−libName ADDSUB \−structureName $DESIGN_NAME \− s t r ipe s $ST_NUM_SETS \−units 1000 \−mode ALL

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6 Appendix A: Design MetricsA design begins with the planning of the die. The mini@sic program from EuroPracticeis a multiproject wafer where a minimum area of 1875 x 1875 um2 is required. This areaconstraint is the startpoint for planning the whole chip. Another important issue is the celllibrary metrics. The metrics of Faraday L90_SP library are:

Description Width Height

Grid 0.28 um 0.28 umCore Cell x * 0.28 um 2.8 umIO Cell 60.48 um 142.8 umCorner Cell 142.8 um 142.8 umPad Cell 64 um 77 um

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