IEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, December 1982TOTAL DOSE RESPONSE OF STL AND F2L LOGIC DEVICES
F. W. Poblenz. R.G. Carroll, D.A. Whitmire, B.W. Cheney, and D.L. WalthallTexas Instruments Incorporated, P.O. Box 226015,
Dallas, Texas 75266
ABSTRACT
Total dose effects on nine STL and IFL LSI commercialcircuits are discussed. The devices were developed to performGlobal Positioning System (GPS) functions. The IFL devicesshowed some radiation sensitivity in output load voltage (VOL) athigh output load currents but were functional at lower output cur-rents to the maximum test level of 1 X 106 rad (Si). STL deviceswere relatively unaffected by the radiation. A diagnostic use oftotal dose testing is discussed. The test results of a hardened rede-sign of one of the circuits are shown.
INTRODUCTION
Nine LSI circuits developed for a Global Positioning System(GPS) receiver application were characterized for total doseresponse. The circuits represent recent developments at TexasInstruments in both Schottky transistor logic (STL) andoxide-separated integrated injection logic (F1L). STL is similar toFL; however, the basic NPN transistor is operated in the normalmode and current is applied to the gate through a resistor con-nected to a voltage supply. The basic STL structure consists of asingle-input NPN inverter with multiple outputs isolated bySchottky contacts and a collector base Schottky clamp to keep thedevice out of hard saturation. Table I summarizes some of thecharacteristics of these devices.
The nine circuits were irradiated under bias in the TexasInstruments gamma facility. Parametric electrical tests wereperformed on the Advanced Component Tester (ACT) V within30 minutes after removing the circuits from the gammacell. Theradiation response of the circuits was characterized by measuringdc and ac parameters and functional test patterns. The circuitswere electrically measured at seven levels between 12.5 krad (Si)and 1 Mrad (Si).
PROCESS AND CIRCUIT DESCRIPTION
12L PROCESS
The cross section of the advanced oxide-separated IFLprocess is shown in Figure 1 along with a schematic representationofthe typical IFL structure. That structure consists of a lateral PNPtransistor merged into a vertical NPN structure.'
Function
Clock
BasebandCode Timer
STL701
STL703Interrupt Handler SBP 96301CAOS
DOACPredetectP-CodeCode Setter
To produce this structure and its associated interconnect, 11mask levels are used, starting with the mask defining the epitaxialareas that are to be isolated by an oxide from each other. A P+diffusion is then patterned and performed to create the collectorand emitter regions of the lateral PNP region. The PNP emitter isalso the extrinsic base area of the vertical NPN. To create theNPN intrinsic base region, a masking step for a P- ion implanta-tion is done before the implantation. Two N diffusions, one forthe NPN collectors and another for resistor components, arerequired.
At this point in the processing, the wafers may be stored, ifthey are gate array components, and inventoried until the inter-connect masks for the gate array application are available. Custom(dedicated) circuits, which are unique layouts of semiconductorcomponents and interconnect patterns, in general experience nointerruption of process flow.
The interconnect system for both types of componentsconsists of two levels of metal separated by a deposited silicondioxide layer. Additional masks are required for contacts, vias(connections between the metal layers), and passivation openings.The six IFL devices described in the following section were fabri-cated using the same process and are designed to be TTL compat-ible at the inputs and outputs.
P2L GATE ARRAYS
There are currently two IFL gate array base bars in full pro-duction status: the SBP 963xx (1400 gates) and the SBP 962xx(2600 gates). (Newer versions of these devices using radiationhardened design features are being characterized.) These arrayscan be routed "automatically" by using TI-generated software. Be-low is a brief discussion of the function of each integrated circuit.SBP 96301 Interrupt Handler Circuit. This device performs a ge-
neric interrupt control function for the SBP 9989 microprocessor.Fifteen interrupt lines are sampled on a clock edge and thenmasked and encoded into a 4-bit vector plus an interrupt requestline. These outputs are fed to the corresponding inputs of themicroprocessor. The device has several operating modes, includ-ing a processor-controlled test function, a communication registerunit (CRU) interface, addressable mask register and anaddressable interrupt acknowledge mode.
SBP 96303 Clear Acquisition Output Select (CAOS) 2 MHz. TheCAOS circuit decodes one of 37 possible addresses and-, based on
Design
370 STL7XX GA450 STL7XX GA520 STL7XX GA700 Small GA902 Small GA1980 Large GA2002 Large GA1597 Dedicated
that address, generates a coded output referred to as "clear acqui-sition" code. This code is generated from a 10-bit pseudorandomnumber generator. The device also stores other channel selectioninformation and produces synchronization pulses for otherdevices that must use these codes.
SBP 96203 Predetection Circuit (PDC). The PDC processes digitalinformation from an analog-to-digital converter relating toin-phase and quadrature input signals from two correlator chan-nels. This data is accumulated over a processor-determined timeinterval. Also, a noise sample is derived from the absolute valueof one of the input signals. The PDC is also capable of removinglow-frequency data and modulation signals from the sampledinputs. The PDC generates a "data ready" interrupt to the proces-sor at the end of the sample interval.
SBP 96202 Digital Oscillator/Accumulator Circuit (DOAC). This de-vice performs data manipulations for a digital phase-locked loopsystem. Specifically, it takes data representing a frequency fromthe processor and generates data representing the phase. This isaccomplished by accumulating the 32-bit frequency word at aspecified clock rate. The circuit consists of a 32-bit accumulator,several 32-bit registers, and control circuitry.
PL CUSTOM CIRCUITS
SN58221 P-Code Generator. The precision code (P-code) genera-tor uses four pseudorandom generators to produce the P-code.
COLLECTOR
Using modulo 2 summed shift register sequences, the device gen-erates a random number stream that takes one full week to com-plete a cycle at a clock frequency of 10.23 MHz.
SN58225 Code Setter Circuit. The code setter circuit (CSC) acceptstiming code from the processor and, based on this data, generatesseven alignment pulse outputs. Three of the pulses are used toalign the CA-code generator on CAOS and four pulses are used toalign the P-code generator on the P-code circuit.
STL PROCESS
Schottky transistor logic2 is generic diode transistor logicimplemented with Schottky logic diodes and a Schottky-clampedNPN transistor. Figure 2 shows a three-output STL gate circuitand a cross section of the device. For nominal conditions, thevoltage swing between the gates can be shown to be the differencebetween the forward voltages ofthe Schottky diode clamp and theSchottky diode merged in the collector of the NPN.Delta V = VH - VL = Vbe - VF (logic diode) - v,e
vbe = vf(clamp diode) + Vce
Delta v = vfcd+ VeV-vfld- ve = vfd vfld
(1)(2)(3)
The process used to implement the STL 7XX gate arraydevices is a standard buried collector, oxide-isolated bipolar pro-cess with a minimum feature size of 3.8 micrometers. The activejunctions are formed using ion implantation. The N-EPI thickness
COLLECTORS OXIDEV _
12L GATE
NPN NPN NPN PNP
N+ SUBSTRATE
Figure 1. Oxide-Separated P2L Gate and Equivalent Circuit
TOTRANSISTOR
BASE
N+
-a-n X
PtSiSCHOTTKY CLAMP TiW
DIODE BASE CONTACT COLLECTOREMITTER SCHOTTKY C2N+\\ Cl /
Figure 2. Oxide-Isolated STL Gate and Equivalent Circuit
1728
TRANSISTORCOLLECTOR
%v 4 I, 1- 0
is 1.25 micrometers and the active base depth is 0.5 micrometer.The delta v is set under nominal conditions by the difference inthe barrier heights of two different metals. Using PtSi for theclamp Schottky and TiW for the logic diode, a voltage swing of250 to 300 mV is obtained.
STL GATE ARRAYS
STL701 Clock Circuit. The clock circuit (CC) utilizes an externallysupplied frequency (20.4608 MHz) to generate six clock signalsfrom internal synchronous divider circuits.
STL702 Baseband. The baseband timing circuit (BTC) containstwo autonomous circuits, a multiplexer clock (MUXCLK) circuitand a delayed clock bias circuit. The MUXCLK circuit providesoutput clocks that range in frequency from 800 to 25 Hz in 1.6-kHz steps. The delayed bias clock circuit provides a phase pro-grammable 1.6-kHz clock.
STL703 Code Timer. The code timing circuit (CTC) uses a fre-quency output from a code digital oscillator resolver to generateclock signals for the P-code. CA-code and code setter clock. TheCTC can resynchronize the CAOS code outputs and also advanceor retard the CA-code.
ELECTRICAL TESTS
All devices were tested on an ACT V VLSI tester, an inter-nally designed test machine, capable of dynamically testing up to33 MHz.
To detect the continued functionality of devices, a completelogic test was run at a benign frequency with the supply at ratedminimum and the output level comparison at 1.0 V. With a 500-ohm pullup resistor to 2 V and a 1,000-ohm pulldown resistor, thedynamic load was guaranteed to be at least 1 mA.
The critical radiation parameters were the ac tests and outputvoltage. FMAX was usually used as the figure of merit for ac perfor-mance, but in some cases propagation delays and setup and holdtimes were included.
FMAX, the test of the internal critical timing path, was runwith 3- and 0-V logic inputs, sweeping the frequency to detect thepass/fail breakpoint. This test was run twice, first at supply maxi-mum, then at minimum. As with the functional test, the dynamicload was 1 mA, with a 1-V trip.
The output voltage vOL, the saturation voltage of the outputtransistors, showed the most dramatic radiation effects. Repetitivetests of VOL were run under a range of loading conditions to allowplotting of VOL as a function ofoutput load and radiation dose. Forthe STL technology, VOH measurements were also made undervaried load.
EXPERIMENTAL PROCEDURE
The device types used in this experiment were from the com-mercial manufacturing line and met a temperature range of -20°to 100°C, but had not been burned in. The devices of a given typewere all from a single diffusion run to eliminate variations inresponse that often occur between diffusion lots. The devices wereelectrically screened at room temperature on the ACT V testerthat was used subsequent to each radiation exposure.
bias with an additional device being used as a control during elec-trical measurements. The inputs and outputs were left floating. Itshould be noted that device outputs, for most device types, couldhave come up in either the high or low state owing to bias appliedduring irradiation. Following radiation exposure, electrical testswere generally completed within 30 minutes to minimize roomtemperature annealing effects. When radiation tests were stoppedovernight or for weekends, an additional electrical screening wasrun before restarting radiation tests to account for possible anneal-ing effects.
RADIATION TEST RESULTS
12L RESPONSE
The PL circuits fabricated from the same basic structurestended to behave in similar ways; i.e., the two small gate arraycircuits, the two large gate array circuits, and the two dedicatedcircuits. Because of these similarities, only one circuit type fromeach class of devices is discussed.
VOL was the only electrical parameter that did not remainwithin specification out to 1 X 106 rad (Si). This result is expectedfor IFL structures and has been observed in other tests.8
Figures 3, 4, and 5 show VOL changes for families of loadcurrents from 1 to 10 mA as a function of total dose. The speci-fication limit was 0.4 V for all currents.
At 1 X 106 rad (Si) the P-code circuit passes all iOL out to 7mA, the DOAC passes iOL to 6 mA, but the interrupt handler (IH)only passes iOL up to 4 mA. These results were a bit surprisingwith the large GA and the small GA both having the same outputcircuit. Electrical measurements and analysis failed to provide ananswer for the differences. It was after all the interrupt handleroutputs were analyzed that a failure pattern emerged that led tothe answer.
The VOL data taken on most of the IFL devices shows thatcertain pins consistently degraded earlier than others, which re-quired explanation. While ideal IFL is a current supply technology,current control is achieved by resistors tied to a main power bus.Because of the voltage drop along the bus, base drive current onthe outputs varies as the path length to the power source varies.To correct this effect, each output base resistor must be tailored tobus position. This was done for each six-output cell by selecting a
0.50
0.45
0. 40
-/> 0.35
W 0. 30
0 0. 25
0> 0.20
E. 0.15X O. lo5O 0.10
0.05s
Radiation exposure was performed at 50 rad (Si)/s, using TI'sGammacell 220 radiation facility. The devices were alternatelyirradiated and electrically measured after cumulative total dosesof 1.25 X 104, 2.5 X 104, 5X 104, X104 , 2X 10 5,5X 105, and1 X 106 rad (Si). Seven devices of each type were irradiated under
INITIAL
LOAD CURRENT- 10 MA 9 8 7 6 5
0. 1
TOTAL DOSE MRAD (Si)1. 0
Figure 3. VOL Versus Total Dose for the Interrupt Handler
1729
0. 50
0.45
0. 40J0> 0.35
w( 0. 30
j 0.250
F 0. 20
IL 0.0 15F°O 0. 10
0. 05
LOAD CURRENT = 10
-SPECIFICATION LIMIT
(LARGE G.A.)
INITIAL
7
0.55
0.50
0. 45
O 0.40
W 0. 35(9
F 0.30-a0> 0.25I-=) 0. 20I.F-Oo. 15
0
0. 10
0. 050. 1 1. 0
TOTAL DOSE MRAD (Si)
Figure 4. VOL Versus Total Dose for the DOAC
0.45
1-,0O. 400~w 0. 35
< 0.30-j0> 0.25F-X 0.20
31 O.t150.
LOAD CURRENT- IO MA
INITIAL 0.1 1.0TOTAL DOSE MRAD (Si)
Figure 5. VoL Versus Total Dose for the P-Code Circuit
main cell bias resistor based on bus potential at each connectionand the number of active outputs within each cell. However, thepath dependence within each cell is not corrected because nocustomization of the gate array is done at this lowest level of cellstructure.
The variation in cell path lengths for the IH gave a directcorrelation to increases in voL at the output pins. A best case plotof VoL for the IH is shown in Figure 6. Notice that the IH nowpasses IOL at 6 mA, which is identical to the level passed by thelarge GA (DOAC). The implications of this problem are summa-rized in Figure 7 that shows, for example, a hardness variation of2 to 1 at an ioL of 6 mA. This will certainly give designers of futureLSI, VLSI and VHSIC circuits cause for concem in their layoutrules. As for the IH, the problem can be solved by adjusting eitherthe path widths or lengths to achieve the same voltage drop foreach output.
The change in VOL for IFL devices results from the decreasedgain of the output transistors. It is believed this gain reduction isprimarily caused by increased surface recombination in theemitter-base depletion region adjacent to the PNP injector4 oraround the periphery of the cell at the oxide interface.
INITIAL 0. 1DOSE MRAD (Si)
Figure 6. Best Case VOL Versus TotalDose for the Interrupt Handler
Figure 7. Hardness Variations in InterruptHandler Output Pins and 'OL
The only other parameter to show a significant change wasFMAX, particularly for the P-code circuit. Plots of FMAX response,with radiation, for each class of circuit are shown in Figure 8.
STL RESPONSE
The radiation response of the three STL devices is summa-rized in Table II. All measured parameters remained within speci-fications out to 1 X 106 rad (Si). Generally, the data spread wasquite small with all devices tracking closely at each radiation testlevel. Icc and 'BB, the +5-V and +2-V supply currents bothshowed increases for the timer. FMAX-1oW, which tests a criticaltiming function at minimum injector current, showed an increaseof 10 percent for the timer. One timer failed a functional testpattem on a clock output at 1 X 106 rad (Si).
The baseband circuit showed a decrease in 'BB of 8 percentand had two functional failures on the three-state outputs at 1 X106 rad (Si). In general, devices fabricated with the STL process
1730
.M.
L4 II..
4
INTERRUPT HANDLER
DOAC
I I I I _I I I IIII I I I II I .11 1INITIAL 0.1 1 .(
TOTAL DOSE MRAD (Sj)
Figure 8. FMAx Response Versus Total Dose for IFL Circuits
appear to be quite hard at 1 megarad. The three STL functionalfailures will be investigated.
RADIATION HARDENED DEVICE
Early radiation tests resulted in a redesign of the interrupthandler to make it harder. The hardened IH features a redesignedoutput circuit, which is capable of handling more current with a
lower saturation and a reduction in fanout from 4 to 2 for internalcircuits. The circuit was hardened by redesign and used the sameproduction process as the original circuit. Radiation test results ona hardened IH test bar are shown in Figure 9. For comparison, theother IFL and STL devices are plotted at the same IOL' includingthe best and worst case (output pins) for the commercial IH.
TABLE 11. 1 MEGARAD TOTAL DOSE TEST SUMMARY FOR STL DEVICES*
Parameter
DC Tests:
ICC6 IBB, II,VIK, IIH, VOH,VOL, IOS, IIL
AC Tests:
FMAX high and low
Clock Baseband
IIL: Increased from 6 to 16 AA IBB: 8 percent increase
High: Decreased from 27.2 to Not applicable26.5 MHz
Timer
Icc: 10 percent decreaseIBB: 29 percent decrease
Low: Increased from24.6 to 27.0 MHz
Functional Tests:Run 3 times with differentlogic conditions
Passed all patterns 1 failed pattern 51 failed pattem 14
1 failed pattern 6
*Sample size was 7 for each part type.
1731
1 5
10 F
NI
lX
5 -
0
0
LOAD CURRENT = SMA
CLOCK (STL)
0.05 - RAD HARDENED INTERRUPT HANDLER
I I I I I I II
INTERRUPTHANDLER
(WORST CASE)
I.H. (BEST CASE)
I I I I1I1 I1INITIAL 0.1
TOTAL DOSE MRAD (Si)
Figure 9. Comparison of VOL Change Versus Total Dose for 12L and STL Devices
CONCLUSION
The effects of ionizing radiation on GPS IFL and STL deviceshas shown that commercial devices fabricated with these technol-ogies are relatively hard to a level of 1 X 106 rad (Si). The STLdevices are quite hard, having shown no significant changes dur-ing radiation testing, other than the three functional failures. Al-though the IFL devices are sensitive to VoL increases at the higherload currents, they still demonstrate good operating characteristicsat 1 megarad for reduced output load currents.
Exposing devices to an ionizing source may prove to be animportant screening technique for designers of future radiation-hardened LSI and VLSI circuits. One example of this applicationwas in the analysis of radiation test data, which identified deviceoutputs that showed an above average sensitivity to increases inVOL. Investigation led to the discovery that differences in pathlength between the 6 output transistors within a cell were in somecases adding resistance in series with the base, which caused re-
duced base drive. With this information it is possible to hardenthe circuit by altering the lead routing at the mask level.
Improvement in the VOL radiation tolerance of the commer-cially designed IH was implemented through circuit redesign.Since the hardened circuit used the same production process, itwas possible to see the full impact of the design changes on circuitperformance. The circuit was not only harder but faster.
