Total Ionizing Dose Effects in 130-nm Commercial CMOS Technologies for HEP experiments L. Gonella,...

Total Ionizing Dose Effects in Total Ionizing Dose Effects in 130-nm Commercial CMOS 130-nm Commercial CMOS

Technologies for HEP experimentsTechnologies for HEP experiments

L. Gonella, M. Silvestri, S. Gerardin

on behalf of the

DACEL – CERN collaboration

http://www.infn.it/

Perugia, 26/9/2006 S. Gerardin

OutlineOutline

• Introduction & DACEL• Experimental and Devices• TID irradiation (X-rays):

– Core transistors: • Worst-case bias conditions

– NMOSFETs– PMOSFETs

• Impact of bias • Different foundries

– I/O transistors:• Worst-case bias conditions

– NMOSFETs– PMOSFETs

• Impact of bias and foundry• Conclusions


DACELDACEL

• Design And Characterization of deep submicron ELectronic devices for future particle detectors

• Born in 2004• Participating Institutions

– INFN sections:• Bari• Bologna• Firenze• Padova• Torino

• In collaboration with CERN-MIC group


IntroductionIntroduction

• Super LHC radiation environment– Expected up to 100 Mrad in 10 years’ time

• Purpose of this work:– Assess the suitability of commercial deep-submicron/

decananometer CMOS technologies for use in future HEP experiments


DevicesDevices

• MOSFETs manufactured in commercial 130-nm CMOS technologies:– Core transistors: tox=2.2nm

• Different aspect ratio (W\L)• Enclosed Layout Transistors (ELT)

– I/O transistors: tox= 5.2nm

• Different aspect ratio• Enclosed Layout Transistors (ELT)

• Three different suppliers called in the following: A, B, and C


ExperimentalExperimental

• CERN X-ray probe station– X SEIFERT RP149 60-KV

maximum voltage, tungsten target

– Dose rate: ~ 25 krad/s– HP4145B parameter analyzer– Thermal chuck (+5°C to +200°C) – Custom probe card– Switching matrix– LabVIEW software – Fully automated!


Core Transistors:Core Transistors:Worst Case Bias ConditionsWorst Case Bias Conditions


Minimum Size NMOSFETsMinimum Size NMOSFETs

• Increase in off-current (Ileak) up to 3 orders of magnitude

• Large negative shift in the Vth

• TID rebound in Vth and Ileak degradation

Supplier ACore

NMOSFET(linear) W/L=

0.16/0.12µm

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

20

40

60

80

100

120

140

I ds [

A]

Vgs

[V]

pre-rad 1 Mrad 5 Mrad 27 Mrad 97 Mrad 190 Mrad

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.410-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4


I ds [A

]

Vgs

[V]

Source

Drain

Gate


Large-width NMOSFETsLarge-width NMOSFETs

• Increase in off-current (Ileak)

• No shift in the threshold voltage

• TID rebound in the Ileak degradation between 5 and 27 Mrad

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.410-1210-11

10-1010-910-810-7

10-610-510-410-3

I ds [A

]

Vgs

[V]


Supplier A Core NMOSFET (linear)

W/L= 2/0.12µm


Enclosed Layout NMOSFETsEnclosed Layout NMOSFETs

• Negligible TID effects on Enclosed Layout Transistors

• Very hard gate oxide! (up to 190 Mrad)

Supplier A Core ELT NMOSFET (enclosed)

W min, L=0.12µm

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.410-1210-11

10-1010-9

10-810-710-6

10-510-410-3

I ds [

mA

]

Vgs

[V]

pre-rad 1 Mrad 97 Mrad 190 Mrad

Source

Drain

Gate


NMOSFETs:NMOSFETs:VVthth vs dose vs dose

• Negligible TID effects in large-width and enclosed layout NMOSFETs

• Up to -150mV shift in minimum size NMOSFETs (0.16/0.12m)

• TID rebound in the Vth between 1 and 10MradSupplier A

Linear Core NMOSFETs

105 106 107 108 109-160

-140

-120

-100

-80

-60

-40

-20

0

ELT 10/10 10/1 2/0.12 0.8/0.12 0.64/0.12 0.48/0.12 0.32/0.12 0.16/0.12

Vth [

mV

]

TID [rad]


NMOSFETs: INMOSFETs: Ileakleak vs dose vs dose

• No change in ELTs

• Up to 3 orders of magnitude increase for all W/L (non-ELT)

• TID rebound in the degradation between 1 and 10 Mrad

Supplier ACore NMOSFETs

pre-rad 105 106 107 108 10910-10

10-9

10-8

10-7

I leak

[A]

TID [rad]

ELT 10/10 10/1 2/0.12 0.8/0.12 0.64/0.12 0.48/0.12 0.32/0.12 0.16/0.12


Minimum Size PMOSFETsMinimum Size PMOSFETs

• Less severe degradation compared to NMOSFETs• Negative Vth shift• Negligible changes in Ileak

Supplier ACore

PMOSFET W/L=

0.16/0.12µmVds=1.5 V

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.210-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

I ds [A

]

Vgs

[V]

pre-rad 1 Mrad 5 Mrad 25 Mrad 55 Mrad

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2

20

40

I ds [

A]

Vgs

[V]



PMOSFETs:PMOSFETs:VVthth vs dose vs dose

105 106 107 108

-10

0

10

20

30

40

50

Vth [

mV

]

TID [rad]

10/10 10/1 2/0.12 0.8/0.12 0.48/0.12 0.16/0.12

• Negligible effects in large-width and enclosed layout NMOSFETs

• Up to 50mV shift in minimum size MOSFETs (0.16/0.12m)

Supplier A Core PMOSFETs


+

STI: Achilles’ heelSTI: Achilles’ heel

• ELTs almost immune => Very hard gate oxide due to scaling

• Increase in Ileak in Large-Width and Minimum-Size NMOSFETs => positive charge trapped in STI

• Vth larger in narrow channel transistors (Radiation Induced Narrow Channel Effect)

• TID rebound due to charge trapping/interface generation kinetics: maximum degradation between 1 and 10 Mrad

W

STI

Parasitic Channels

+++

+

Main Channel

poly gate

positive trapped charge

Interface states

++++


Core Transistors: Core Transistors: Impact of Bias ConditionsImpact of Bias Conditions


Bias Dependence: Bias Dependence: VVthth

Minimum-Size NMOSFETs• Worst condition:

– Vgs = Vdd

– Vth,max=-150 mV

• Intermediate condition

– Vgs = Vdd/2

– Vth.max=-120 mV

• Best condition

– Vgs = 0 V

– Vth,max=-60mVSupplier A

Core NMOSFETsW/L=0.16/0.12µm

105 106 107 108-160

-140

-120

-100

-80

-60

-40

-20

0

Vth [m

V]

TID [rad]

Vgs

=Vdd

Vgs

=Vdd

/2

Vgs

=0 V


Bias Dependence: IBias Dependence: Ileakleak

Supplier A Core NMOSFETsW/L=0.16/0.12µm

Minimum-Size NMOSFETs• Worst condition:

– Vgs = Vdd

– Ileak,max ↑ = 103x

• Intermediate condition

– Vgs = Vdd/2


• Best condition

– Vgs = 0 V


pre-rad 106 107 108

10-10

10-9

10-8

10-7

10-6

I leak

[A]

TID [rad]

Vgs

=Vdd

Vgs

=Vdd

/2

Vgs

=0 V


Core Transistors: Core Transistors: Different FoundriesDifferent Foundries


Different foundries: NMOSFETs Different foundries: NMOSFETs VVthth

• Qualitatively, the same effects

• Quantitatively, softer and harder technologies

• TID rebound occurs at different total doses

• Maximum Vth in minimum size NMOSFETs from 50 mV to 150 mV

Suppliers A,B,C Core NMOSFETs

W/L=0.16/0.12-0.13µm

105 106 107 108 109-160

-140

-120

-100

-80

-60

-40

-20

0

Vth [m

V]

TID [rad]

A 0.16/0.12 B 0.16/0.13 C 0.16/0.12


Different foundries: NMOSFETs IDifferent foundries: NMOSFETs Ileakleak

• Qualitatively, the same effects

• Quantitatively, softer and harder technologies

• TID rebound occurs at different total doses

• Maximum Ileak in minimum size NMOSFETs from 10x to 104xSuppliers A,B,C

Core NMOSFETsW/L=0.16/0.12-0.13µm

pre-rad 105 106 107 108 10910-10

10-9

10-8

10-7

10-6

I leak

[A]

TID [rad]

A 0.16/0.12 B 0.16/0.13 C 0.16/0.12


I/O Transistors:I/O Transistors:Worst Case Bias ConditionsWorst Case Bias Conditions


Minimum Size NMOSFETsMinimum Size NMOSFETs

Supplier AI/O MOSFETs

W/L=0.36/0.24µm

NMOSFET

PMOSFET

• More severe degradation compared to core devices for NMOSFETs and PMOSFETs in terms of Vth and Ileak

• Vth and Ileak in NMOSFETs• Vth in PMOSFETs

0.0 0.4 0.8 1.2 1.6 2.0 2.410-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

pre-rad 300 krad 1 Mrad 27 Mrad 97 Mrad 190 Mrad

I ds [A

]

Vgs

[V]

-2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.010-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

I ds [A

]

Vgs

[V]



Enclosed LayoutEnclosed Layout

• ELTs degrade as well

• Gate oxide still an issue

• Increase in subthreshold swing: interface traps

Supplier A I/O ELT NMOSFETW min, L=0.12µm

0.0 0.4 0.8 1.2 1.6 2.0 2.410-1210-11

10-1010-910-810-7

10-610-510-410-3

I ds [A

]

Vgs

[V]



NMOSFETs:NMOSFETs:VVthth vs dose vs dose

105 106 107 108

-400

-300

-200

-100

0

100

Vth [

mV

]

TID [rad]

0.36/0.24 0.8/0.24 0.5/0.24 2/0.24 10/1 10/10 ELT min/0.26

Supplier AI/O NMOSFETs

• Vth up to -400 mV in minimum-size devices

• TID rebound in narrow devices

• Monotonic increase in large-width and ELTs


NMOSFETs:NMOSFETs:IIleakleak vs dose vs dose

• No change in ELTs

• Up to 5 orders of magnitude increase for all W/L (non-ELTs)

• TID rebound in the degradation between 1 and 10Mrad

Supplier AI/O NMOSFETs

pre-rad 105 106 107 108 109

10-11

10-10

10-9

10-8

10-7

10-6

10-5

I lea

k [A]

TID [rad]

0.36/0.24 0.8/0.24 0.5/0.24 2/0.24 10/1 10/10 ELT W=min L=0.26


PMOSFETs:PMOSFETs:VVthth vs dose vs dose

105 106 107 108

0

100

200

300

400

Vth [

mV

]

TID [rad]

10/10 10/1 2/0.24 0.8/0.24 0.5/0.24 0.36/0.24 ELT W=min, L=0.26

• Vth up to 350 mV in minimum-size devices

• Smaller dependence on geometry than NMOSFETs

• Monotonic increase

Supplier AI/O PMOSFETs


Impact of Bias and FoundryImpact of Bias and Foundry

• Bias: dependence similar to that of core transistors– Vth.max(MS NMOSFETs) from -50 mV to -250 mV

– Ileak,max(NMOSFETs) ↑ from 10x to 105x

• Foundry: variability similar to that of core transistors– Vth,max(NMOSFETs) from -400 mV to -60 mV

– Ileak,max(NMOSFETs) ↑ from 102x to 108x


ConclusionsConclusions

• TID effects on Core Transistors– Narrow and short devices most affected– Very hard gate oxide, less hard STI– Large impact of bias conditions during operation– Large foundry to foundry variability

• TID effects on I/O Transistors– Same effects as on Core Transistors + gate oxide still an issue

• 130-nm CMOS is harder than older technologies, and may be up to the challenge of future HEP experiments even without ELTs, but, in this case, needs constant monitoring due to variability from foundry to foundry


Open IssuesOpen Issues

• Batch to batch variability (encouraging preliminary results)

• Annealing and dose rate vs rebound

• Effects of different radiation sources (protons)

• Impact on flicker noise

• Long-term effects on the gate oxide reliability

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Total Ionizing Dose Effects in 130-nm Commercial CMOS Technologies for HEP experiments L. Gonella,...

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