Touch Control Wireless Robo

8/2/2019 Touch Control Wireless Robo

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TOUCH CONTROL WIRELESS ROBO


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In this project we show that how we control the robo with the help of touch

screen. IN this project we use two circuit. One is transmitter and second is

receiver. In transmitter circuit we use ATMEGA16L WITH TOUCH

SCREEN and in the receiver circuit we use AT MEGA8. To relate both the

circuit we use RF ask module ( 433 ) mhtz . For robo we use two or four dc

motors.

Main part of this project is touch screen. Here we use 4 wire resistive touch

screen.

Resistive 4- and 5-wire touch systems belong to the most popular and most

common touch screen technologies. Their market share is about 75%,

mainly due to their low costs and simple interface electronics. Resistive

System can be found in various mobile applications including PDAs and

Smartphones.

Usually a resistive touch screen consists of at least three layers: A flexible

membrane made from PET film is suspended over a rigid substrate made

from glass or acryl .Both surfaces are coated with a transparent conductive

film like ITO (Indium tin oxide). The conductive ITO layers are kept apart by

an insulting spacer along the edges, and by spacer dots on the inner

surface of the two ITO layers. In this way there will be no electrical

connection unless pressure is applied to the topsheet (PET film).


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(The busbars in the topsheet and substrate are perpendicular to eachother. The busbars are connected to the touch screen controller through a

4-wire flex cable. The 4 wires are referred as X+ (left), X- (right), Y+ (top)

and Y- (bottom).

An advantage of the 4-wire touch screens is that it is possible to determine

the touch pressure by measuring the contact resistance (RTouch) between

the two ITO layers. RTouch decreases as the touch pressure (or the size of

the depressed area) increases. This characteristic can be useful in

applications in which it is not only required to detect where the pressure is

applied, but also the type of pressure (area and force).


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The method for measuring the pressure point is based upon a preferably

homogenous resistive surface (ITO). When applying a voltage to theelectrode pair in the resistive surface a uniform voltage gradient appears

across the surface. A second ITO layer is necessary to do a high-

resistance voltage measurement. A resistive touch screen can thus be

seen as an electrical switch requiring a small amount of pressure (0.1 1.5

Newton) to close.


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The point of contact divides each layer in a series resistor network with

two resistors (see Figure 2-3), and a connecting resistor between the two

layers. By measuring the voltage at this point the user gets information

about the position of the contact point orthogonal to the voltage gradient.

To get a complete set of coordinates, the voltage gradient must be applied

once in vertical and then in horizontal direction: first a supply voltage must

be applied to one layer and a measurement of the voltage across the other

layer is performed, next the supply is instead connected to the other layer

and the opposite layer voltage is measured. In stand-by mode one of the

lines are connected to a level triggered interrupt in order to detect touch

activity. Please refer to Table 2-1 for connections while measuring the

coordinates.


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To get a complete set of coordinates, the voltage gradient is applied on the

substrate layer once in horizontal direction to determine the Y coordinate

and once in vertical direction to determine the X coordinate. In both cases

the topsheet layer is used to do a high-impedance measurement after the

sensing voltage has settled. In standby

mode the fifth w


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An A/D converter with a resolution of 10 bits and the absolute inaccuracy

far under the linearity error of the touch screen (1,5%-3%) is required for

the conversion of the analog values into digital values.

When considering the minimum detection time for applied pressure on the

screen and changes in coordinates, the conversion time of the ADC must

be considered. In an application only monitoring clicks, 70 points per

seconds is typically needed. For detection of motion, e.g. handwriting, one

should calculate approximately 200 points per second - taking into account

that multiple measurements are included to compass the correct point (by

oversampling and digital filtering). Also, the CPU must be able to process

the ADC readings with sufficient computational accuracy to not reduce the

detection rate.


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Introduction to the Atmel ATmega 16 Microcontroller

Learning Objectives: At the end of this lab students will be able to

Identify the Atmel ATmega 16 microcontroller, STK500 Development Board,

and associated hardware.

Create a new project in AVR Studio and populate the project with pre-existing

code.

Use AVR Studio to compile code in ANSI C.

Use AVR Studio to program the ATmega 16 microcontroller.

Components:

Qty. Item

1 Atmel ATmega 16 microcontroller mounted to STK500 interface board

1 Serial programming cable

1 12 VDC power supply

1 6-pin ribbon cable

1 2-wire female-female jumper


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2 10-wire female-female jumper

Introduction:

A microcontroller can be a powerful tool when building electro-mechanical

systems. Like a mini, self-contained

computer, it can be programmed to interact with both the hardware and the user.

Even the most basic microcontroller

can perform simple math operations, control digital outputs, and monitor digital

inputs. As the computer industry has

evolved, so has the technology associated with microcontrollers. Newer

microcontrollers are much faster, have more

memory, and have a host of input and output features that dwarf the ability of

earlier models. Most modern

controllers have analog-to digital converters, high-speed timers and counters,

interrupt capabilities, outputs that can

be pulse-width modulated, serial communication ports, and the list goes on.


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The microcontroller and the development board used in this lab are

donated by Atmel for your use. In

industry, you can expect to pay anywhere from $50 to $400 for just the

development board and up to

$1000 for a professional compiler and programming interface! SO BE

CAREFUL AND RESPECTFUL of

the microcontrollers and development boards! Like any electronic device,

they are sensitive and may be

damaged easily! BE CAREFUL of static charges! USE COMMON SENSE,

and FOLLOW THE

INSTRUCTIONS in the lab assignments. You will build upon your

experience from each lab, and are encouraged to learn from examples.

The ATmega 16 Microcontroller The ATmega 16 microcontroller used in this

lab is a 40-Pin Wide DIP (Dual Inline Package) chip. This chip selected because it

is robust and the DIP package interfaces with prototyping supplies like solderless

bread boards and solder pref-boards. This same micrcocontroller is available in a

surface mount package, about the size of a dime, that would be more useful in a

production (ie industry) setting. Figure 1below shows the pin-out diagram of the


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ATmega 16. This Diagram is very useful, it tell you the user of the chip, how it

should be powered, which pins tie to which functional hardware,


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H-Bridges: Theory and Practice

Introduction

A number of web sites talk about H-bridges, they are a topic of

great discussion in robotics clubs and they are the bane of

many robotics hobbyists. I periodically chime in on discussions

about them, and while not an expert by a long shot I've built a

few over the years. Further, they were one of my personal

stumbling blocks when I was first getting into robotics. This

section of the notebook is devoted to the theory and practice

of building H-bridges for controlling brushed DC motors (the

most common kind you will find in hobby robotics ...) I've got an

image of one below with both as a unit and "expanded" in an

exploded view.


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Basic Theory

Let's start with the name, H-bridge. Sometimes called a "full

bridge" the H-bridge is so named because it has four switching

elements at the "corners" of the H and the motor forms the

cross bar. The basic bridge is shown in the figure to the right.

Of course the letter H doesn't have the top and bottom joined

together, but hopefully the picture is clear. This is also


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something of a theme of this tutorial where I will state

something, and then tell you it isn't really true :-).

The key fact to note is that there are, in theory, four

switching elements within the bridge. These four elements are

often called, high side left, high side right, low side right, and

low side left (when traversing in clockwise order).

The switches are turned on in pairs, either high left and lower

right, or lower left and high right, but never both switches on

the same "side" of the bridge. If both switches on one side of a

bridge are turned on it creates a short circuit between the

battery plus and battery minus terminals. This phenomena is

called shoot through in the Switch-Mode Power Supply (SMPS)

literature. If the bridge is sufficiently powerful it will absorb

that load and your batteries will simply drain quickly. Usually

however the switches in question melt.


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To power the motor, you turn on two switches that are

diagonally opposed. In the picture to the right, imagine that the

high side left and low side right switches are turned on. The

current flow is shown in green.

The current flows and the motor begins to turn in a "positive"

direction. What happens if you turn on the high side right and

low side left switches? You guessed it, current flows the other

direction through the motor and the motor turns in the

opposite direction.

Pretty simple stuff right? Actually it is just that simple, the

tricky part comes in when you decide what to use for switches.

Anything that can carry a current will work, from four SPST

switches, one DPDT switch, relays, transistors, to enhancement

mode power MOSFETs.

One more topic in the basic theory section, quadrants. If each

switch can be controlled independently then you can do some


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interesting things with the bridge, some folks call such a bridge

a "four quadrant device" (4QD get it?). If you built it out of a

single DPDT relay, you can really only control forward or

reverse. You can build a small truth table that tells you for

each of the switch's states, what the bridge will do. As each

switch has one of two states, and there are four switches,

there are 16 possible states. However, since any state that

turns both switches on one side on is "bad" (smoke issues

forth), there are in fact only four useful states (the four

quadrants) where the transistors are turned on.

High

Side

Left

High

Side

Right

Lower

Left

Lower

Right Quadrant Description

On Off Off On Motor goes Clockwise

Off On On Off Motor goes Counter-clockwise

On On Off Off Motor "brakes" and decelerates

Off Off On On Motor "brakes" and decelerates


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The last two rows describe a maneuver where you "short

circuit" the motor which causes the motors generator effect to

work against itself. The turning motor generates a voltage

which tries to force the motor to turn the opposite direction.

This causes the motor to rapidly stop spinning and is called

"braking" on a lot of H-bridge designs.

Of course there is also the state where all the transistors are

turned off. In this case the motor coasts if it was spinning and

does nothing if it was doing nothing.

Instruction Set Nomenclature

Status Register (SREG)

SREG: Status Register

C: Carry Flag

Z: Zero Flag

N: Negative Flag


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V: Twos complement overflow indicator

S: NV, For signed tests

H: Half Carry Flag

T: Transfer bit used by BLD and BST instructions

I: Global Interrupt Enable/Disable Flag

Registers and Operands

Rd: Destination (and source) register in the Register File

Rr: Source register in the Register File

R: Result after instruction is executed

K: Constant data

k: Constant address

b: Bit in the Register File or I/O Register (3-bit)

s: Bit in the Status Register (3-bit)

X,Y,Z: Indirect Address Register

(X=R27:R26, Y=R29:R28 and Z=R31:R30)


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A: I/O location address

q: Displacement for direct addressing (6-bit)

8-bit

Instruction Set

Rev. 0856HAVR07/09

2

0856HAVR07/09

AVR Instruction Set

I/O Registers

RAMPX, RAMPY, RAMPZ

Registers concatenated with the X-, Y-, and Z-registers enabling indirect

addressing of the whole data space on MCUs with

more than 64K bytes data space, and constant data fetch on MCUs with

more than 64K bytes program space.

RAMPD


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Register concatenated with the Z-register enabling direct addressing of the

whole data space on MCUs with more than 64K

bytes data space.

EIND

Register concatenated with the Z-register enabling indirect jump and call to

the whole program space on MCUs with more

than 64K words (128K bytes) program space.

Stack

STACK: Stack for return address and pushed registers

SP: Stack Pointer to STACK

Flags

: Flag affected by instruction

0: Flag cleared by instruction

1: Flag set by instruction

-: Flag not affected by instruction

3


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0856HAVR07/09

AVR Instruction Set

The Program and Data Addressing Modes

The AVR Enhanced RISC microcontroller supports powerful and efficient

addressing modes for access to the Program

memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and

Extended I/O Memory). This section describes

the various addressing modes supported by the AVR architecture. In the

following figures, OP means the operation code

part of the instruction word. To simplify, not all figures show the exact

location of the addressing bits. To generalize, the

abstract terms RAMEND and FLASHEND have been used to represent the

highest location in data and program space,

respectively.

Note: Not all addressing modes are present in all devices. Refer to the

device spesific instruction summary.

Register Direct, Single Register Rd


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Figure 1. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers Rd and Rr

Figure 2. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in

register d (Rd).

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0856HAVR07/09

AVR Instruction Set

I/O Direct

Figure 3. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the

destination or source register address.

Note: Some complex AVR Microcontrollers have more peripheral units than

can be supported within the 64 locations reserved in the


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opcode for I/O direct addressing. The extended I/O memory from address

64 to 255 can only be reached by data addressing,

not I/O addressing.

Data Direct

Figure 4. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word

instruction. Rd/Rr specify the destination or source

register.

OP Rr/Rd

31 16

15 0

Data Address

0x0000

RAMEND

20 19

Data Space


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5

0856HAVR07/09

AVR Instruction Set

Data Indirect with Displacement

Figure 5. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the

address contained in 6 bits of the instruction

word. Rd/Rr specify the destination or source register.

Data Indirect

Figure 6. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register. In AVR

devices without SRAM, Data Indirect Addressing is

called Register Indirect Addressing. Register Indirect Addressing is a

subset of Data Indirect Addressing since the data

space form 0 to 31 is the Register File.

Data Space


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0x0000

RAMEND

Y OR Z - REGISTER

OP Rr/Rd q

0

10 6 5 0

15

15

Data Space

0x0000

X, Y OR Z - REGISTER

15 0

RAMEND

6

0856HAVR07/09


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AVR Instruction Set

Data Indirect with Pre-decrement

Figure 7. Data Indirect Addressing with Pre-decrement

The X,- Y-, or the Z-register is decremented before the operation. Operand

address is the decremented contents of the X-,

Y-, or the Z-register.

Data Indirect with Post-increment

Figure 8. Data Indirect Addressing with Post-increment

The X-, Y-, or the Z-register is incremented after the operation. Operand

address is the content of the X-, Y-, or the Z-register

prior to incrementing.

Data Space

0x0000


15 0

-1


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RAMEND

Data Space

0x0000


15 0

1

RAMEND

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0856HAVR07/09

AVR Instruction Set

Program Memory Constant Addressing using the LPM, ELPM, and

SPM Instructions

Figure 9. Program Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15

MSBs select word address. For LPM, the LSB selects


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low byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the

LSB should be cleared. If ELPM is used, the

RAMPZ Register is used to extend the Z-register.

Program Memory with Post-increment using the LPM Z+ and ELPM Z+

Instruction

Figure 10. Program Memory Addressing with Post-increment

Constant byte address is specified by the Z-register contents. The 15

MSBs select word address. The LSB selects low byte

if cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM Z+ is used, the

RAMPZ Register is used to extend the Z-register.

FLASHEND

0x0000

LSB

FLASHEND

0x0000

1


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LSB

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AVR Instruction Set

Direct Program Addressing, JMP and CALL

Figure 11. Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction

word.

Indirect Program Addressing, IJMP and ICALL

Figure 12. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e.,

the PC is loaded with the contents of the Zregister).

FLASHEND

31 16

OP 6 MSB

16 LSB


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PC

21 0

15 0

0x0000

FLASHEND

PC

15 0

0x0000

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0856HAVR07/09

AVR Instruction Set

Relative Program Addressing, RJMP and RCALL

Figure 13. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k

is from -2048 to 2047.

FLASHEND


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1

0x0000

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AVR Instruction Set

Conditional Branch Summary

Note: 1. Interchange Rd and Rr in the operation before the test, i.e., CP

Rd,Rr CP Rr,Rd

Test Boolean Mnemonic Complementary Boolean Mnemonic

Comment

Rd > Rr Z(NV) = 0 BRLT(1) Rd Rr Z+(NV) = 1 BRGE* Signed

RdRr (NV) = 0 BRGE Rd < Rr (N V) = 1 BRLT Signed

Rd = Rr Z = 1 BREQ Rd Rr Z = 0 BRNE Signed

Rd Rr Z+(NV) = 1 BRGE(1) Rd > Rr Z(NV) = 0 BRLT* Signed

Rd < Rr (NV) = 1 BRLT Rd Rr (NV) = 0 BRGE Signed

Rd > Rr C + Z = 0 BRLO(1) Rd Rr C + Z = 1 BRSH* Unsigned


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RdRr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned

Rd = Rr Z = 1 BREQ Rd Rr Z = 0 BRNE Unsigned

Rd Rr C + Z = 1 BRSH(1) Rd > Rr C + Z = 0 BRLO* Unsigned

Rd < Rr C = 1 BRLO/BRCS Rd Rr C = 0 BRSH/BRCC Unsigned

Carry C = 1 BRCS No carry C = 0 BRCC Simple

Negative N = 1 BRMI Positive N = 0 BRPL Simple

Overflow V = 1 BRVS No overflow V = 0 BRVC Simple

Zero Z = 1 BREQ Not zero Z = 0 BRNE Simple

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0856HAVR07/09

AVR Instruction Set

Complete Instruction Set Summary

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

#Clocks


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XMEGA

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1

ADIW(1) Rd, K Add Immediate to Word Rd Rd + 1:Rd + K Z,C,N,V,S 2

SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1

SBIW(1) Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K

Z,C,N,V,S 2

AND Rd, Rr Logical AND Rd Rd Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd Rd K Z,N,V,S 1

OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd RdRr Z,N,V,S 1


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COM Rd Ones Complement Rd $FF - Rd Z,C,N,V,S 1

NEG Rd Twos Complement Rd $00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd Rd ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V,S 1

CLR Rd Clear Register Rd RdRd Z,N,V,S 1

SER Rd Set Register Rd $FF None 1

MUL(1) Rd,Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2

MULS(1) Rd,Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2

MULSU(1) Rd,Rr Multiply Signed with Unsigned R1:R0 Rd x Rr (SU)

Z,C 2

FMUL(1) Rd,Rr Fractional Multiply Unsigned R1:R0 Rd x Rr


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FMULS(1) Rd,Rr Fractional Multiply Signed R1:R0 Rd x Rr


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0

None 2

EIJMP(1) Extended Indirect Jump to (Z) PC(15:0)

PC(21:16)

Z,

EIND

None 2

JMP(1) k Jump PC k None 3

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0856HAVR07/09

AVR Instruction Set

RCALL k Relative Call Subroutine PC PC + k + 1 None 3 / 4(3)(5) 2 /

3(3)

ICALL(1) Indirect Call to (Z) PC(15:0)

PC(21:16)


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Z,

0

None 3 / 4(3) 2 / 3(3)

EICALL(1) Extended Indirect Call to (Z) PC(15:0)

PC(21:16)

Z,

EIND

None 4 (3) 3 (3)

CALL(1) k call Subroutine PC k None 4 / 5(3) 3 / 4(3)

RET Subroutine Return PC STACK None 4 / 5(3)

RETI Interrupt Return PC STACK I 4 / 5(3)

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1

/ 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1


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CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3

None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None

1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC PC + 2

or 3 None 1 / 2 / 3 2 / 3 / 4

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC PC + 2 or 3

None 1 / 2 / 3 2 / 3 / 4

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k +

1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC +

k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2


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BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 /

2

BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None

1 / 2

BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (NV= 0) then PC PC +

k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N V= 1) then PC PC + k + 1

None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1

None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1

None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2


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BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 /

2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1

None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1

None 1 / 2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1 /

2

BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None

1 / 2

Data Transfer Instructions

MOV Rd, Rr Copy Register Rd Rr None 1

MOVW(1) Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd K None 1

LDS(1) Rd, k Load Direct from data space Rd (k) None 1(5)/2(3) 2(3)(4)

LD(2) Rd, X Load Indirect Rd (X) None 1(5)2(3) 1(3)(4)



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#Clocks

XMEGA

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0856HAVR07/09

AVR Instruction Set

LD(2) Rd, X+ Load Indirect and Post-Increment Rd

X

(X)

X + 1

None 2(3) 1(3)(4)

LD(2) Rd, -X Load Indirect and Pre-Decrement X X - 1,

Rd (X)

X - 1


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(X)

None 2(3)/3(5) 2(3)(4)

LD(2) Rd, Y Load Indirect Rd (Y) (Y) None 1(5)/2(3) 1(3)(4)

LD(2) Rd, Y+ Load Indirect and Post-Increment Rd

Y

(Y)

Y + 1

None 2(3) 1(3)(4)

LD(2) Rd, -Y Load Indirect and Pre-Decrement Y

Rd

Y - 1

(Y)

None 2(3)/3(5) 2(3)(4)


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LDD(1) Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2(3)

2(3)(4)

LD(2) Rd, Z Load Indirect Rd (Z) None 1(5)/2(3) 1(3)(4)

LD(2) Rd, Z+ Load Indirect and Post-Increment Rd

Z

(Z),

Z+1

None 2(3) 1(3)(4)

LD(2) Rd, -Z Load Indirect and Pre-Decrement Z

Rd

Z - 1,

(Z)

None 2(3)/3(5) 2(3)(4)


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LDD(1) Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2(3)

2(3)(4)

STS(1) k, Rr Store Direct to Data Space (k) Rd None 1(5)/2(3) 2(3)

ST(2) X, Rr Store Indirect (X) Rr None 1(5)/2(3) 1(3)

ST(2) X+, Rr Store Indirect and Post-Increment (X)

X

Rr,

X + 1

None 1(5)/2(3) 1(3)

ST(2) -X, Rr Store Indirect and Pre-Decrement X

(X)

X - 1,

Rr

None 2(3) 2(3)


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ST(2) Y, Rr Store Indirect (Y) Rr None 1(5)/2(3) 1(3)

ST(2) Y+, Rr Store Indirect and Post-Increment (Y)

Y

Rr,

Y + 1

None 1(5)/2(3) 1(3)

ST(2) -Y, Rr Store Indirect and Pre-Decrement Y

(Y)

Y - 1,

Rr

None 2(3) 2(3)

STD(1) Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2(3)

2(3)

ST(2) Z, Rr Store Indirect (Z) Rr None 1(5)/2(3) 1(3)


48/332

ST(2) Z+, Rr Store Indirect and Post-Increment (Z)

Z

Rr

Z + 1

None 1(5)/2(3) 1(3)

ST(2) -Z, Rr Store Indirect and Pre-Decrement Z Z - 1 None 2(3) 2(3)

STD(1) Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2(3)

2(3)

LPM(1)(2) Load Program Memory R0 (Z) None 3 3

LPM(1)(2) Rd, Z Load Program Memory Rd (Z) None 3 3

LPM(1)(2) Rd, Z+ Load Program Memory and Post-

Increment

Rd

Z


49/332

(Z),

Z + 1

None 3 3

ELPM(1) Extended Load Program Memory R0 (RAMPZ:Z) None 3

ELPM(1) Rd, Z Extended Load Program Memory Rd (RAMPZ:Z) None 3

ELPM(1) Rd, Z+ Extended Load Program Memory and

Post-Increment

Rd

Z

(RAMPZ:Z),

Z + 1

None 3

SPM(1) Store Program Memory (RAMPZ:Z) R1:R0 None - -

SPM(1) Z+ Store Program Memory and Post-


50/332

Increment by 2

(RAMPZ:Z)

Z

R1:R0,

Z + 2

None - -

IN Rd, A In From I/O Location Rd I/O(A) None 1

OUT A, Rr Out To I/O Location I/O(A) Rr None 1

PUSH(1) Rr Push Register on Stack STACK Rr None 2 1(3)

POP(1) Rd Pop Register from Stack Rd STACK None 2 2(3)


#Clocks

XMEGA

14


51/332

0856HAVR07/09

AVR Instruction Set

Notes: 1. This instruction is not available in all devices. Refer to the device

specific instruction set summary.

2. Not all variants of this instruction are available in all devices. Refer to the

device specific instruction set summary.

3. Cycle times for Data memory accesses assume internal memory

accesses, and are not valid for accesses via the external

RAM interface.

Bit and Bit-test Instructions

LSL Rd Logical Shift Left Rd(n+1)

Rd(0)

C

Rd(n),

0,


52/332

Rd(7)

Z,C,N,V,H 1

LSR Rd Logical Shift Right Rd(n)

Rd(7)

C

Rd(n+1),

0,

Rd(0)

Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)

Rd(n+1)

C

C,


53/332

Rd(n),

Rd(7)

Z,C,N,V,H 1

ROR Rd Rotate Right Through Carry Rd(7)

Rd(n)

C

C,

Rd(n+1),

Rd(0)

Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1

BSET s Flag Set SREG(s) 1 SREG(s) 1

BCLR s Flag Clear SREG(s) 0 SREG(s) 1


54/332

SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 1(5)2 1

CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 1(5)/2 1

BST Rr, b Bit Store from Register to T T Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) T None 1

SEC Set Carry C 1 C 1

CLC Clear Carry C 0 C 1

SEN Set Negative Flag N 1 N 1

CLN Clear Negative Flag N 0 N 1

SEZ Set Zero Flag Z 1 Z 1

CLZ Clear Zero Flag Z 0 Z 1

SEI Global Interrupt Enable I 1 I 1

CLI Global Interrupt Disable I 0 I 1

SES Set Signed Test Flag S 1 S 1

CLS Clear Signed Test Flag S 0 S 1

SEV Set Twos Complement Overflow V 1 V 1


55/332

CLV Clear Twos Complement Overflow V 0 V 1

SET Set T in SREG T 1 T 1

CLT Clear T in SREG T 0 T 1

SEH Set Half Carry Flag in SREG H 1 H 1

CLH Clear Half Carry Flag in SREG H 0 H 1

MCU Control Instructions

BREAK(1) Break (See specific descr. for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1


#Clocks

XMEGA

15

0856HAVR07/09


56/332

AVR Instruction Set

4. One extra cycle must be added when accessing Internal SRAM.

5. Number of clock cycles for ATtiny10.

16

0856HAVR07/09

AVR Instruction Set

ADC Add with Carry

Description:

Adds two registers and the contents of the C Flag and places the result in

the destination register Rd.

Operation:

(i) Rd Rd + Rr + C

Syntax: Operands: Program Counter:

(i) ADC Rd,Rr 0 d 31, 0 r 31 PC PC + 1

16-bit Opcode:

Status Register (SREG) Boolean Formula:


57/332

H: Rd3Rr3+Rr3R3+R3Rd3

Set if there was a carry from bit 3; cleared otherwise

S: NV, For signed tests.

V: Rd7Rr7R7+Rd7Rr7R7

Set if twos complement overflow resulted from the operation; cleared

otherwise.

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 R6 R5 R4 R3 R2 R1 R0

Set if the result is $00; cleared otherwise.

C: Rd7Rr7+Rr7R7+R7Rd7

Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

; Add R1:R0 to R3:R2

add r2,r0 ; Add low byte


58/332

adc r3,r1 ; Add with carry high byte

Words: 1 (2 bytes)

Cycles: 1

0001 11rd dddd rrrr

I T H S V N Z C

17

0856HAVR07/09

AVR Instruction Set

ADD Add without Carry

Description:

Adds two registers without the C Flag and places the result in the

destination register Rd.

Operation:

(i) Rd Rd + Rr



59/332

(i) ADD Rd,Rr 0 d 31, 0 r 31 PC PC + 1

16-bit Opcode:

Status Register (SREG) and Boolean Formula:

H: Rd3Rr3+Rr3R3+R3Rd3

Set if there was a carry from bit 3; cleared otherwise


V: Rd7Rr7R7+Rd7Rr7R7


otherwise.

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0


C: Rd7 Rr7 +Rr7 R7+ R7 Rd7




60/332

Example:

add r1,r2 ; Add r2 to r1 (r1=r1+r2)

add r28,r28 ; Add r28 to itself (r28=r28+r28)

Words: 1 (2 bytes)

Cycles: 1

0000 11rd dddd rrrr

I T H S V N Z C

18

0856HAVR07/09

AVR Instruction Set

ADIW Add Immediate to Word

Description:

Adds an immediate value (0 - 63) to a register pair and places the result in

the register pair. This instruction operates on the


61/332

upper four register pairs, and is well suited for operations on the pointer

registers.

This instruction is not available in all devices. Refer to the device specific

instruction set summary.

Operation:

(i) Rd+1:Rd Rd+1:Rd + K


(i) ADIW Rd+1:Rd,K d{24,26,28,30}, 0 K 63 PC PC + 1

16-bit Opcode:



V: Rdh7 R15


otherwise.

N: R15



62/332

Z: R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3

R2 R1 R0


C: R15 Rdh7


R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 = R15-R8, Rdl7-

Rdl0=R7-R0).

Example:

adiw r25:24,1 ; Add 1 to r25:r24

adiw ZH:ZL,63 ; Add 63 to the Z-pointer(r31:r30)

Words: 1 (2 bytes)

Cycles: 2

1001 0110 KKdd KKKK

I T H S V N Z C

19


63/332

0856HAVR07/09

AVR Instruction Set

AND Logical AND

Description:

Performs the logical AND between the contents of register Rd and register

Rr and places the result in the destination register

Rd.

Operation:

(i) Rd Rd Rr


(i) AND Rd,Rr 0 d 31, 0 r 31 PC PC + 1

16-bit Opcode:



V: 0

Cleared


64/332

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0



Example:

and r2,r3 ; Bitwise and r2 and r3, result in r2

ldi r16,1 ; Set bitmask 0000 0001 in r16

and r2,r16 ; Isolate bit 0 in r2

Words: 1 (2 bytes)

Cycles: 1

0010 00rd dddd rrrr

I T H S V N Z C

0

20


65/332

0856HAVR07/09

AVR Instruction Set

ANDI Logical AND with Immediate

Description:

Performs the logical AND between the contents of register Rd and a

constant and places the result in the destination register

Rd.

Operation:

(i) Rd Rd K


(i) ANDI Rd,K 16 d 31, 0 K 255 PC PC + 1

16-bit Opcode:



V: 0

Cleared


66/332

N: R7


Z: R7 R6 R5R4 R3 R2 R1 R0



Example:

andi r17,$0F ; Clear upper nibble of r17

andi r18,$10 ; Isolate bit 4 in r18

andi r19,$AA ; Clear odd bits of r19

Words: 1 (2 bytes)

Cycles: 1

0111 KKKK dddd KKKK

I T H S V N Z C

0

21


67/332

0856HAVR07/09

AVR Instruction Set

ASR Arithmetic Shift Right

Description:

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is

loaded into the C Flag of the SREG. This operation

effectively divides a signed value by two without changing its sign. The

Carry Flag can be used to round the result.

Operation:

(i)


(i) ASR Rd 0 d 31 PC PC + 1

16-bit Opcode:



V: NC (For N and C after the shift)


68/332

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0


C: Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.


Example:

ldi r16,$10 ; Load decimal 16 into r16

asr r16 ; r16=r16 / 2

ldi r17,$FC ; Load -4 in r17

asr r17 ; r17=r17/2

Words: 1 (2 bytes)

Cycles: 1

1001 010d dddd 0101

I T H S V N Z C


69/332

b7-------------------b0 C

22

0856HAVR07/09

AVR Instruction Set

BCLR Bit Clear in SREG

Description:

Clears a single Flag in SREG.

Operation:

(i) SREG(s) 0


(i) BCLR s 0 s 7 PC PC + 1

16-bit Opcode:


I: 0 if s = 7; Unchanged otherwise.


70/332

T: 0 if s = 6; Unchanged otherwise.

H: 0 if s = 5; Unchanged otherwise.

S: 0 if s = 4; Unchanged otherwise.

V: 0 if s = 3; Unchanged otherwise.

N: 0 if s = 2; Unchanged otherwise.

Z: 0 if s = 1; Unchanged otherwise.

C: 0 if s = 0; Unchanged otherwise.

Example:

bclr 0 ; Clear Carry Flag

bclr 7 ; Disable interrupts

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1sss 1000

I T H S V N Z C

23


71/332

0856HAVR07/09

AVR Instruction Set

BLD Bit Load from the T Flag in SREG to a Bit in Register

Description:

Copies the T Flag in the SREG (Status Register) to bit b in register Rd.

Operation:

(i) Rd(b) T


(i) BLD Rd,b 0 d 31, 0 b 7 PC PC + 1

16 bit Opcode:


Example:

; Copy bit

bst r1,2 ; Store bit 2 of r1 in T Flag

bld r0,4 ; Load T Flag into bit 4 of r0


72/332

Words: 1 (2 bytes)

Cycles: 1

1111 100d dddd 0bbb

I T H S V N Z C

24

0856HAVR07/09

AVR Instruction Set

BRBC Branch if Bit in SREG is Cleared

Description:

Conditional relative branch. Tests a single bit in SREG and branches

relatively to PC if the bit is cleared. This instruction

branches relatively to PC in either direction (PC - 63 destination PC +

64). The parameter k is the offset from PC and is

represented in twos complement form.

Operation:


73/332

(i) If SREG(s) = 0 then PC PC + k + 1, else PC PC + 1


(i) BRBC s,k 0 s 7, -64 k +63 PC PC + k + 1

PC PC + 1, if condition is false

16-bit Opcode:


Example:

cpi r20,5 ; Compare r20 to the value 5

brbc 1,noteq ; Branch if Zero Flag cleared

...

noteq:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true

1111 01kk kkkk ksss


74/332

I T H S V N Z C

25

0856HAVR07/09

AVR Instruction Set

BRBS Branch if Bit in SREG is Set

Description:

Conditional relative branch. Tests a single bit in SREG and branches

relatively to PC if the bit is set. This instruction



represented in twos complement form.

Operation:

(i) If SREG(s) = 1 then PC PC + k + 1, else PC PC + 1


(i) BRBS s,k 0 s 7, -64 k +63 PC PC + k + 1


75/332


16-bit Opcode:


Example:

bst r0,3 ; Load T bit with bit 3 of r0

brbs 6,bitset ; Branch T bit was set

...

bitset: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 00kk kkkk ksss

I T H S V N Z C

26

0856HAVR07/09


76/332

AVR Instruction Set

BRCC Branch if Carry Cleared

Description:

Conditional relative branch. Tests the Carry Flag (C) and branches

relatively to PC if C is cleared. This instruction branches

relatively to PC in either direction (PC - 63 destination PC + 64). The

parameter k is the offset from PC and is represented

in twos complement form. (Equivalent to instruction BRBC 0,k).

Operation:

(i) If C = 0 then PC PC + k + 1, else PC PC + 1


(i) BRCC k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:


77/332

add r22,r23 ; Add r23 to r22

brcc nocarry ; Branch if carry cleared

...

nocarry: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 01kk kkkk k000

I T H S V N Z C

27

0856HAVR07/09

AVR Instruction Set

BRCS Branch if Carry Set

Description:


78/332


relatively to PC if C is set. This instruction branches relatively

to PC in either direction (PC - 63 destination PC + 64). The parameter

k is the offset from PC and is represented

in twos complement form. (Equivalent to instruction BRBS 0,k).

Operation:

(i) If C = 1 then PC PC + k + 1, else PC PC + 1


(i) BRCS k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

cpi r26,$56 ; Compare r26 with $56

brcs carry ; Branch if carry set

...


79/332

carry: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 00kk kkkk k000

I T H S V N Z C

28

0856HAVR07/09

AVR Instruction Set

BREAK Break

Description:

The BREAK instruction is used by the On-chip Debug system, and is

normally not used in the application software. When

the BREAK instruction is executed, the AVR CPU is set in the Stopped

Mode. This gives the On-chip Debugger access to


80/332

internal resources.

If any Lock bits are set, or either the JTAGEN or OCDEN Fuses are

unprogrammed, the CPU will treat the BREAK instruction

as a NOP and will not enter the Stopped mode.



Operation:

(i) On-chip Debug system break.


(i) BREAK None PC PC + 1

16-bit Opcode:


Words: 1 (2 bytes)

Cycles: 1

1001 0101 1001 1000

I T H S V N Z C


81/332

29

0856HAVR07/09

AVR Instruction Set

BREQ Branch if Equal

Description:

Conditional relative branch. Tests the Zero Flag (Z) and branches relatively

to PC if Z is set. If the instruction is executed

immediately after any of the instructions CP, CPI, SUB or SUBI, the branch

will occur if and only if the unsigned or signed

binary number represented in Rd was equal to the unsigned or signed

binary number represented in Rr. This instruction



represented in twos complement form. (Equivalent to instruction BRBS

1,k).

Operation:


82/332

(i) If Rd = Rr (Z = 1) then PC PC + k + 1, else PC PC + 1


(i) BREQ k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

cp r1,r0 ; Compare registers r1 and r0

breq equal ; Branch if registers equal

...

equal: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 00kk kkkk k001


83/332

I T H S V N Z C

30

0856HAVR07/09

AVR Instruction Set

BRGE Branch if Greater or Equal (Signed)

Description:

Conditional relative branch. Tests the Signed Flag (S) and branches

relatively to PC if S is cleared. If the instruction is executed


will occur if and only if the signed binary

number represented in Rd was greater than or equal to the signed binary

number represented in Rr. This instruction



represented in twos complement form. (Equivalent to instruction BRBC

4,k).


84/332

Operation:

(i) If Rd Rr (NV = 0) then PC PC + k + 1, else PC PC + 1


(i) BRGE k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

cp r11,r12 ; Compare registers r11 and r12

brge greateq ; Branch if r11 r12 (signed)

...

greateq: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)




85/332

1111 01kk kkkk k100

I T H S V N Z C

31

0856HAVR07/09

AVR Instruction Set

BRHC Branch if Half Carry Flag is Cleared

Description:

Conditional relative branch. Tests the Half Carry Flag (H) and branches

relatively to PC if H is cleared. This instruction




5,k).

Operation:

(i) If H = 0 then PC PC + k + 1, else PC PC + 1


86/332


(i) BRHC k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

brhc hclear ; Branch if Half Carry Flag cleared

...

hclear: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 01kk kkkk k101

I T H S V N Z C


87/332

32

0856HAVR07/09

AVR Instruction Set

BRHS Branch if Half Carry Flag is Set

Description:

Conditional relative branch. Tests the Half Carry Flag (H) and branches

relatively to PC if H is set. This instruction branches




Operation:

(i) If H = 1 then PC PC + k + 1, else PC PC + 1


(i) BRHS k -64 k +63 PC PC + k + 1


16-bit Opcode:


88/332


Example:

brhs hset ; Branch if Half Carry Flag set

...

hset: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 00kk kkkk k101

I T H S V N Z C

33

0856HAVR07/09

AVR Instruction Set

BRID Branch if Global Interrupt is Disabled

Description:


89/332

Conditional relative branch. Tests the Global Interrupt Flag (I) and

branches relatively to PC if I is cleared. This instruction




7,k).

Operation:

(i) If I = 0 then PC PC + k + 1, else PC PC + 1


(i) BRID k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

brid intdis ; Branch if interrupt disabled

...


90/332

intdis: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 01kk kkkk k111

I T H S V N Z C

34

0856HAVR07/09

AVR Instruction Set

BRIE Branch if Global Interrupt is Enabled

Description:

Conditional relative branch. Tests the Global Interrupt Flag (I) and

branches relatively to PC if I is set. This instruction




91/332

represented in twos complement form. (Equivalent to instruction BRBS

7,k).

Operation:

(i) If I = 1 then PC PC + k + 1, else PC PC + 1


(i) BRIE k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

brie inten ; Branch if interrupt enabled

...

inten: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)




92/332

1111 00kk kkkk k111

I T H S V N Z C

35

0856HAVR07/09

AVR Instruction Set

BRLO Branch if Lower (Unsigned)

Description:


relatively to PC if C is set. If the instruction is executed


will occur if and only if the unsigned binary

number represented in Rd was smaller than the unsigned binary number

represented in Rr. This instruction branches relatively




93/332


Operation:

(i) If Rd < Rr (C = 1) then PC PC + k + 1, else PC PC + 1


(i) BRLO k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

eor r19,r19 ; Clear r19

loop: inc r19 ; Increase r19

...

cpi r19,$10 ; Compare r19 with $10

brlo loop ; Branch if r19 < $10 (unsigned)

nop ; Exit from loop (do nothing)

Words: 1 (2 bytes)


94/332



1111 00kk kkkk k000

I T H S V N Z C

36

0856HAVR07/09

AVR Instruction Set

BRLT Branch if Less Than (Signed)

Description:

Conditional relative branch. Tests the Signed Flag (S) and branches

relatively to PC if S is set. If the instruction is executed


will occur if and only if the signed binary number

represented in Rd was less than the signed binary number represented in

Rr. This instruction branches relatively to PC


95/332

in either direction (PC - 63 destination PC + 64). The parameter k is

the offset from PC and is represented in twos complement

form. (Equivalent to instruction BRBS 4,k).

Operation:

(i) If Rd < Rr (N V = 1) then PC PC + k + 1, else PC PC + 1


(i) BRLT k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

cp r16,r1 ; Compare r16 to r1

brlt less ; Branch if r16 < r1 (signed)

...

less: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)


96/332



1111 00kk kkkk k100

I T H S V N Z C

37

0856HAVR07/09

AVR Instruction Set

BRMI Branch if Minus

Description:

Conditional relative branch. Tests the Negative Flag (N) and branches

relatively to PC if N is set. This instruction branches




Operation:


97/332

(i) If N = 1 then PC PC + k + 1, else PC PC + 1


(i) BRMI k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

subi r18,4 ; Subtract 4 from r18

brmi negative ; Branch if result negative

...

negative: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 00kk kkkk k010


98/332

I T H S V N Z C

38

0856HAVR07/09

AVR Instruction Set

BRNE Branch if Not Equal

Description:

Conditional relative branch. Tests the Zero Flag (Z) and branches relatively

to PC if Z is cleared. If the instruction is executed


will occur if and only if the unsigned or

signed binary number represented in Rd was not equal to the unsigned or

signed binary number represented in Rr. This

instruction branches relatively to PC in either direction (PC - 63

destination PC + 64). The parameter k is the offset from

PC and is represented in twos complement form. (Equivalent to instruction

BRBC 1,k).


99/332

Operation:

(i) If Rd Rr (Z = 0) then PC PC + k + 1, else PC PC + 1


(i) BRNE k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

eor r27,r27 ; Clear r27

loop: inc r27 ; Increase r27

...

cpi r27,5 ; Compare r27 to 5

brne loop ; Branch if r275

nop ; Loop exit (do nothing)

Words: 1 (2 bytes)



100/332


1111 01kk kkkk k001

I T H S V N Z C

39

0856HAVR07/09

AVR Instruction Set

BRPL Branch if Plus

Description:

Conditional relative branch. Tests the Negative Flag (N) and branches

relatively to PC if N is cleared. This instruction




2,k).

Operation:


101/332

(i) If N = 0 then PC PC + k + 1, else PC PC + 1


(i) BRPL k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

subi r26,$50 ; Subtract $50 from r26

brpl positive ; Branch if r26 positive

...

positive: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 01kk kkkk k010


102/332

I T H S V N Z C

40

0856HAVR07/09

AVR Instruction Set

BRSH Branch if Same or Higher (Unsigned)

Description:


relatively to PC if C is cleared. If the instruction is executed

immediately after execution of any of the instructions CP, CPI, SUB or

SUBI the branch will occur if and only if the

unsigned binary number represented in Rd was greater than or equal to the

unsigned binary number represented in Rr.

This instruction branches relatively to PC in either direction (PC - 63

destination PC + 64). The parameter k is the offset

from PC and is represented in twos complement form. (Equivalent to

instruction BRBC 0,k).


103/332

Operation:

(i) If Rd Rr (C = 0) then PC PC + k + 1, else PC PC + 1


(i) BRSH k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:

subi r19,4 ; Subtract 4 from r19

brsh highsm ; Branch if r19 >= 4 (unsigned)

...

highsm: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)




104/332

1111 01kk kkkk k000

I T H S V N Z C

41

0856HAVR07/09

AVR Instruction Set

BRTC Branch if the T Flag is Cleared

Description:

Conditional relative branch. Tests the T Flag and branches relatively to PC

if T is cleared. This instruction branches relatively




Operation:

(i) If T = 0 then PC PC + k + 1, else PC PC + 1



105/332

(i) BRTC k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:


brtc tclear ; Branch if this bit was cleared

...

tclear: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 01kk kkkk k110

I T H S V N Z C

42


106/332

0856HAVR07/09

AVR Instruction Set

BRTS Branch if the T Flag is Set

Description:

Conditional relative branch. Tests the T Flag and branches relatively to PC

if T is set. This instruction branches relatively to

PC in either direction (PC - 63 destination PC + 64). The parameter k

is the offset from PC and is represented in twos

complement form. (Equivalent to instruction BRBS 6,k).

Operation:

(i) If T = 1 then PC PC + k + 1, else PC PC + 1


(i) BRTS k -64 k +63 PC PC + k + 1


16-bit Opcode:



107/332

Example:


brts tset ; Branch if this bit was set

...

tset: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 00kk kkkk k110

I T H S V N Z C

43

0856HAVR07/09

AVR Instruction Set

BRVC Branch if Overflow Cleared

Description:


108/332

Conditional relative branch. Tests the Overflow Flag (V) and branches

relatively to PC if V is cleared. This instruction branches




Operation:

(i) If V = 0 then PC PC + k + 1, else PC PC + 1


(i) BRVC k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:


brvc noover ; Branch if no overflow

...


109/332

noover: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



1111 01kk kkkk k011

I T H S V N Z C

44

0856HAVR07/09

AVR Instruction Set

BRVS Branch if Overflow Set

Description:

Conditional relative branch. Tests the Overflow Flag (V) and branches

relatively to PC if V is set. This instruction branches




110/332


Operation:

(i) If V = 1 then PC PC + k + 1, else PC PC + 1


(i) BRVS k -64 k +63 PC PC + k + 1


16-bit Opcode:


Example:


brvs overfl ; Branch if overflow

...

overfl: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)



111/332


1111 00kk kkkk k011

I T H S V N Z C

45

0856HAVR07/09

AVR Instruction Set

BSET Bit Set in SREG

Description:

Sets a single Flag or bit in SREG.

Operation:

(i) SREG(s) 1


(i) BSET s 0 s 7 PC PC + 1

16-bit Opcode:


112/332


I: 1 if s = 7; Unchanged otherwise.

T: 1 if s = 6; Unchanged otherwise.

H: 1 if s = 5; Unchanged otherwise.

S: 1 if s = 4; Unchanged otherwise.

V: 1 if s = 3; Unchanged otherwise.

N: 1 if s = 2; Unchanged otherwise.

Z: 1 if s = 1; Unchanged otherwise.

C: 1 if s = 0; Unchanged otherwise.

Example:

bset 6 ; Set T Flag

bset 7 ; Enable interrupt

Words: 1 (2 bytes)

Cycles: 1

1001 0100 0sss 1000

I T H S V N Z C


113/332

46

0856HAVR07/09

AVR Instruction Set

BST Bit Store from Bit in Register to T Flag in SREG

Description:

Stores bit b from Rd to the T Flag in SREG (Status Register).

Operation:

(i) T Rd(b)


(i) BST Rd,b 0 d 31, 0 b 7 PC PC + 1

16-bit Opcode:


T: 0 if bit b in Rd is cleared. Set to 1 otherwise.

Example:


114/332

; Copy bit


bld r0,4 ; Load T into bit 4 of r0

Words: 1 (2 bytes)

Cycles: 1

1111 101d dddd 0bbb

I T H S V N Z C

47

0856HAVR07/09

AVR Instruction Set

CALL Long Call to a Subroutine

Description:

Calls to a subroutine within the entire Program memory. The return address

(to the instruction after the CALL) will be stored


115/332

onto the Stack. (See also RCALL). The Stack Pointer uses a post-

decrement scheme during CALL.



Operation:

(i) PC k Devices with 16 bits PC, 128K bytes Program memory

maximum.

(ii) PC k Devices with 22 bits PC, 8M bytes Program memory maximum.

Syntax: Operands: Program Counter Stack:

(i) CALL k 0 k < 64K PC k STACK PC+2

SP SP-2, (2 bytes, 16 bits)

(ii) CALL k 0 k < 4M PC k STACK PC+2

SP SP-3 (3 bytes, 22 bits)

32-bit Opcode:


Example:


116/332

mov r16,r0 ; Copy r0 to r16

call check ; Call subroutine

nop ; Continue (do nothing)

...

check: cpi r16,$42 ; Check if r16 has a special value

breq error ; Branch if equal

ret ; Return from subroutine

...

error: rjmp error ; Infinite loop

Words : 2 (4 bytes)

Cycles : 4, devices with 16 bit PC

5, devices with 22 bit PC

Cycles XMEGA: 3, devices with 16 bit PC

4, devices with 22 bit PC

1001 010k kkkk 111k

kkkk kkkk kkkk kkkk


117/332

I T H S V N Z C

48

0856HAVR07/09

AVR Instruction Set

CBI Clear Bit in I/O Register

Description:

Clears a specified bit in an I/O Register. This instruction operates on the

lower 32 I/O Registers addresses 0-31.

Operation:

(i) I/O(A,b) 0


(i) CBI A,b 0 A 31, 0 b 7 PC PC + 1

16-bit Opcode:


Example:


118/332

cbi $12,7 ; Clear bit 7 in Port D

Words : 1 (2 bytes)

Cycles : 2

Cycles XMEGA: 1

Cycles ATtiny10: 1

1001 1000 AAAA Abbb

I T H S V N Z C

49

0856HAVR07/09

AVR Instruction Set

CBR Clear Bits in Register

Description:

Clears the specified bits in register Rd. Performs the logical AND between

the contents of register Rd and the complement

of the constant mask K. The result will be placed in register Rd.


119/332

Operation:

(i) Rd Rd ($FF - K)


(i) CBR Rd,K 16 d 31, 0 K 255 PC PC + 1

16-bit Opcode: (see ANDI with K complemented)



V: 0

Cleared

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0



Example:


120/332

cbr r16,$F0 ; Clear upper nibble of r16

cbr r18,1 ; Clear bit 0 in r18

Words: 1 (2 bytes)

Cycles: 1

I T H S V N Z C

0

50

0856HAVR07/09

AVR Instruction Set

CLC Clear Carry Flag

Description:

Clears the Carry Flag (C) in SREG (Status Register).

Operation:

(i) C 0



121/332

(i) CLC None PC PC + 1

16-bit Opcode:


C: 0

Carry Flag cleared

Example:

add r0,r0 ; Add r0 to itself

clc ; Clear Carry Flag

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1000 1000

I T H S V N Z C

0

51

0856HAVR07/09

AVR Instruction Set


122/332

CLH Clear Half Carry Flag

Description:

Clears the Half Carry Flag (H) in SREG (Status Register).

Operation:

(i) H 0


(i) CLH None PC PC + 1

16-bit Opcode:


H: 0

Half Carry Flag cleared

Example:

clh ; Clear the Half Carry Flag

Words: 1 (2 bytes)

Cycles: 1


123/332

1001 0100 1101 1000

I T H S V N Z C

0

52

0856HAVR07/09

AVR Instruction Set

CLI Clear Global Interrupt Flag

Description:

Clears the Global Interrupt Flag (I) in SREG (Status Register). The

interrupts will be immediately disabled. No interrupt will

be executed after the CLI instruction, even if it occurs simultaneously with

the CLI instruction.

Operation:

(i) I 0


(i) CLI None PC PC + 1


124/332

16-bit Opcode:


I: 0

Global Interrupt Flag cleared

Example:

in temp, SREG ; Store SREG value (temp must be defined

by user)

cli ; Disable interrupts during timed sequence

sbi EECR, EEMWE ; Start EEPROM write

sbi EECR, EEWE

out SREG, temp ; Restore SREG value (I-Flag)

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1111 1000

I T H S V N Z C

0


125/332

53

0856HAVR07/09

AVR Instruction Set

CLN Clear Negative Flag

Description:

Clears the Negative Flag (N) in SREG (Status Register).

Operation:

(i) N 0


(i) CLN None PC PC + 1

16-bit Opcode:


N: 0

Negative Flag cleared

Example:


126/332


cln ; Clear Negative Flag

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1010 1000

I T H S V N Z C

0

54

0856HAVR07/09

AVR Instruction Set

CLR Clear Register

Description:

Clears a register. This instruction performs an Exclusive OR between a

register and itself. This will clear all bits in the

register.

Operation:


127/332

(i) Rd RdRd


(i) CLR Rd 0 d 31 PC PC + 1

16-bit Opcode: (see EOR Rd,Rd)


S: 0

Cleared

V: 0

Cleared

N: 0

Cleared

Z: 1

Set


Example:


128/332

clr r18 ; clear r18

loop: inc r18 ; increase r18

...

cpi r18,$50 ; Compare r18 to $50

brne loop

Words: 1 (2 bytes)

Cycles: 1

0010 01dd dddd dddd

I T H S V N Z C

0 0 0 1

55

0856HAVR07/09

AVR Instruction Set

CLS Clear Signed Flag

Description:

Clears the Signed Flag (S) in SREG (Status Register).


129/332

Operation:

(i) S 0


(i) CLS None PC PC + 1

16-bit Opcode:


S: 0

Signed Flag cleared

Example:


cls ; Clear Signed Flag

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1100 1000

I T H S V N Z C


130/332

0

56

0856HAVR07/09

AVR Instruction Set

CLT Clear T Flag

Description:

Clears the T Flag in SREG (Status Register).

Operation:

(i) T 0


(i) CLT None PC PC + 1

16-bit Opcode:


T: 0

T Flag cleared


131/332

Example:

clt ; Clear T Flag

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1110 1000

I T H S V N Z C

0

57

0856HAVR07/09

AVR Instruction Set

CLV Clear Overflow Flag

Description:

Clears the Overflow Flag (V) in SREG (Status Register).

Operation:

(i) V 0


132/332


(i) CLV None PC PC + 1

16-bit Opcode:


V: 0

Overflow Flag cleared

Example:


clv ; Clear Overflow Flag

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1011 1000

I T H S V N Z C

0

58

0856HAVR07/09


133/332

AVR Instruction Set

CLZ Clear Zero Flag

Description:

Clears the Zero Flag (Z) in SREG (Status Register).

Operation:

(i) Z 0


(i) CLZ None PC PC + 1

16-bit Opcode:


Z: 0

Zero Flag cleared

Example:


clz ; Clear zero


134/332

Words: 1 (2 bytes)

Cycles: 1

1001 0100 1001 1000

I T H S V N Z C

0

59

0856HAVR07/09

AVR Instruction Set

COM Ones Complement

Description:

This instruction performs a Ones Complement of register Rd.

Operation:

(i) Rd $FF - Rd


(i) COM Rd 0 d 31 PC PC + 1


135/332

16-bit Opcode:


S: NV

For signed tests.

V: 0

Cleared.

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0

Set if the result is $00; Cleared otherwise.

C: 1

Set.


Example:

com r4 ; Take ones complement of r4


136/332

breq zero ; Branch if zero

...

zero: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1

1001 010d dddd 0000

I T H S V N Z C

01

60

0856HAVR07/09

AVR Instruction Set

CP Compare

Description:

This instruction performs a compare between two registers Rd and Rr.

None of the registers are changed. All conditional

branches can be used after this instruction.


137/332

Operation:

(i) Rd - Rr


(i) CP Rd,Rr 0 d 31, 0 r 31 PC PC + 1

16-bit Opcode:


H: Rd3 Rr3+ Rr3 R3 +R3 Rd3

Set if there was a borrow from bit 3; cleared otherwise


V: Rd7 Rr7 R7+ Rd7 Rr7 R7


otherwise.

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0



138/332

C: Rd7 Rr7+ Rr7 R7 +R7 Rd7

Set if the absolute value of the contents of Rr is larger than the absolute

value of Rd; cleared otherwise.

R (Result) after the operation.

Example:

cp r4,r19 ; Compare r4 with r19

brne noteq ; Branch if r4 r19

...

noteq: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1

0001 01rd dddd rrrr

I T H S V N Z C

61

0856HAVR07/09


139/332

AVR Instruction Set

CPC Compare with Carry

Description:

This instruction performs a compare between two registers Rd and Rr and

also takes into account the previous carry. None

of the registers are changed. All conditional branches can be used after this

instruction.

Operation:

(i) Rd - Rr - C


(i) CPC Rd,Rr 0 d 31, 0 r 31 PC PC + 1

16-bit Opcode:


H: Rd3 Rr3+ Rr3 R3 +R3 Rd3




140/332

V: Rd7 Rr7 R7+ Rd7 Rr7 R7


otherwise.

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0 Z

Previous value remains unchanged when the result is zero; cleared

otherwise.

C: Rd7 Rr7+ Rr7 R7 +R7 Rd7

Set if the absolute value of the contents of Rr plus previous carry is larger

than the absolute value of Rd; cleared

otherwise.


Example:

; Compare r3:r2 with r1:r0

cp r2,r0 ; Compare low byte


141/332

cpc r3,r1 ; Compare high byte

brne noteq ; Branch if not equal

...

noteq: nop ; Branch destination (do nothing)

0000 01rd dddd rrrr

I T H S V N Z C

62

0856HAVR07/09

AVR Instruction Set

Words: 1 (2 bytes)

Cycles: 1

63

0856HAVR07/09

AVR Instruction Set

CPI Compare with Immediate


142/332

Description:

This instruction performs a compare between register Rd and a constant.

The register is not changed. All conditional

branches can be used after this instruction.

Operation:

(i) Rd - K


(i) CPI Rd,K 16 d 31, 0 K 255 PC PC + 1

16-bit Opcode:


H: Rd3 K3+ K3 R3+ R3 Rd3



V: Rd7 K7 R7 +Rd7 K7 R7


otherwise.


143/332

N: R7


Z: R7 R6 R5 R4 R3 R2 R1 R0


C: Rd7 K7 +K7 R7+ R7 Rd7

Set if the absolute value of K is larger than the absolute value of Rd;

cleared otherwise.


Example:

cpi r19,3 ; Compare r19 with 3

brne error ; Branch if r193

...

error: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1

0011 KKKK dddd KKKK


144/332

I T H S V N Z C

64

0856HAVR07/09

AVR Instruction Set

CPSE Compare Skip if Equal

Description:

This instruction performs a compare between two registers Rd and Rr, and

skips the next instruction if Rd = Rr.

Operation:

(i) If Rd = Rr then PC PC + 2 (or 3) else PC PC + 1


(i) CPSE Rd,Rr 0 d 31, 0 r 31 PC PC + 1, Condition false - no

skip

PC PC + 2, Skip a one word instruction

PC PC + 3, Skip a two word instruction


145/332

16-bit Opcode:


Example:

inc r4 ; Increase r4

cpse r4,r0 ; Compare r4 to r0

neg r4 ; Only executed if r4r0

nop ; Continue (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false (no skip)

2 if condition is true (skip is executed) and the instruction skipped is 1 word

3 if condition is true (skip is executed) and the instruction skipped is 2

words

0001 00rd dddd rrrr

I T H S V N Z C

65


146/332

0856HAVR07/09

AVR Instruction Set

DEC Decrement

Description:

Subtracts one -1- from the contents of register Rd and places the result in

the destination register Rd.

The C Flag in SREG is not affected by the operation, thus allowing the

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