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TPS2105
IN1
IN2
EN
5 V VCC
5 V VAUX
Control Signal
LOAD5 V
HoldupCapacitor
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TPS2105-EPSLVSCH2 –JULY 2014
TPS2105-EP VAUX Power-Distribution Switch1 Features 2 Applications1• Dual-Input, Single-Output MOSFET Switch With • Notebook and Desktop PCs
No Reverse Current Flow (No Parasitic Diodes) • Cell phone, Palmtops, and PDAs• IN1: 250-mΩ, 500-mA N-Channel; 18-µA Supply • Battery Management
Current3 Description• IN2: 1.3-mΩ, 100-mA P-Channel; 0.75-µA Supply
Current (VAUX Mode) The TPS2105 is a dual-input, single-output powerswitch designed to provide uninterrupted output• Advanced Switch Control Logicvoltage when transitioning between two independent• CMOS and TTL Compatible Enable Input power supplies. Both devices combine one N-channel
• Controlled Rise, Fall, and Transition Times (250 mΩ) and one P-channel (1.3-Ω) MOSFET with asingle output. The P-channel MOSFET (IN2) is used• 2.7-V to 5.5-V Operating Rangewith auxiliary power supplies that deliver lower• SOT-23-5 Packagecurrent for standby modes. The N-channel MOSFET
• 2-kV Human Body Model, 750-V Charged Device (IN1) is used with a main power supply that deliversModel, 200-V Machine-Model ESD Protection higher current required for normal operation. Low on-
resistance makes the N-channel the ideal path for• Supports Defense, Aerospace, and Medicalhigher main supply current when power-supplyApplicationsregulation and system voltage drops are critical.– Controlled Baseline When using the P-channel MOSFET, quiescent
– One Assembly and Test Site current is reduced to 0.75 µA to decrease thedemand on the standby power supply. The MOSFETs– One Fabrication Sitein the TPS2105 do not have the parasitic diodes,– Available in Military (–55°C to 125°C)typically found in discrete MOSFETs, therebyTemperature Range preventing back-flow current when the switch is off.
– Extended Product Life CycleDevice Information(1)– Extended Product-Change Notification
ORDER NUMBER PACKAGE BODY SIZE (NOM)– Product TraceabilityTPS2105MDBVREP SOT-23 (5) 2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2105-EPSLVSCH2 –JULY 2014 www.ti.com
Table of Contents7.2 Functional Block Diagram ......................................... 91 Features .................................................................. 17.3 Feature Description................................................... 92 Applications ........................................................... 17.4 Device Functional Modes ....................................... 103 Description ............................................................. 1
8 Application and Implementation ........................ 114 Revision History..................................................... 28.1 Application Information............................................ 115 Pin Configuration and Functions ......................... 38.2 Typical Application .................................................. 116 Specifications......................................................... 4
9 Power Supply Recommendations ...................... 146.1 Absolute Maximum Ratings ...................................... 410 Layout................................................................... 146.2 Handling Ratings....................................................... 4
10.1 Layout Guidelines ................................................. 146.3 Recommended Operating Conditions....................... 410.2 Layout Examples................................................... 156.4 Thermal Information .................................................. 4
11 Device and Documentation Support ................. 176.5 Electrical Characteristics........................................... 511.1 Trademarks ........................................................... 176.6 Switching Characteristics .......................................... 611.2 Electrostatic Discharge Caution............................ 176.7 Typical Characteristics .............................................. 711.3 Glossary ................................................................ 177 Detailed Description .............................................. 9
12 Mechanical, Packaging, and Orderable7.1 Overview ................................................................... 9Information ........................................................... 17
4 Revision History
DATE VERSION NOTESJuly 2014 * Initial Release
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GND
IN2
IN1
OUT
EN 1
2
3
5
4
TPS2105
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
5 Pin Configuration and Functions
5-Pin SOTDBV Package
(Top View)
Pin FunctionsPIN
I/O DESCRIPTIONNAME NO.EN 1 I Active-high enable for IN1-OUT switchGND 2 I GroundIN1 (1) 5 I Main input voltage, NMOS drain (250 mΩ), requires 0.22-µF bypassIN2 (1) 3 I Auxiliary input voltage, PMOS drain (1.3 Ω), requires 0.22-µF bypassOUT 4 O Power switch output
(1) Unused INx should not be grounded.
Table 1. Function TableTPS2105
VIN1 VIN2 EN OUT0 V 0 V XX (1) GND0 V 5 V h GND5 V 0 V h VIN15 V 5 V h VIN10 V 5 V l VIN25 V 0 V l VIN25 V 5 V l VIN2
(1) XX = Don't care
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6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITVI(IN1) Input voltage (2) –0.3 6 VVI(IN2) Input voltage (2) –0.3 6 V
Input voltage, VI at EN (2) –0.3 6 VVO Output voltage (2) –0.3 6 VIO(IN1) Continuous output current 700 mAIO(IN2) Continuous output current 140 mA
Continuous total power dissipation See Thermal InformationTJ Operating virtual junction temperature –55 150 °C
Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 s 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
6.2 Handling RatingsMIN MAX UNIT
Tstg Storage temperature range –65 150 °CHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –2000 2000
ElectrostaticV(ESD) Machine model (MM) ESD stress voltage –200 200 VdischargeCharged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –750 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)
MIN MAX UNITVI(INx) Input voltage 2.7 5.5 V
Input voltage, VI at EN 0 5.5 VIO(IN1) Continuous output current 500 mAIO(IN2) Continuous output current 100 (1) mATJ Operating virtual junction temperature –55 125 °C
(1) The device can deliver up to 220 mA at IO(IN2). However, operation at the higher current levels results in greater voltage drop across thedevice, and greater voltage droop when switching between IN1 and IN2.
6.4 Thermal InformationTPS2105-EP
THERMAL METRIC (1) UNITDBV (5 PINS)
RθJA Junction-to-ambient thermal resistance 208.7RθJC(top) Junction-to-case (top) thermal resistance 122.9RθJB Junction-to-board thermal resistance 36.7
°C/WψJT Junction-to-top characterization parameter 14.2ψJB Junction-to-board characterization parameter 35.8RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Continuous Juction Temperature, T J (°C)
Estim
ate
d L
ife (
Yea
rs)
80 85 90 95 100 105 110 115 120 125 130 135 140 145 1501
2
3
4
5
7
10
20
30
40
50
70
100
D013
Electromigration IN1 (500 mA)Electromigration IN2 (100 mA)WB Failure Mode
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
6.5 Electrical CharacteristicsOver recommended operating range (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER SWITCH
IN1-OUT, VI(IN1) = 5.5 V, VI(IN2) = 0 V 250 435 mΩrDS(on) On-state resistance
IN2-OUT, VI(IN2) = 5.5 V, VI(IN1) = 0 V 1.3 2.4 ΩENABLE INPUTVIH High-level input voltage 2.7 V ≤ VI(INx) ≤ 5.5 V 2 VVIL Low-level input voltage 2.7 V ≤ VI(INx) ≤ 5.5 V 0.8 VII Input current EN = 0 V or EN = VI(INx) –0.65 0.65 µASUPPLY CURRENT
EN = L, IN2 selected 0.75 1.5 µAII Supply current
EN = H, IN1 selected 18 35 µA
SPACE
(1) Wirebond life = Time at temperature with or without bias(2) Electromigration fail mode = Time at temperature with bias(3) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).(4) The predicted operating lifetime versus junction temperature is based on reliability modeling and available
qualification data.
Figure 1. Predicted Lifetime Derating Chart for TPS2105-EP
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5
tPLH
tPHL
EN
VO
EN
VO
50%
10%
VI
GNDGND
V I
90%
50%
90%
10%VO
GND
VI
tr t f
Propagation Delay Time, Low-to-High-Level Output Propagation Delay Time, High-to–Low-Level Output
Rise/Fall Time
ton
toff
EN
VO
EN
VO
50%
10%
VI
GNDGND
V I
90%
50%
Turnon Transition Time Turnoff Transition Time
OUT
CLIO
LOAD CIRCUIT
TPS2105-EPSLVSCH2 –JULY 2014 www.ti.com
6.6 Switching CharacteristicsTJ = 25°C, VI(IN1) = VI(IN2) = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITCL = 1 µF, IL = 500 mA 340
IN1-OUT VI(IN2) = 0 CL = 10 µF, IL = 500 mA 340CL = 1 µF, IL = 100 mA 312
tr Output rise time µsCL = 1 µF, IL = 100 mA 3.4
IN2-OUT VI(IN1) = 0 CL = 10 µF, IL = 100 mA 34CL = 1 µF, IL = 10 mA 3.5CL = 1 µF, IL = 500 mA 6
IN1-OUT VI(IN2) = 0 CL = 10 µF, IL = 500 mA 108CL = 1 µF, IL = 100 mA 8
tf Output fall time µsCL = 1 µF, IL = 100 mA 100
IN2-OUT VI(IN1) = 0 CL = 10 µF, IL = 100 mA 990CL = 1 µF, IL = 10 mA 1000
IN1-OUT VI(IN2) = 0 55Propagation delay time,tPLH CL = 10 µF, IL = 100 mA µslow-to-high output IN2-OUT VI(IN1) = 0 1IN1-OUT VI(IN2) = 0 1.5Propagation delay time,tPHL CL = 10 µF, IL = 100 mA µshigh-to-low output IN2-OUT VI(IN1) = 0 50
Figure 2. Test Circuit and Voltage Waveforms
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0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 100 200 300 400 500
Inru
sh C
urre
nt (
A)
Output Capacitance (�F) C006
0
0.2
0.4
0.6
0.8
1
0.01 0.1 1 10 100
Out
put
Vol
tage
Dro
op (
V)
Output Current (mA) C005
CL = 1 �F
CL = 10 �F
CL = 100 �F
CL = 47 �F
CL = 220 �F
1
10
100
1000
10000
0.01 0.1 1 10 100 1000
Fal
l Tim
e (�
s)
Output Current (mA) C003
CL = 1 �F
CL = 10 �F
CL = 47 �F
CL = 100 �F
0.1
1
10
100
1000
0.01 0.1 1 10 100
Fal
l Tim
e (�
s)
Output Current (mA) C004
CL = 1 �F
CL = 100 �F
CL = 47 �F
CL = 10 �F
250
280
310
340
370
400
0.01 0.1 1 10 100 1000
Ris
e T
ime
(�s)
Output Current (mA) C001
CL = 1 �F
CL = 10 �F
CL = 47 �F
CL = 100 �F
1
10
100
1000
0 10 20 30 40 50 60 70 80 90 100
Ris
e T
ime
(�s)
Output Current (mA) C002
CL = 1 �F
CL = 10 �F
CL = 47 �F
CL = 100 �F
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
6.7 Typical Characteristics
VI(IN1) = 0 V VI(IN2) = 5 V TJ = 25°CVI(IN1) = 5 V VI(IN2) = 0 V TJ = 25°C
Figure 4. IN2 Switch Rise Time vs Output CurrentFigure 3. IN1 Switch Rise Time vs Output Current
VI(IN1) = 5 V VI(IN2) = 0 V TJ = 25°C VI(IN1) = 0 V VI(IN2) = 5 V TJ = 25°C
Figure 5. IN1 Switch Fall Time vs Output Current Figure 6. IN2 Switch Fall Time vs Output Current
VI(IN1) = 5 V VI(IN2) = 5 V TJ = 25°C VI(IN1) = 5 V VI(IN2) = 0 V RL = 10 ΩIf switching from IN1 to IN2, the voltage droop is much smaller. TJ = 25°CThus, choose the load capacitance according to Figure 6.
Figure 7. Output Voltage Droop vs Output Current When Figure 8. Inrush Current vs Output CapacitanceOutput is Switched from IN2 to IN1
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Junction Temperature (°C)
IN1-O
UT
On-S
tate
Resis
tance (
mΩ
)
-75 -50 -25 0 25 50 75 100 125 150 175160
170
180
190
200
210
220
230
240
250
260
270
280
D008
2.7 V3.3 V4.0 V5.0 V5.5 V
Junction Temperature (°C)
IN2-O
UT
On-S
tate
Resis
tance (
Ω)
-75 -50 -25 0 25 50 75 100 125 150 1750.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
D007
2.7 V3.3 V4.0 V5.0 V5.5 V
Junction Temperature (°C)
Supp
ly C
urr
ent (µ
A)
-75 -50 -25 0 25 50 75 100 125 150 1750.18
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
D004
2.7 V3.3 V4.0 V5.0 V5.5 V
Junction Temperature (°C)
Supp
ly C
urr
ent (µ
A)
-75 -50 -25 0 25 50 75 100 125 150 1750.15
0.175
0.2
0.225
0.25
0.275
0.3
0.325
0.35
0.375
0.4
0.425
0.45
0.475
0.5
D006
2.7 V3.3 V4.0 V5.0 V5.5 V
Junction Temperature (°C)
Su
pp
ly C
urr
en
t (µ
A)
-75 -50 -25 0 25 50 75 100 125 150 1755
7.5
10
12.5
15
17.5
20
22.5
25
27.5
30
D003
2.7 V3.3 V4.0 V5.0 V5.5 V
Junction Temperature (°C)
Su
pp
ly C
urr
en
t (µ
A)
-75 -50 -25 0 25 50 75 100 125 150 1750.2
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.3
0.31
0.32
0.33
0.34
0.35
D005
2.7 V3.3 V4.0 V5.0 V5.5 V
TPS2105-EPSLVSCH2 –JULY 2014 www.ti.com
Typical Characteristics (continued)
Figure 9. IN1 Supply Current vs Junction Temperature Figure 10. IN1 Supply Current vs Junction Temperature(IN1 Enabled) (IN1 Disabled)
Figure 11. IN2 Supply Current vs Junction Temperature Figure 12. IN2 Supply Current vs Junction Temperature(IN2 Enabled) (IN2 Disabled)
Figure 13. IN1-Out On-State Resistance vs Junction Figure 14. IN2-Out On-State Resistance vs JunctionTemperature Temperature
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VCCSelect
Driver
GND
OUT
SW2
1.3 Ω
SW1
250 mΩ
Driver
IN1
EN
IN2
Discharge
Circuit
PulldownCircuit
ChargePump
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
7 Detailed Description
7.1 OverviewThe TPS2105 is a dual-input, single-output power switch designed to provide uninterrupted output voltage whentransitioning between two independent power supplies.
The device combines one N-channel (250-m) MOSFET with a single output. The P-channel MOSFET (IN2) isused with auxiliary power supplies that deliver lower current for standby modes. The N-channel MOSFET (IN1) isused with a main power supply that delivers higher current required for normal operation.
The low on-resistance makes the N-channel the ideal path for higher main supply current when power-supplyregulation and system voltage drops are critical. When using the P-channel MOSFET, quiescent current isreduced to 0.75 µA to decrease the demand on the standby power supply.
The MOSFETs in the device do not have the parasitic diodes, typically found in discrete MOSFETs, therebypreventing back-flow current when the switch is off.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Power Switches
7.3.1.1 N-Channel MOSFETThe IN1-OUT N-channel MOSFET power switch has a typical on-resistance of 250 mΩ at 5-V input voltage andis configured as a high-side switch.
7.3.1.2 P-Channel MOSFETThe IN2-OUT P-channel MOSFET power switch has a typical on-resistance of 1.3 Ω at 5-V input voltage and isconfigured as a high-side switch. When operating, the P-channel MOSFET quiescent current is reduced totypically 0.75 µA.
7.3.1.3 Charge PumpAn internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requiresvery little supply current.
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Feature Description (continued)7.3.1.4 DriverThe driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surgesand reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry thatcontrols the rise times and fall times of the output voltage.
7.3.1.5 EnableThe logic enable turns on the IN2-OUT power switch when a logic low is present on EN. A logic high on ENrestores bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input iscompatible with both TTL and CMOS logic levels.
7.4 Device Functional Modes
7.4.1 Operation With EN ControlThe logic enable turns on the IN1-OUT power switch when a logic high is present on EN. Also, a logic lowpresent on EN turns off the IN1-OUT and turns on the IN2-OUT power switch.
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EN
IN1
IN2
OUT
GND5 V VAUX
5 V VCC
CardBus or System Controller
TPS2105
0.22 µF
0.22 µF
1 µF xx µF
5 V
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
8 Application and Implementation
8.1 Application InformationThe TPS2105 is a dual-input, single-output power switch designed to provide uninterrupted output voltage whentransitioning between two independent power supplies.
8.2 Typical Application
Figure 15. Typical Application Schematic
8.2.1 Design RequirementsFor this design example, use the following as the input parameters.
Table 2. Design ParametersDESIGN PARAMETER EXAMPLE VALUE
Input voltage range, VI(IN1) 5 VInput voltage range, VI(IN2) 5 V
Output voltage 5 VContinuous output current, IO 100 mA
Output capacitor, CL 220 µF
8.2.2 Detailed Design Procedure
8.2.2.1 Step-by-Step Design ProcedureTo begin the design process, the designer must decide upon a few parameters. The designer needs to know thefollowing:• Input voltage range, VI(IN1)• Input voltage range, VI(IN2)• Output voltage• Continuous output current• Output capacitance
8.2.2.2 Power-Supply ConsiderationsTI recommends a 0.22-µF ceramic bypass capacitor between IN and GND, close to the device. The outputcapacitor should be chosen based on the size of the load during the transition of the switch. TI recommends a220-µF capacitor for 100-mA loads. Typical output capacitors (xx µF, shown in Figure 15) required for a givenload can be determined from Figure 7, which shows the output voltage droop when output is switched from IN2to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally, bypassingthe output with a 1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.
8.2.2.3 Switch TransitionThe N-channel MOSFET on IN1 uses a charge pump to create the gate-drive voltage, which gives the IN1 switcha rise time of approximately 0.4 ms. The P-channel MOSFET on IN2 has a simpler drive circuit that allows a risetime of approximately 4 µs. Because the device has two switches and a single enable pin, these rise times areseen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limitthe surge currents seen by the power supply during switching.Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11
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8.2.2.4 Thermal ProtectionThermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuitfaults are present for extended periods of time. The increased dissipation causes the junction temperature to riseto dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts it off atapproximately 145°C (TJ). The switch remains off until the junction temperature has dropped approximately 10°C.The switch continues to cycle in this manner until the load fault or input power is removed.
8.2.2.5 Undervoltage LockoutAn undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up.Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This functionfacilitates the design of hot-insertion systems that may not have the capability to turn off the power switch beforeinput power is removed. Upon reinsertion, the power switch is turned on with a controlled rise time to reduce EMIand voltage overshoots.
8.2.2.6 Power Dissipation and Junction TemperatureThe low on-resistance on the N-channel MOSFET allows small surface-mount packages, such as SOIC, to passlarge currents. The thermal resistances of these packages are high compared to those of power packages; it is agood design practice to check power dissipation and junction temperature. First, find ron at the input voltage andoperating temperature. As an initial estimate, use the highest operating ambient temperature of interest and readron from Figure 13 or Figure 14. Next calculate the power dissipation using:
PD = ron × I2 (1)
Finally, calculate the junction temperature:TJ = PD × RθJA + TA
where• TA = Ambient temperature• RθJA = Thermal resistance (2)
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation using the calculated value as the new estimate. Two or three iterations are generallysufficient to obtain a reasonable answer.
8.2.2.7 ESD ProtectionAll TPS2105 pins incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model, 750-VCDM, and 200-V machine-model discharge as defined in MIL-STD-883C.
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C015
Time = 10 �s/div
EN (2 V/div)
VO (2 V/div)
C016
Time = 50 �s/div
EN (2 V/div)
VO (2 V/div)
C013
Time = 200 �s/div
EN (2 V/div)
VO (2 V/div)
C014
Time = 2 �s/div
EN (2 V/div)
VO (2 V/div)
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
8.2.3 Application Curves
VI(IN1) = 0 V VI(IN2) = 5 V CL = 1 µF VI(IN1) = 5 V VI(IN2) = 0 V CL = 1 µFRL = 50 Ω RL = 50 Ω
Figure 16. Propagation Delay and Rise Time With Figure 17. Propagation Delay and Rise Time With1-µF Load, IN2 Turnon 1-µF Load, IN1 Turnon
VI(IN1) = 0 V VI(IN2) = 5 V CL = 1 µF VI(IN1) = 5 V VI(IN2) = 0 V CL = 1 µFRL = 50 Ω RL = 50 Ω
Figure 18. Propagation Delay and Fall Time With Figure 19. Propagation Delay and Fall Time With1-µF Load, IN2 Turnoff 1-µF Load, IN1 Turnoff
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.7 to 5.5 V. A 0.22-μF ceramicbypass capacitor is needed between IN and GND; TI recommends placing the capacitor close to the device. Theoutput capacitor should be chosen based on the size of the load during the transition of the switch. TIrecommends a 220-μF capacitor for 100-mA loads. Adding a 1-μF ceramic bypass capacitor at the output canhelp to improve the immunity of the device to short-circuit transients.
TPS2105-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor. The value of aceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. Thecapacitance variations due to temperature can be minimized by selecting a dielectric material that is stable overtemperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because theyhave a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must alsobe selected with the DC bias taken into account. Ceramic capacitors lose capacitance when a DC bias is appliedacross the capacitor. This capacitance loss is due to the polarization of the ceramic material. The capacitanceloss is not permanent; after a large DC bias is applied, reducing the DC bias reduces the degree of polarizationand capacitance increases. The capacitance value of a capacitor decreases as the DC bias across a capacitorincreases.
All tantalum capacitors have tantalum (Ta) particles sintered together to form an anode. The cathode materialcan either be the traditional MnO2 or a conductive polymer. Because MnO2 is actually a semiconductor, it has avery high amount of resistance associated with it. A characteristic of this material is that as temperature changes,so does its conductivity. So MnO2-based Tantalum capacitors have relatively high ESR and that ESR shiftssignificantly across the operational temperature range.
However, polymer-based cathodes use a highly-conductive polymer material. Because the material is inherentlyconductive, tantalum-polymers have a relatively-low ESR compared to their MnO2 counterparts in the samevoltage and capacitance ranges.
All tantalum capacitors have a voltage derating factor associated with them. Because the polymer material putsless stress on the tantalum-pentoxide dielectric during reflow soldering, more voltage can be applied comparedto a MnO2-based tantalum. For polymer-based capacitors, TI recommends 20% derating. Whereas the MnO2-based tantalum capacitors require 50% or higher derating. Refer to the capacitor vendor data sheet for moredetails regarding the derating guidelines.
10 Layout
10.1 Layout Guidelines• The IN1 and OUT pins of the TPS2105-EP can carry up to 500 mA, so trace to these pins should have short
length and wider traces to minimize the voltage drop to the load.• Both the IN1 and IN2 pins should be bypassed to ground with a low-ESR ceramic bypass capacitor. The
typical recommended bypass capacitance is 0.22-µF ceramic capacitor.• A bypass capacitor and a load capacitor are needed on the output terminal.• TI recommends a 220-µF output load capacitor for 100-mA loads.• Locating the 1-µF ceramic bypass capacitor at the output can improve the immunity of the device to short-
circuit transients.• The GND terminal should be tied to the PCB ground plane at the terminal of the DUT.
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Enable Main Input, Input 1
Auxiliary Input,
Input 2 Output
Ground
Bypass Capacitors
C1 and C2
Output Capacitors
C3 and C4
EN
GND
IN2
IN1
OUT
DUT Area, Pin 1 located on top left.
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
10.2 Layout Examples
Figure 20. Input and Output Capacitors and DUT Area
Figure 21. Enable, Input, Output, and Ground Pins
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15
TPS2105-EPSLVSCH2 –JULY 2014 www.ti.com
Layout Examples (continued)
Figure 22. Schematics Diagram
Table 3. Component DescriptionsPART DESCRIPTIONC1, C2 0.22 µF, size 0805
C3 1 µF, size 0805C4 220 µF, tantalum capacitorsU1 TPS2105MDBVREP
TP_EN, TP_IN1, TP_IN2, TP_OUT, TP_GND Test point, through hole
16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
TPS2105-EPwww.ti.com SLVSCH2 –JULY 2014
11 Device and Documentation Support
11.1 TrademarksAll trademarks are the property of their respective owners.
11.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
11.3 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
TPS2105MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 PD9M
V62/14616-01XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 PD9M
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2105-EP :
• Catalog: TPS2105
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
TPS2105MDBVREP SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2105MDBVREP SOT-23 DBV 5 3000 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
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