WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Trading Off Dependability and Cost for Trading Off Dependability and Cost for NanoscaleNanoscale High Performance High Performance
Microprocessors: Microprocessors: The Clock Distribution ProblemThe Clock Distribution Problem
Cecilia MetraARCES - DEIS – University of Bologna
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Scaling of Microelectronic Technology
Courtesy of Intel Corporation Intel Techn. Journal, 2007
Scaling of microelectronic technology:↑ IC complexity and ↑ IC performance.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
But scaling comes together with:↑ IC complexity ↑ # of switching elements↑ power supply noise↑ operation frequency time margins ↓↑ likelihood of fabrication defects↑ entity of on-die process variations
↑ difficulties in ensuring limited skew, jitter and correct duty cycle for all clock signals of
a synchronous system
Scaling and Clock Due Dependability RisksScaling and Clock Due Dependability Risks
↓ System Dependability
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Clock DistributionClock DistributionComplex network, spreading out throughout the whole chip (horizontally and vertically).
S. Tam, S. Rusu, U.N. Desai, R. Kim, J. Zhang, I. Young, “Clock Generation and Distribution for the First IA-64 Microprocessor", IEEE J. of Solid-State Circuits, Vol. 35, No 11, pp. 1545 - 1552 , 2000.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Clock CompensationClock Compensation
ODCS (On Die Clock Shrink):intended to compensate duty cycle variations
(mainly due to parameter variations) at the PLL output
DSK (DeSKew buffers):intended to compensate skew (mainly due to
parameter variations) at the global clock level
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DSK DSK ExampleExample: Pentium: Pentium®®44Intel™ Pentium®4example:
PD: Phase Detectors
DB: programmable Delay Buffers, whose programming bits can be fixed permanently
N.A. Kurd, J.S. Barkatullah, R.O. Dizon, T.D. Fletcher, P.D. Madland, “A Multigigahertz Clocking Scheme for the Pentium® 4 Microprocessor”, IEEE J. of Solid State Circuits, Vol. 36, No. 11, Nov. 2001, pp. 1647-1653.
DB47
DB1
DB2
DB3
PDDB46
PD
To TestAccess Port
PD
PD
PhaseDetectors
BinaryDistrib-utionTrees
programmable DelayDomain Buffer
To TestAccess Port
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DSK DSK ExampleExample: Pentium: Pentium®®44 ((cntcnt’’dd))Programmable Delay Buffer:
N.A. Kurd, J.S. Barkatullah, R.O. Dizon, T.D. Fletcher, P.D. Madland, “A Multigigahertz Clocking Scheme for the Pentium® 4 Microprocessor”, IEEE J. of Solid State Circuits, Vol. 36, No. 11, Nov. 2001, pp. 1647-1653.
3-bi
t Con
trol
Reg
iste
r
TapClock
iScanDataIn
domain_clk_disable#
d0
d1
d2
OutputClk
3 to
8 de
code
r
s0
s1
s2
s7
s0
s1
s2
s7
s<7:0>
Early Clock
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DSK DSK ExampleExample: : ItaniumItanium®® -- 1st 1st gengenDSK architecture:
DSK local controller:
S. Tam, S. Rusu, U.N. Desai, R. Kim, J. Zhang, I. Young, “Clock Generation and Distribution for the First IA-64 Microprocessor”, IEEE J. of Solid-State Circuits, Vol. 35, Nov. 2000, pp. 1545-1552.
Local Controller
Regional
Clock Grid
RCD
RCD
DelayCircuit
Deskew Buffer
Global Clock
TAP I/F
Ref. Clock
Digital Low-Pass FilterPhaseDetector
16-to-1Counter
ReferenceClock
FeedbackClock
Enable
To DeskewBuffer Register
Lead / Lag
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DSK DSK ExampleExample: : ItaniumItanium®® -- 1st 1st gengen ((cntcnt’’dd))
Variable Delay Circuit:
S. Tam, S. Rusu, U.N. Desai, R. Kim, J. Zhang, I. Young, “Clock Generation and Distribution for the First IA-64 Microprocessor”, IEEE J. of Solid-State Circuits, Vol. 35, Nov. 2000, pp. 1545-1552.
Input
20TAP I/F
20-bit Delay Control Register
Enable
Output
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DSK DSK ExampleExample: : ItaniumItanium®® -- 2nd 2nd gengen
Variable Delay Circuit:
F. E. Anderson, J. S. Wells, E. Z. Berta, “The Core Clock System on the Next-Generation ItaniumTM Microprocessor”, in Proc. of IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers (ISSCC 2002), Vol. 2, 2002, pp. 110 – 424.
2
4x 2x 1x
4x 2x 1x
Fine control
Coarse control
2
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DSK DSK ExampleExample: : ItaniumItanium®® -- 3rd 3rd gengen
Variable Delay Circuit (for fine delay adjustment):
S. Tam, R. Limaye, U. Desai, “Clock Generation and Distribution for the 130-nm Itanium 2 Processor® with 6-MB On-Die L3 Cache”, IEEE J. of Solid-State Circuits, Vol. 39, No. 4, April 2004, pp. 636-642.
Vin +Vout +
Vout -Vin -
n4 n3 n2 n1 n0ZN4 ZN3 ZN2 ZN1 ZN0
ZP4 ZP3 ZP2 ZP1 ZP0p4 p3 p2 p1 p0
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Attempts at Clock CorrectnessAttempts at Clock CorrectnessDeSKew strategies intended to compensate skew
(mainly due to parameter variations) at the global clock level
But are parameter variations the only attempt at clock signal correctness ?
Or can clock signals get also (directly/indirectly) involved by faults occurring during fabrication, or
in the field ?
And how this will change with technology scaling ?
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can Clock Signals Get Can Clock Signals Get Directly Involved by Faults ?Directly Involved by Faults ?
Inductive Fault Analysis (IFA) performed on theIntel® Itanium® microprocessor proved [1] that:
after the most likely Vcc-Vss bridging fault (BF),
BFs directly involving a CK signal and Vcc (or Vss) are the most likely !
[1] C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
1
10
100
1000
10000
100000
1000000
10000000
100000000
Vcc/V
ss
all g
lobal
clock
s
fpu/
sbclk
10#
fpu/
sbclk
10#
fpu/
saclk
10#
fpu/
saclk
10#
fpu/
scan
out_
cntrl
10
fpu/
scan
out_
cntrl
10
ds1s
cano
ut_c
ntrl
ds1s
aclk#
ds1s
bclk#
fpu/
ss10
fpu/
ss10
dpw/d
pwot
ht/sa
clk02
#
dpw/d
pwot
ht/sb
clk02
#
dpw/d
pwot
ht/sb
clk02
#
dpw/d
pwot
ht/sa
clk02
#
fpu/
ds10
iscan
lpov
errd
tcsl
fpu/
ds10
iscan
lpov
errd
tcsl
dpw/d
pwot
ht/ss
02ds
2sbc
lk#
TOP WCA signal nets
These are scan clocks and scan control signals
Clock is the #1 net in terms of probability
WCA
Can Clock Signals Get Can Clock Signals Get Directly Involved by Faults ? (Directly Involved by Faults ? (cntcnt’’dd))
C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can Clock Signals Get Can Clock Signals Get Directly Involved by Faults ? (Directly Involved by Faults ? (cntcnt’’dd))
Electrical level simulations of the Itanium® clock distribution network, with BFs emulated by resistances in the [0-10kΩ] range, proved [1] that:
the most likely effects of clock faults are the occurrence of duty cycle variations which can occur also at the local clock level
[1] C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can Clock Signals Get Can Clock Signals Get Directly Involved by Directly Involved by Faults ? (Faults ? (cntcnt’’dd))
Voltages at a leaf of the clock tree with a 50 ΩBF to Vcc
duty cycle variation at the local clock level!
C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
VCC/2
DSK
DSK
DSKPLL
CLKP
CLKN
RCD
RCD DLCLK
OTB
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can Clock Signals Get Can Clock Signals Get Directly Involved by Faults ? (Directly Involved by Faults ? (cntcnt’’dd))
Clock signals can also get directly involved by faults [1]Such clock faults:
are orders of magnitude more likely than other faults [1]
may produce effects observable only at a local level [1]
are likely to result in duty-cycle variations [1]
will be increasingly more likely with technology scaling
If not screened out or compensated, such faults might compromise the correct operation of the microprocessor in the field
Dependability Risks ![1] C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them
during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can Clock Signals Get Can Clock Signals Get Indirectly Involved by Faults ?Indirectly Involved by Faults ?
Electrical level simulations of the Pentium 4®
microprocessor adjustable delay clock buffers [2] with injected:
transistor stuck-ons (SONs), transistor stuck-opens (SOPs), node stuck-ats (SAs),BFs (R in the [0-6kΩ] range)
proved that:such faults are very likely to result in output clocks with incorrect duty-cycle [2].
[2] C. Metra, D. Rossi, TM Mak, “Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?”, IEEE Trans. on Computers, Vol. 56, No. 3, March, 2007, pp. 415-428.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DetectableEffect29%
No Effect29%
Duty CycleVariation
42%
SON Effect Probability
DetectableEffect36%
No Effect29%
Duty CycleVariation
35%
SOP Effect Probability
Effects of Faults Effects of Faults Affecting Clock BuffersAffecting Clock Buffers
C. Metra, D. Rossi, TM Mak, “Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?”, IEEE Trans. on Computers, Vol. 56, No. 3, March, 2007, pp. 415-428.
DetectableEffect71%
No Effect29%
SA Effect Probability
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
% BF affecting the CKout duty-cycle
0
10
20
30
40
50
60
70
80
90
100
[0, 0.
5]]0.
5, 1]
]1, 1.
5]]1.
5, 2]
]2, 2.
5]]2.
5, 3]
]3, 3.
5]]3.
5, 4]
]4.5,
5]]5,
5.5]
]5.5,
6]
R (kOhms)
% B
F
Effects of Faults Effects of Faults Affecting Clock Buffers (Affecting Clock Buffers (cntcnt’’dd))
C. Metra, D. Rossi, TM Mak, “Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?”, IEEE Trans. on Computers, Vol. 56, No. 3, March, 2007, pp. 415-428.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Produced DutyProduced Duty--Cycle Variations Cycle Variations Can be SignificantCan be Significant
1 2 3 4 5 6 7 8 9 10Rbrid (kΩ)
51015
202530
354045
505560
65
Dut
y-C
ycle
varia
tion
(%)
RBrid
Example of a BF between Vcc and the buffer output.
High duty-cycle variations for values of connecting resistance ≤ 4kΩ!
C. Metra, D. Rossi, TM Mak, “Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?”, IEEE Trans. on Computers, Vol. 56, No. 3, March, 2007, pp. 415-428.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can Clock Signals Get Can Clock Signals Get Indirectly Involved by Faults ? (Indirectly Involved by Faults ? (cntcnt’’dd))
Clock signals can also get indirectly involved by faults (which directly affect clock buffers) [2]
Such clock faults: are likely to result in duty-cycle variations, which can bevery significant [2] will be increasingly more likely with technology scaling
If not screened out or compensated, such faults might compromise the correct operation of the microprocessor in the field
Dependability Risks ![2] C. Metra, D. Rossi, TM Mak, “Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?”,
IEEE Trans. on Computers, Vol. 56, No. 3, March, 2007, pp. 415-428.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Clock FaultsClock Faults’’ Due Dependability Risks: Due Dependability Risks: Solutions ?Solutions ?
Can clock faults be screened out through manufacturing (structural or functional) testing ?
Or can their effect be compensated?
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Generally, Generally, no specific testingno specific testing procedure is procedure is adopted for clock faultsadopted for clock faults
However, However, can clock faults be indirectly detectedcan clock faults be indirectly detectedduring manufacturing testing during manufacturing testing ((e.g.,e.g., structural or structural or functional testing) ? functional testing) ?
It has been verified that clock fault indirect It has been verified that clock fault indirect detection through detection through
structural testing is not likelystructural testing is not likely [1][1]
functional testing is not likely [3]functional testing is not likely [3]
Can Clock Faults Be Tested Out ?Can Clock Faults Be Tested Out ?
[3] C. Metra, D. Rossi, M. Omaña, J.M. Cazeaux, TM Mak, “Can Clock Faults Be Detected Through Functional Test ?”, Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’06), pp. 168—173, 2006.
[1] C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Inability of Structural Testing to Guarantee Clock Faults’ Detection
Can Clock Faults Be Tested Out ? (Can Clock Faults Be Tested Out ? (cntcnt’’dd))
Detecting clock faults throughDetecting clock faults through structural testing structural testing is not likely [1]:is not likely [1]:
[1] C. Metra, S. Di Francescantonio, TM Mak, “Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, May 2004, pp. 531-546.
depending on the structural test technique, anywhere between 59% and up to 88% of possible clock faulty conditions may be not detected.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
44 %44 %43 %33 %23 %AvPdet-sp
34 %
40%
35 %
50%
24 %
10%
33 %27 %AvPdet-lp
30%20%Mod(∆DC %)
Results for all long/short paths of 10 considered ISCAS’85 benchmarks
Inability of Functional Testing to Guarantee Clock Faults’ Detection
detdet
( ) 1,2,..., 10P iAvP i nn
= = =∑
Can Clock Faults Be Tested Out ? (Can Clock Faults Be Tested Out ? (cntcnt’’dd))Detecting clock faults throughDetecting clock faults through functional testing functional testing is not is not likely [3]:likely [3]:
[3] C. Metra, D. Rossi, M. Omaña, J.M. Cazeaux, TM Mak, “Can Clock Faults Be Detected Through Functional Test ?”, Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’06), pp. 168—173, 2006.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Clock FaultsClock Faults’’ Due Dependability Risks: Due Dependability Risks: Solutions ?Solutions ?
Can clock faults be screened out through manufacturing (structural or functional) testing ?
No guarantee
Or can their effect be compensated?
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Can CKF Effect Be Compensated ? Can CKF Effect Be Compensated ? Compensation schemes are intended to compensate skew mainly due to parameter variations at the global clock level
CKFs’ most likely effect is to produce duty cycle variations, which:
can be very significant
can occur also at the local level only
Compensation schemes could be modified to deal with CK faults, but
their cost would be very high
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Clock FaultsClock Faults’’ Due Dependability Risks: Due Dependability Risks: Solutions ?Solutions ?
Can clock faults be screened out through manufacturing (structural or functional) testing ?
No guarantee
NO (unless high cost)
Or can their effect be compensated?
Need for Testing Approaches and/or Correction Schemes to
Increase Dependability at Affordable Costs
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Example of Example of Low Cost Testing Approach for Clock FaultsLow Cost Testing Approach for Clock Faults
It has been proposed [4]:to make CFs’ most likely effects (i.e., duty-cycle variations) result in clock stuck-at faults (S@) catastrophic effects easy detection through conventional
manufacturing test
[4] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Approach to Clock Fault Testing for High Performance Microprocessors", in IEEE Proc. VLSI Test Symposium, 2007, pp. 441-446.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Possible Hardware ImplementationPossible Hardware ImplementationInsertion of Duty-Cycle Error Detect and Latch blocks (DCEDLi) among physically adjacent (local and global) CK buffers.
BufferBi
CKi
CKi+1
CK(i+1)B
CKiB
DCEDLi
en(i+1)
BufferBi+1
Ei
Each DCEDLi :checks the outputs of 2 adjacent clock buffers;gives the enable signal for one of such clock buffers.
All DCEDLi disabled (Ei=0) during µP normal operation.
C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Approach to Clock Fault Testing for High Performance Microprocessors", in IEEE Proc. VLSI Test Symposium, 2007, pp. 441-446.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
if CKiB≠CK(i+1)B en(i+1)=0 buffer Bi+1disabled CK(i+1)B S@0
easy detection;
Possible Hardware Implementation (Possible Hardware Implementation (cntcnt’’dd))
DCEDLi enabled (Ei=1)during µP testing:
Duty-Cycle Error Detect and Latch blocks (DCEDLi) between adjacent clock buffers.
if CKiB=CK(i+1)Ben(i+1)=1 buffer Bi+1enabled no effect.
BufferBi
CKi
CKi+1
CK(i+1)B
CKiB
DCEDLi
en(i+1)
BufferBi+1
Ei
C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Approach to Clock Fault Testing for High Performance Microprocessors", in IEEE Proc. VLSI Test Symposium, 2007, pp. 441-446.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Approach synergetic with local CK distribution no routing problems.
When TE=1 enigenerated in a ripple fashion S@0 on all CKs physically locatedamong the faulty one and the last one.
CF easy detectionthrough conventional manufacturing test.
Application to Local Buffers: Application to Local Buffers: PentiumPentium®®4 Example4 Example
CK1L
CK2L
RCD
CK3L
CKnL
RCD
Bn
B3
B2
B1
en3
en2
enn
DCEDL2
DCEDL1
DCEDLn-1
TE
TE
TE
TE connected to Ei of each DCEDLi
C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Approach to Clock Fault Testing for High Performance Microprocessors", in IEEE Proc. VLSI Test Symposium, 2007, pp. 441-446.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
DB47
DB3
DB1
DB2
Bin
ary
Dis
trib
utio
n Tr
ees PD
CK1R
CK2R
PD
PDCK3R
To Test Access Port
CK47R
en2R
en47R
en3R
DCEDL1
DCEDL2
DCEDL46
TEECP TE*
Scheme activated after calibration (ECP=1) detection of CFs, after parameter variation compensation.
Signal TE* =AND(TE, ECP) connected to theenable terminals (Ei)of the DCEDLs.
Application to Global Buffers: Application to Global Buffers: PentiumPentium®®4 Example4 Example
Approach synergetic with global CK distribution no routing problems.
C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Approach to Clock Fault Testing for High Performance Microprocessors", in IEEE Proc. VLSI Test Symposium, 2007, pp. 441-446.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Approach synergetic with global CK distribution no routing problems.
When TE*=1 eniRgenerated in a ripple fashion S@0 on all CKs physically locatedamong the faulty one and the last one.
CK fault easy detectionthrough conventional
manufacturing test
Application to Global Buffers: Application to Global Buffers: PentiumPentium®®4 Example (4 Example (cntcnt’’dd))
DB47
DB3
DB1
DB2
Bin
ary
Dis
trib
utio
n Tr
ees PD
CK1R
CK2R
PD
PDCK3R
To Test Access Port
CK47R
en2R
en47R
en3R
DCEDL1
DCEDL2
DCEDL46
TEECP TE*
C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Approach to Clock Fault Testing for High Performance Microprocessors", in IEEE Proc. VLSI Test Symposium, 2007, pp. 441-446.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Example of Example of Low Cost Correction Scheme for Clock FaultsLow Cost Correction Scheme for Clock Faults
Proposal of a scheme [5] capable of:
detecting mismatches between couples of physically adjacent local CKs and giving:
i. a high impedance state output, in case of mismatch;
ii. the logic value present on one of the two input clock signals, in case of matching.
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Scheme composed of 3 blocks:
It receives n input local clocks(CKin,i, i=1,…, n) to be compensatedin case of phase mismatch (i.e., duty cycle variation - ∆DC). It consist of (n-1) sub-blocks, each:
detecting phase mismatchesbetween two physical adjacentinput clocks (CKin,I - CKin,(i+1)) giving a high impedance state (Z) if the input CKs present ∆DC.
CKin,2
CKin,1
CKin,3
Det
ectio
n B
lock
CK2,3
CK1,2
CK3,4
1. Detection Block
Correction Scheme: Component Blocks Correction Scheme: Component Blocks
CKin,5
CKin,4
CKin,n
CK5,6
CK4,5
CK(n-1),n
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
It receives the (n-1)outputs of theDetection block (CKi,(i+1), i=1,…, n-1) and provides ncompensated clock signals (CK*i, i=1,…, n).
Com
pens
atio
nB
lock
2. Compensation Block
CKin,2
CKin,1
CKin,3
Det
ectio
n B
lock
CK2,3
CK1,2
CK3,4
CKin,5
CKin,4
CKin,n
CK5,6
CK4,5
CK(n-1),n
CK*2
CK*1
CK*3
CK*5
CK*4
CK*n
Scheme composed of 3 blocks:Correction Scheme: Component BlocksCorrection Scheme: Component Blocks ((cntcnt’’dd))
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Compensation Block: Possible ImplementationCompensation Block: Possible ImplementationWe can simply short together the (n-1) outputs of the Detection Block.
the high-Z state outputs of the Detection Block areforced to assume the correct logic value imposed by the non high-Z state outputs.
CKin,4
CKin,2CK2,3
D23
CK4,5
CKin,1CK1,2D12
CKin,3 CK3,4D34
D45
CKin,5CK5,6D56
CK*2
CK*4
CK*1
CK*3
CK*5
CK*6
DetectionBlock
CompensationBlock
No electrical conflict arises minimal power consumption and compensation time !
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Out
put B
lock
3. Output Block
Com
pens
atio
nB
lockCKin,2
CKin,1
CKin,3
Det
ectio
n B
lock
CK2,3
CK1,2
CK3,4
CKin,5
CKin,4
CKin,n
CK5,6
CK4,5
CK(n-1),n
CK*2
CK*1
CK*3
CK*5
CK*4
CK*n
CKout,2
CKout,1
CKout,3
CKout,5
CKout,4
CKout,n
Scheme composed of 3 blocks:
It receives theoutputs of theCompensation block andprovides properly buffered, compensated output clocks (CKout,i, i=1,…, n).
Correction Scheme: Component Blocks (Correction Scheme: Component Blocks (cntcnt’’dd))
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Cost ComparisonCost Comparison
Costs evaluated in terms of:
compensation error;power consumption;area overhead.
Scheme in [5] compared with:
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
[6] M. Omaña, D. Rossi, C. Metra, "Low Cost Scheme for On-Line Clock Skew Compensation", in Proc. of IEEE VLSI Test Symposium, pp. 90-95, 2005.
the clock compensation scheme in [6] (Solution 1);
the strategy that simply shorts together the outputs of the local clock buffers (Solution 2).
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Cost Comparison: Compensation ErrorCost Comparison: Compensation Error
Duty-cycle error (% of nominal duty-cycle)
Scheme in [5]Solution 1Solution 2
Out
put d
uty-
cycl
e er
ror (
% o
f nom
inal
dut
y-cy
cle)
Case 1: for all schemes it has been consideredthat 1 out of 16 input CKs presents a ∆DC between 0% and 100% of its nominal value (50% of TCK).
The scheme in [5]& solution 2 present a considerable low compensation error (0.2% and 0.4%, respectively)that does not change with the magnitude of ∆DC.
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
0
5
10
15
20
25
30
35
40
45
50
0 1 2 3 4 5 6 7 8
# of input clocks with incorrect duty-cycle
Out
put d
uty-
cycl
e er
ror (
% o
f nom
inal
dut
y-cy
cle) Solution 2
Proposed schemeSolution 1Scheme in [5]
Cost Comparison: Compensation Error (Cost Comparison: Compensation Error (cntdcntd))Case 2: compensation error as a function of the # of incorrect input CKs (= among them and with a ∆DC of 40% of its nominal value).
The scheme in [5] presents the lowest compensation error, with a reduction >69% compared to solution 1 and >40% compared to solution 2.
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Cost Comparison: Power ConsumptionCost Comparison: Power Consumption
Duty-cycle error (% of nominal duty-cycle)
Pow
er c
onsu
mpt
ion
(µW
)
Scheme in [5]Solution 1Solution 2
Power consumed by the 3 considered solutions as a function of ∆DC.
Due to the avoidance of electrical conflictsduring compensation, the power consumedby the scheme in [5] is approx. constant (∼ 40µW) with ∆DC.
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Cost Comparison: Area OverheadCost Comparison: Area Overhead
Number of input CKs
Are
a oc
cupa
tion
(squ
ares
)
Solution 1Solution 2Scheme in [5]
Area (expressed in squares) of the 3 considered solutions as a function of the # of input clocks to be compensated.
The area of the scheme in [5] slightly increaseswith respect to that of the solution 2. However, such an increase can be considerednegligible when the total chip area is accounted.
[5] C. Metra, M. Omaña, TM. Mak, S. Tam, "Novel Compensation Scheme for Local Clocks of High Performance Microprocessors", in IEEE Proc. of the IEEE Int. Test Conference, 2007, pp. 1-9.
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
ConclusionsConclusionsFaults affecting clock signals are likely and their likelihood will increase with technology scaling
They may be not screened out during manufacturing testing
They can not be compensated at low costs by currentschemes
They may compromise the microprocessor correct operation in the field, with consequent decrease independability
New Testing Approaches and/or Correction Schemes are (should be) searched for increased Dependability at
Affordable Costs
WDSN’09, Cascais (Portugal), June 29th, 2009 Cecilia Metra
Trading Off Dependability and Cost for Trading Off Dependability and Cost for NanoscaleNanoscale High Performance High Performance
Microprocessors: Microprocessors: The Clock Distribution ProblemThe Clock Distribution Problem
Cecilia MetraDEIS – University of Bologna