Transceiver Test Vector Developement Rev 11-2-11

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Applications Note

Test Engineering Tutorial

Complex VLSI Test Vector Development

PCI 10/100 ETHERNET MAC CONTROLLER WITH INTEGRATED PHY

Author Danny ONeill 16 September 2013



Table of Contents.............................................................................................................................................................................................................................................................................................................................................................................Applications Note............................................................................................................................................................................................................................................................................................................................................Test Engineering Tutorial................................................................................................................................................................................................................................................................................................................................Complex VLSI Test Vector Development.......................................................................................................................................................................................................................................................................................................PCI 10/100 ETHERNET MAC CONTROLLER WITH INTEGRATED PHY..............................................................................................................................................................................................................................................Table of Contents.............................................................................................................................................................................................................................................................................................................................................1. Register Level Test Plan..............................................................................................................................................................................................................................................................................................................................2. Logic Analyzer Capture of the System Level DUT Signaling....................................................................................................................................................................................................................................................................

4. RX Descriptor Read......................................................................................................................................................................................................................................................................................................................................5. TX Buffer Read.............................................................................................................................................................................................................................................................................................................................................6. RX Buffer Write ..........................................................................................................................................................................................................................................................................................................................................7. How PCI Works............................................................................................................................................................................................................................................................................................................................................8. STE 10/100 Datasheet..................................................................................................................................................................................................................................................................................................................................9. Ethernet Tutorials.........................................................................................................................................................................................................................................................................................................................................10. Reading the Control and Status Register CSR5.........................................................................................................................................................................................................................................................................................11. Writing the Network Access Register CSR6.............................................................................................................................................................................................................................................................................................12. Scope Capture of Test Pattern Execution..................................................................................................................................................................................................................................................................................................13. Schematic of the DUT Card.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................14. Ethernet Loopback......................................................................................................................................................................................................................................................................................................................................15. STE Block Diagram ...................................................................................................................................................................................................................................................................................................................................

1. Register Level Test Plan

2. Logic Analyzer Capture of the System Level DUT Signaling – ex. DUT Reading the Transmit Descriptor

3. TX Descriptor Read

4. RX Descriptor Read

5. TX Buffer Read6. RX Buffer Write

7. How PCI Works

8. STE 10/100 Datasheet

9. Ethernet Tutorials

10. Reading the Control and Status Register CSR511. Writing the Network Access Register CSR6

12. Scope Capture of Test Pattern Execution13. Schematic of the DUT Card

14. Ethernet Loopback

15. STE Block Diagram16. Tulip Software Driver



1. Register Level Test Plan

This assumes writes to configurationregisters (CRn) have been completed.

Write 0x00000001 to CSR0 (offset PBAR1 + 0x00) <----------p 17/66 via the PCI Access Register, Reset all internal HW excluding the transceivers and config registers

Write 0x8000 to XR0 (offset PBAR1 + 0xB4) --------p 31/66 via the Transceiver Control Register, Reset the transceiver

Write 0xF0000000 to CSR3 (PBAR1 + 0x18) --------p 17/66 Rec’v Descriptor Base Address RX_PTR = 0x80000000

Write 0xFF000000 to CSR4 (PBAR1 + 0x20) --------p 17/66 Transmit Descriptor Base Address TX_PTR = 0x40000000

Write 0x3000 to XR0 (PBAR1 + 0xB4) <---------------- p 31/66 Autonegotiation enabled and 100Mbs selected

Wait 6 seconds --------This is for the PHY to autonegotiate a link to itself.

Write 0x0100 to XR0 (PBAR1 + 0xB4) <---------------- p 31/66 Disable Autonegotiation by driving Bit [12]=0 so that Full Duplex can be selected by driving Bit[8]=1

//Write 0x0020204A to CSR6 (PBAR1 + 0x30) <---------------Currently writing 0x002820C2 which means we're disabling SQE, enabling multicast, and not passing bad packet. Change it to pass bad packet.

Write 0x000820CA/0x000824CA to CSR6 (PBAR1 + 0x30) -------- p19/66 in the Network Access Register set the Stop Transfer Bit [13]= 1 to start

TRANSMIT DESCRIPTOR READ- the ST will now read the following 4 Reads the following 4 D-Words From 0x40000000DWORDS from 0xFF000000. The tester must respond with this data:

0x80000000 <-----------------------TX DES0

0x62000040 <-----------------------TX DES1 first packet and end of ring. Buffer 2 byte count= 2**6= 64 bytes- 4 bytes per D-Word or 16 D-Word burst

0x20000000 ------------ TX Buffer Start Address programmed to A0000000

0x00000000 <----------------------TX DES3 s/b don't care, but zero it out.

RECEIVE DESCRIPTOR READ Reads the following 4 D-Words from 0x80000000

The ST will now read the following 4DWORDs from 0xF0000000. The tester must respond with this data:

0x80000000 <-----------------RXDES0 set Own Bit [31]

0x02000080 <------------------

0x10000000 <----------RX Buffer Start Address programmed to C0000000

0x00000000 <----------------------RX DES3 s/b don't care, but zero it out.



TX BUFFER READ Issues A0000000

The ST will now read the following 16words from the tester

0x00000000

0x55555555

0xAAAAAAAA

0xFFFFFFFF

0x0F0F0F0F

0x5A5A5A5A

0x00FF00FF

0xAA55AA55

0x00000000

0x55555555

0xAAAAAAAA

0xFFFFFFFF

0x0F0F0F0F

0x5A5A5A5A

0x00FF00FF

0xAA55AA55

2ND TRANSMIT DESCRIPTOR READ Issues C0000000 give the STE, nGNT, nTRDY, nDEVSEL

The ST will now read the following 4DWORDS from 0xFF000000. The tester must respond with this data:

0x80000000

0x62000040

0x20000000

0x00000000

RX BUFFER WRITE The ST will now write the following18 words to the tester: <--------------------------- It should be able to burst as long as REQ and GNT are asserted. P. 15 of CVF, Give STE nGNT, nTRDY, nDEVSEL

0x00000000

0x55555555



0xAAAAAAAA

0xFFFFFFFF

0x0F0F0F0F

0x5A5A5A5A

0x00FF00FF

0xAA55AA55

0x00000000

0x55555555

0xAAAAAAAA

0xFFFFFFFF

0x0F0F0F0F

0x5A5A5A5A

0x00FF00FF

0xAA55AA55

0x1B43BCF0

0x00440028



2. Logic Analyzer Capture of the System Level DUT Signaling

Figure 1. DUT Reading the Transmit Descriptor

Here is a capture of the ST part reading a transmit descriptor. The ST parts initiates a cycle to host memory. The address is set in CSR4 and in this case is 0x0198F040. The ST part does a burst read which means it reathan one dword. This is indicated by the four consecutive DATA cycles in that attached capture. A burst is indicated by the master holding FRAME# and IRDY# low after the initial address phase. The attached capture sfour dwords in the transmit descriptor being read.



Table 1. System Level DUT Logic Analyzer Capture

Sample# Comment CYCLE Add[32] Data[32] AD[31-0] C/BE[3-0] FRAME# IRDY# DEVSEL# TRDY# STOP# Time_Rel

-3 IDLE 0183C754 0110 1 1 1 1 1 0. ns

-2 IDLE 0183C754 0110 1 1 1 1 1 30. ns

-1 write 0x00000001 to CSR0 MEM WR FF1FFC00 FF1FFC00 0111 0 1 1 1 1 3.57797 s

0 DATA 00000001 00000001 0000 1 0 0 0 1 60. ns

1 IDLE 00000001 0000 1 1 1 1 1 30. ns

2 write 0x8000 to XR0 MEM WR FF1FFCB4 FF1FFCB4 0111 0 1 1 1 1 24.45 us

3 DATA ----8000 819F8000 1100 1 0 0 0 1 60. ns

4 IDLE 819F8000 1100 1 1 1 1 1 30. ns5 write rcv desc address to CSR3 MEM WR FF1FFC18 FF1FFC18 0111 0 1 1 1 1 21.78 us

6 DATA 0162A8E8 0162A8E8 0000 1 0 0 0 1 60. ns

7 IDLE 0162A8E8 0000 1 1 1 1 1 30. ns

8 write xmt desc address to CSR4 MEM WR FF1FFC20 FF1FFC20 0111 0 1 1 1 1 20.82 us

9 DATA 016931A8 016931A8 0000 1 0 0 0 1 60. ns

10 IDLE 016931A8 0000 1 1 1 1 1 30. ns

11 write 0x3000 to XR0 MEM WR FF1FFCB4 FF1FFCB4 0111 0 1 1 1 1 20.16 us

12 DATA ----3000 819F3000 1100 1 0 0 0 1 60. ns

13 IDLE 819F3000 1100 1 1 1 1 1 30. ns

14 read XR1, verify bit 2 is set MEM RD FF1FFCB8 FF1FFCB8 0110 0 1 1 1 1 72.54 us

15 DATA ----7809 00007809 1100 1 0 0 0 1 60. ns

16 IDLE 00007809 1100 1 1 1 1 1 30. ns

85 write 0x0020244A to CSR6 MEM WR FF1FFC30 FF1FFC30 0111 0 1 1 1 1 116.885 m

86 DATA 0020244A 0020244A 0000 1 0 0 0 1 60. ns

87 IDLE 0020244A 0000 1 1 1 1 1 30. ns

88 ST reads xmit descriptor MEM RD 016931A8 016931A8 0110 0 1 1 1 1 210. ns

89 DATA 80000000 80000000 0000 0 0 0 0 1 870. ns

90 DATA 62000040 62000040 0000 0 0 0 0 1 30. ns

91 DATA 017B99A8 017B99A8 0000 0 0 0 0 1 30. ns

92 DATA 00000000 00000000 0000 1 0 0 0 1 30. ns

93 IDLE 00000000 0000 1 1 1 1 1 30. ns

98 ST reads rcv descriptor MEM RD 0162A8E8 0162A8E8 0110 0 1 1 1 1 210. ns

99 DATA 80000000 80000000 0000 0 0 0 0 1 60. ns

100 DATA 02000080 02000080 0000 0 0 0 0 1 30. ns

101 DATA 01694380 01694380 0000 0 0 0 0 1 30. ns

102 DATA 00000000 00000000 0000 1 0 0 0 1 30. ns

103 IDLE 00000000 0000 1 1 1 1 1 30. ns

104 ST reads xmt buffer MEM RD 017B99A8 017B99A8 0110 0 1 1 1 1 210. ns

107 DATA 00000000 00000000 0000 0 0 0 0 1 420. ns

108 DATA 55555555 55555555 0000 0 0 0 0 1 30. ns

109 DATA AAAAAAAA AAAAAAAA 0000 0 0 0 0 1 30. ns

110 DATA FFFFFFFF FFFFFFFF 0000 0 0 0 0 1 30. ns



3. TX Descriptor Read

Table 2: Test Vector Micro-Instructions, UUT Syncronization. Here is the test vector code to do a TX Descriptor Read

1 Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:).

2 The tester which is now the Target, then gives the STE its GNTn.3 Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is,

that the STE issues the transmit descriptor base address 0x40000000 on the PCI AD bus,

and the Memory Read command (0x6) on the command bus, and asserts FRAME#4. Burst read which means it reads more than one D-word This is indicated by the four consecutive DATA cycles in attached capture. A burst is indicated by the master



Holding FRAME# and IRDY low after the initial address pulse the attached capture shows all folder D-Word in the Transmit Descriptor being read5 Insert dummy turn-around per the Read Transaction waveform

6 Then the Target gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE will then beginreading the TX Descriptor first of 4 D-Words TDES0 (pointed to by the transmit descriptor address) on the next PCI Klunk.

Note reading means the tester has to drive the TXDES0 own bit MSB 31 Hi.

TRDYn is used to hold off the master until the target is ready. On the next the PCI Clock, the tester provides TXDES1 = 0x62000040(page 40 of 66)which sets the buffer size. 40= 0100 0000 sets the 2 byte count to 2**6= 64 bytes. 64 bytes/4 bytes per

D-word= Burst Length of 16. On the next PCI Clock TXDES2, which is the TX Buffer Address 0xA0000000, is written into (read by) the STE



4. RX Descriptor Read

PCICLK RSTn FRAMEn IRDYn GNTn AD[31:0] CBEB[3:0] TRDYn IDSEL DEVSELn REQn STOPn PERRn SERRn PAR INTAn PMEn BRA[16:0] BRD[4:0] BrCSn BrOEn BrWEn LEDLK LEDC1 LEDSpd Vccdct Vauxdct BD6 BD7 EECS;// D LLLVV// P F CCCC E EEECA// C R I //// T I V S P S I B BB B B B BBB DDDCU// I R A R G A A A A BBBB R D S R T E E N P R RR R R R RRR MMMDX E// C S M D N D D D D EEEE D S E E O R R P T M A AA A D D COW 111ED BBE// L T E Y T 3 2 1 0 nnnn Y E L Q P R R A A E 1 00 0 0 0 SEE LFSTE DDC// K n n n n 1 3 5 7 3210 n L n n n n n R n n 6 87 0 4 0 nnn KDPET 67S// - - - - - -------- -------- -------- -------- ---- - - - - - - - - - - ----------------- ----- --- ----- ---//Request PCI Access:

;ldlc.100//Wait for UUT to access RX Descriptor Buffer Address

Wait_RX_Descriptor_REQ:K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Wait_RX_Descriptor_REQ

//GNT# REQ#K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_RX_Desc_REQK 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.17//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61// CSR3 RX_Ptr = 88000000hWait_Memory_Access_2:

K 1 L X 0 HLLLHLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Wait_Memory_Access_2//Delays driving bus one clock--klunk vs. PCI timing//Read RXDES0

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;JmpFail.No_RX_Desc_Access

K 1 L L 0 10000000 00000000 00000000 00000000 XXXX 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Read RXDES1, 2, 3// p. 38/66 - Table 10. Receive Descriptor Descriptions

K 1 L L 0 00000010 00000000 00000000 10000000 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...


K 1 H L 0 00000000 00000000 00000000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//-----------------------------------------------------------------------------------------------

Table 3: Test Vector Micro-Instructions, UUT Syncronization. Here is the test vector code to do a RX Descriptor Read

1 Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:).2 The tester which is now the Target, then gives the STE its GNTn.

3 Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is,that the STE issues the receive descriptor base address 0x88000000 on the PCI AD bus,

and the Memory Read command (0x6) on the command bus, and asserts FRAME#

4 Insert dummy turn-around per the Read Transaction waveform5 Then the Target gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE will then begin

reading the RX Descriptor first of 4 D-Words RDES0 (pointed to by the transmit descriptor address) on the next PCI Klunk. Note reading means the tester has to drive the RXDES0 own bit MSB 31 Hi.

TRDYn is used to hold off the master until the target is ready. On the next the PCI Clock, the tester provides TXDES1 = 0x62000040(page 40 of 66)which sets the buffer size. 40= 0100 0000 sets the 2 byte count to 2**6= 64 bytes. 64 bytes/4 bytes per

D-word= Burst Length of 16. On the next PCI Clock RXDES2, which is the RX Buffer Address 0xC0000000, is writt en into (read by) the STE

# 1

# 3

# 3

# 3

# 2

# 4

# 5

# 5# 5



5. TX Buffer Read

PCICLK RSTn FRAMEn IRDYn GNTn AD[31:0] CBEB[3:0] TRDYn IDSEL DEVSELn REQn STOPn PERRn SERRn PAR INTAn PMEn BRA[16:0] BRD[4:0] BrCSn BrOEn BrWEn LEDLK LEDC1 LEDSpd Vccdct Vauxdct BD6 BD7 EECS;// D LLLVV// P F CCCC E EEECA// C R I //// T I V S P S I B BB B B B BBB DDDCU// I R A R G A A A A BBBB R D S R T E E N P R RR R R R RRR MMMDX E// C S M D N D D D D EEEE D S E E O R R P T M A AA A D D COW 111ED BBE// L T E Y T 3 2 1 0 nnnn Y E L Q P R R A A E 1 00 0 0 0 SEE LFSTE DDC// K n n n n 1 3 5 7 3210 n L n n n n n R n n 6 87 0 4 0 nnn KDPET 67S// - - - - - -------- -------- -------- -------- ---- - - - - - - - - - - ----------------- ----- --- ----- ---//Wait for UUT to access TX Descriptor Buffer Address

;ldlc.100

Wait_TX_Buffer_REQ:K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Wait_TX_Buffer_REQ

//GNT# REQ#K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_TX_Buffer_REQK 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...Wait_BufferMemory_Access_1:

K 1 L X 0 HLHLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;JmpFail.No_BufferMemory_AccessK 1 L L 0 11111111 11111111 11111111 11111111 LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...K 1 L L 0 11111111 11111111 00000000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX



@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...












K 1 H L 0 10011010 10111100 11011110 11110000 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//--------------------------------------------------------------

Table 3: TX Buffer Read

1 Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:).2 The tester which is now the Target, then gives the STE its GNTn.

# 1

# 2

# 3

# 5

# 4

# 4



3 Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is,that the STE issues the Transmit Buffer Start Address 0xA0000000 on the PCI AD bus,

and the Memory Read command (0x6) on the command bus, and asserts FRAME#4. Then the Target gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE asserts IRDY# active Low out then begins

reading the TX Buffer.

5. The DUT will now read the following 16 words from the tester



6. RX Buffer Write

PCICLK RSTn FRAMEn IRDYn GNTn AD[31:0] CBEB[3:0] TRDYn IDSEL DEVSELn REQn STOPn PERRn SERRn PAR INTAn PMEn BRA[16:0] BRD[4:0] BrCSn BrOEn BrWEn LEDLK LEDC1 LEDSpd Vccdct Vauxdct BD6 BD7 EECS;// D LLLVV// P F CCCC E EEECA// C R I //// T I V S P S I B BB B B B BBB DDDCU// I R A R G A A A A BBBB R D S R T E E N P R RR R R R RRR MMMDX E// C S M D N D D D D EEEE D S E E O R R P T M A AA A D D COW 111ED BBE// L T E Y T 3 2 1 0 nnnn Y E L Q P R R A A E 1 00 0 0 0 SEE LFSTE DDC// K n n n n 1 3 5 7 3210 n L n n n n n R n n 6 87 0 4 0 nnn KDPET 67S// - - - - - -------- -------- -------- -------- ---- - - - - - - - - - - ----------------- ----- --- ----- ---//Wait for UUT to write RX Buffer:

;ldlc.1000Wait_Write_RX_Buffer_REQ:

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Wait_Write_RX_Buffer_REQ//GNT# REQ#

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;JmpFail.No_RX_Buffer_REQK 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

RX_Buffer_Access:K 1 L X 0 HHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HHHHHHHH HHHHHHHH LLLLLLLL LLLLLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 LLHLHHLH LLHLHLHL HHLHLHLH LLHLHLHL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// should be 0xBBAADDC// K 1 L L 0 HLHHHLHH HLHLHLHL HHLHHHLH HHLLHHLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 HHLHLLHL HLHLHHLH LLHLHHLH LLHLHHLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 X X 0 LLLLLLLL LLHLHHHL LLLLLLLL LLLLLLLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 X X 0 HLLLLLLL LHLHLLHL HHLHLLHL HHLHLLHL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 X X 0 LLLLLLHL LLLLLLHH LLLLLHLL LLLLLHLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 X X 0 HHHHHHHH HHHHHHHH HLLLLLLL LHHHHHHH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 X X 0 LLLLLHHL LLLLLHHH LLLLHLLL LLLLHLLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 X X 0 LLHLHHLH LLLLLLLL LHHHHLLL LLLLLHHH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLLHLHL LLLLHLHH LLLLHHLL LLLLHHLH LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 HHLLLLHH HHLHLLHL HLLLLHHH HHHHHLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLLHHHL LLLLHHHH LLLHLLLL LLLHLLLH LLLL 0 0 0 L X X X L X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 HLLLLHHH HHHHLHHL HHHLLHLH HHLHLHLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HLHLHLHL LHLHLHLH HLHLHLHL LHLHLHLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 LLHLLLHL LLHHLLHL HLHLLLLH HLLHLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HLHLLHLH HLHLLHLH HLHLLHLH HLHLLHLH LLLL 0 0 0 L X X X L X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 LLHLLLHL LLHHLLHL LHLHHLLL LHHLHHLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LHLHHLHL LHLHHLHL LHLHHLHL LHLHHLHL LLLL 0 0 0 L X X X L X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 H L 0 LLLLLLLL LLHLLLHL HLHLHLLL LLHLHHHL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLLLLLL HHHHHHHH LLLLLLLL HHHHHHHH XXXX 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX// K 1 H L 0 LLLLLLLL LLHLLHHL HLHLHLLL LLHLHHHL XXXX 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HHHHHHHH LLLLHHHH HHHHLLLL LLLLLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LHLHHLHL HHHHLLLL LLLLHHHH HLHLLHLH LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLHLLHL LLHHLHLL LHLHLHHL LHHHHLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HLLHHLHL HLHHHHLL HHLHHHHL HHHHLLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 H L 0 LLLHLLHL LLHHLHLL LHLHLHHL LHHHHLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

# 1

# 2# 3

# 4



//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

// K 1 H L 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

Table 4: RX Buffer Write

1 Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:).

2 The tester which is now the Target, then gives the STE its GNTn.3 Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is,

that the STE issues the Receive Buffer Start Address 0xC0000000 on the PCI AD bus,

and the Memory Write command (0x7) on the command bus, and asserts FRAME#4 The DUT will now write the following 18 words to the tester. Then the Target gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE will then begin

reading the RX Buffer.



7. How PCI Works



1. Address Phase

1a) Initiator identifies the target via the ADX and the type of transaction via the command bus

1b) Initiator also asserts FRAME# to indicate the presence of valid ADX and command

2. Data Phase

2a) When the Target determines it is the selected target, it must claim the transaction by asserting DEVSEL# . If the Initiator doesn’t sample DEVSEL# asserted, it aborts the transaction2b) The Initiator indicates the last data t ransfer of a burst in progress by deasserting FRAME# and asserting IRDY# . When the last data transfer has been completed , the Initiator returns the PCI Bus to idle by deassertinIRDY#, so that another master can detect that the bus is idle by detecting FRAME# and IRDY# both deasserted on the same rising edge of the PCI Clock 2c) When the Target samples IRDY# asserted and FRAME# deasserted in a data phase, it realizes this is the final data phase. However the data phase will not complete until the target has also deasserted TRDY#

3. Config Page 121 of PCI System Architecture Fourth Edition by Tom Shanly and Don Anderson

3a) To access Configuartion Registers, a config command must be initiated, and the device must sense it’s IDSEL input asserted during the Address Phase3b) AD[10:8] selects the function; AD[7:2] during the ADX Phase select one of the Target function’s 64 D-Words of Config Space

8. STE 10/100 Datasheet

STE10/100A datasheet pages

http://var/www/apps/conversion/tmp/2011/STE10-100A.pdf




9. Ethernet Tutorials

Beginers guide to Ethernet 802.3

10. Reading the Control and Status Register CSR5

STE10/100A datasheet pages 19-20.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

F C 3 6 5 4 1 0

1 1 1 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0

a. Read the following from CSR5 [31:0] (Control and Status Register) b. ‘HHHHHH’ from CSR5 [31:26] Reserved.c. ‘LLL’ from CSR5 [25:23] BET bits. This field is valid iff FBE bit 13 Fatal Bus Error is set. But FBE = 0 therefore No Fatal Bus Error.d. ‘LHH’ from CSR5 [22:20] Transmit State FIFO Fill. Read the data from memory and put into FIFOe. ‘LHH’ from CSR5 [19:17] Receive State wait for receiving data.f. ‘L’ from CSR5 [16] Normal Interrupt Status Summary. Default State 0g. ‘L’ from CSR5 [15] Abnormal Interrupt Status Summary. Default State 0h. ‘H’ from CSR5 [14] Reserved.i. ‘L’ from CSR5 [13] Fatal Bus Error. Default State 0 j. ‘H’ from CSR5 [12] Reserved.k. ‘L’ from CSR5 [11] General Purpose Timer Timeout. Default State 0l. ‘H’ from CSR5 [10] Reservedm. ‘L’ from CSR5 [9] Receive Watchdog Timeout. Default State 0n. ‘L’ from CSR5 [8] Receive Process Stopped. Default State 0o. ‘L’ from CSR5 [7] Receive Descriptor Unavailable. Default State 0 p. ‘L’ from CSR5 [6] Receive Completed Interrupt. Default State 0q. ‘L’ from CSR5 [5] Transmit Under-Flow. Default State 0r. ‘H’ from CSR5 [4] Reserveds. ‘L’ from CSR5 [3] Transmit Jabber Timer Time-out. Default State 0t. ‘L’ from CSR5 [2] Transmit Descriptor Unavailable. Default State 0u. ‘L’ from CSR5 [1] Transmit Process Stopped. Default State 0v. ‘L’ from CSR5 [0] Transmit Completed Interrupt. Default State 0

http://www.analog.com/static/imported-files/application_notes/458197465EE269v01.pdf




w. Set all other values to defaults.1

STE10/100A datasheet pages 19-20.

1 STE10/100A datasheet pages 19-20.







11. Writing the Network Access Register CSR6

Write 0x000824CA To CSR6 (PBAR1 + 0x30)

1. Write the following to CSR6 [31:0] (Network Access Register) “00000000001010000010000011000010”:a. ‘1’ to CSR6 [21] Store and Forward (SF) so UUT ignores transmit threshold setting. b. ‘1’ to CSR6 [13] Stop Transmit (ST) to start Transmit.c. ‘1’ to CSR6 [6] Promiscuous mode (PR) so UUT accepts any good packet.d. ‘1’ to CSR6 [1] Start/Stop Receive (SR) to set Receive processor to run.e. Set all other values to defaults.2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 2 8 2 4 C A

0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0

CSR6 [21] SF Store and Forward for transmit enable.CSR6 [19] SQE set to 1 disables SQE function.CSR6 [13] ST Stop Transmit set to start.CSR6 [10] OM Operating Mode bit set to enable MAC Loopback CSR6 [7] MM Multicast Mode set to receive all multicast packets.CSR6 [6] PR Promiscuous Mode set to receive any good packet.CSR6 [3] PB Pass Back packet set to receive any packets passing address filter, including runt packets, CRC error, truncated packets. For receiving all bad.CSR6 [1] SR Start Stop Receive processor will enter running state.

Tulip Software Driver CSR6 Register Programming.

2 STE10/100A datasheet pages 19-20.

http://var/www/apps/conversion/tmp/scratch_3/Files/csr6register.rtf

http://var/www/apps/conversion/tmp/scratch_3/Files/csr6register.rtf







12. Scope Capture of Test Pattern Execution

Picture # Trace

Description

Trace

1ShowsCBEB0indicative of a 16 wordwrite,followed bya read of CSR5 andthen STEwrites twomore FCSwords toRX buffer.

Trace 1:FRAME#Trace 2:TRDY#Trace 3: PCICLK Trace 4:C/BEB0#

2 This view

shows thetwo wordwrite of thelatter part of the scope pictureabove. TheSTE readsthe TXBuffer againand thendoes a writeto TXDES0.

Trace 1:

FRAME#Trace 2:TRDY#Trace 3: PCICLK Trace 4:C/BEB#



13. Schematic of the DUT Card



http://var/www/apps/conversion/tmp/scratch_3/Files/ST10-100ADUTCARD.pdf



15. STE Block Diagram

Page 10 of 26 of Beginners guide to Ethernet 802.3

STE10/100A datasheet pages







16. Industry Standard PCI Ethernet Tulip Software Driver

http://var/www/apps/conversion/tmp/scratch_3/Files/tulip.txt

http://var/www/apps/conversion/tmp/scratch_3/Files/tulip.txt

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Transceiver Test Vector Developement Rev 11-2-11

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