Transmitter for Quantum Encryption System
Supervisor: Yossi Hipsh
Performed by: Asaf Holzer Edward Shifman
High Speed Digital Systems Laboratory
Final presentation Spring 2006
Background
Several methods can be used for encrypting information. One of
them is the BB84 scheme, which was developed by Brassard &
Bennett. The advantage of this method is that it is impossible to
crack it, because it is based on the “No Cloning” principle.
The BB84 scheme was mathematically proved as a perfectly safe
Method, in a theoretical perfect world without noises.
Project Objectives
•The transmitter module is part of a complex system, which
purpose is to send a digital code, which will later be used as
key for encrypting and decrypting information.
•Our goal is to produce an electrical pulse which is ~0.5ns
wide and its magnitude is 4v. The purpose of this pulse is to
activate the laser diode.
The Overall System Block Diagram
Computer + Labview
Transmitter Reciever
Interferometers, etc.
Computer + Counter
Synchronization
Original Plan
Pulse trigger
D.D.L TTL 2 ECLECL Programmable
Delay Chip
1:2ECL Programmable
Delay Chip
Long fiber
And Gate1:2
Bal_UN Bal_UN
Gain Gain
P_Quant P_Sync
monostable
Original Plan – continued…
Pulse trigger
D.D.L TTL 2 ECLECL Programmable
Delay Chip
1:2ECL Programmable
Delay Chip
Long fiber
And Gate1:2
Bal_UN Bal_UN
Gain Gain
Ref P_Stab
monostable
In order to improve the module’s performance we decided to
use ECL technology from the very beginning of the pulse
module, so we put the TTL-ECL device at the beginning.
We replaced the components so they will operate in
3.3 voltage level.
Some more advances
Pulse trigger
TTL 2 ECL
ECL Prog. Delay Chip 1:2 And Gate
1:4
Bal_UN
Gainmonostable
ECL Prog. Delay Chip
ECL Prog. Delay Chip
…
…
…
P_Quant
P_Sync
P_Sync
Ref
Plan #2
Plan #3Computer – LabView
1:4(TTL)
Mux Mux
TTL-ECL TTL-ECL TTL-ECL
Pulse-Module Pulse-Module Pulse-Module
1:4(TTL)
sel sel
counter
P_Quant P_Stab P_Sync
stab_en sync_ctrltrig
detector refref
The Monostable (ECL) – Take #1…
Flip Flop
S
R
Q
DECL Prog.
Delay Chip 1
ECL Prog. Delay Chip 3
ECL Prog. Delay Chip 21:4
(ECL)
QCLK
MC100EP31
MC100EP31 Characteristics:
The Monostable Timing Diagram
Data
CLK
Reset
Q
ts
tclk-Q
tR-Q
Q
400ps130ps
Min. Pulse width:
530ps
t
t
t
t
Plan #3 – Pulse Module
monostable monostable
And Gate
1:2
Bal_UN
Bal_UN
Gain
Gain
Plan B
3ns 0.5ns
10ns
ref
Flip Flop
S
R
Q
D
ECL Prog. Delay Chip 2
ECL Prog. Delay Chip 1
1:4(ECL)
QCLK
Plan #3 – Pulse Module
Flip Flop
S
R
Q
DECL Prog. Delay Chip 3
ECL Prog. Delay Chip 5
ECL Prog. Delay Chip 4
1:4(ECL) QCLK
3ns
0.5ns
And Gate0.5ns
Voltage Surfaces
• Vcc - 3.3V
• Vtt – 1.3V
• GND
We ended up with one voltage source of 3.3V.
Using a regulator to get 1.3V and a DC/DC
converter to get 5V.
Voltage Surfaces
The Original Bal-UN
INOUT
68Ω
68Ω 68Ω
68Ω
140Ω 140Ω
150Ω
150Ω1nF
1nF
100nF
100nF
+
-
Vtt=1.3v
Vtt=1.3v
The Final Bal-UN
INOUT
68Ω
68Ω 68Ω
68Ω
140Ω 140Ω+
-
Vtt=1.3v
The Final ORCAD Design
The Final ORCAD Design
The Final ORCAD Design:Pulse-Module:
The Final ORCAD DesignTest Points:
•Counter_tp – The detector has detected p_quan.
•Splitter14_tp – A pulse trigger has been received.
•Quan_tp
•Stab_tp
•Sync_tp
Testing each Pulse Module
Connectors
•Power Connector
•SMA Connector
•Flat-Cable Connector
The Final Layout
Component ListComponent Description Manufacturer Quantity
NB3L553_D 1:4 TTL ON Semi 1
MC100EP11_DT 1:2 PECL ON Semi 6
SN74F74_N FF (monostable) TI 2
MC100EPT20_DT TTL to PECL ON Semi 3
MC100EPT21_DT PECL to TTL ON Semi 1
MC100EP58_DT Multiplexer ON Semi 1
MC100EP195_FA ECL Prog. Delay ON Semi 9
SN7LVC1G125_DCK Enable Buffer TI 1
MC100EP05_DT AND Gate ON Semi 3
PTH04000WAH_EUS Regulator TI 1
DC/DC Step-Up Converter DC/DC Converter Tekgear 1
ZPUL-30P Amplifier Mini Circuits 6
Power & Connectors ListComponent Description Manufacturer Quantity
HWS10-3/A Power Supplier Lambda 1
SMA8410L-9000 SMA Connector JYEBAO 12
CTB9300/6A Power Connector Camden 1
17978-150 Flat Connector FCI 1
PART B
Stack & Lines Design:
Raw material used – Fr4
W = 7mil 1.8323W
h
Calculated using Microstrip equations, to achieve
Stack & Lines Design:
Raw material used – Fr4
W = 7mil
Calculated using Stripline equations, to achieve
Stack & Lines Design:
HyperLynx Simulation
First AssumingDesign File: 1_ 2_ _ _ 1_ 2.ffsHyperLynx LineS im V7.5
U1
MC100EP11DT_33D
2
1
U2
MC100EP11DT_33Q
2
1
TL1
50.1 ohms30.756 ps0.200 inCoupled Stackup
TL2
50.1 ohms30.756 ps0.200 inCoupled Stackup
R1
50.0 ohms
R2
50.0 ohms
Vtt1.3V
HyperLynx Simulation
Simulation Results for various frequencies
OSCILLOSCOPEDesign file: 1_2___1_2.FFS Designer: Shifman
HyperLynx V7.5
Date: Monday Apr. 16, 2007 Time: 16:11:59Show Latest Waveform = YES
-2000.0
-1500.0
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0.000
500.0
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0.000 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
@500MHzOSCILLOSCOPE
Design file: 1_2___1_2.FFS Designer: ShifmanHyperLynx V7.5
Date: Monday Apr. 16, 2007 Time: 16:13:51Show Latest Waveform = YES
-2000.0
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0.000
500.0
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0.000 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
@2000MHz
HyperLynx Simulation
Falling Edge SimulationOSCILLOSCOPE
Design file: 1_2___1_2.FFS Designer: ShifmanHyperLynx V7.5
Date: Monday Apr. 16, 2007 Time: 16:21:33Show Latest Waveform = YES
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0.000
500.0
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0.000 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 2000.0Time (ps)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
HyperLynx Simulation
Simulation Results for various frequencies
@500MHz @2000MHz
Now Assuming
OSCILLOSCOPEDesign file: 1_2___1_2.FFS Designer: Shifman
HyperLynx V7.5
Date: Tuesday Apr. 17, 2007 Time: 12:49:38Show Latest Waveform = YES
-2500.0
-2000.0
-1500.0
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-500.0
0.000
500.0
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1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000 11.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
OSCILLOSCOPEDesign file: 1_2___1_2.FFS Designer: Shifman
HyperLynx V7.5
Date: Tuesday Apr. 17, 2007 Time: 12:46:56Show Latest Waveform = YES
-2500.0
-2000.0
-1500.0
-1000.0
-500.0
0.000
500.0
1000.0
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1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000 11.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
Delay =
HyperLynx Simulation
Simulation until now usingS – distance between the lines
HyperLynx V7.5
GND1
HyperLynx V7.5
GND1
Field Influence @ S=8mil Field Influence @ S=20mil
HyperLynx Simulation - Vias
HyperLynx does not support Vias, so we had to model the via, using a capacitor & a resistor.
Design File: 1_2___1_2_up_only_via.ffsHyperLynx LineSim V7.5
U1
MC100EP11DT_33D
2
1
U2
MC100EP11DT_33Q
2
1
TL1
49.9 ohms153.179 ps1.000 inCoupled Stackup
TL2
50.0 ohms153.560 ps1.000 inCoupled Stackup
R1
50.0 ohms
R2
50.0 ohms
Vtt1.3V
TL4
50.0 ohms153.582 ps1.000 inCoupled Stackup
TL3
49.8 ohms183.679 ps1.000 inCoupled Stackup
TL5
49.8 ohms183.680 ps1.000 inCoupled Stackup
TL6
49.9 ohms153.171 ps1.000 inCoupled Stackup
C1
3.0 fF
C2
3.0 fF
C3
3.0 fF
C4
3.0 fF
R3
2.0 milliohms
R4
2.0 milliohms
R5
2.0 milliohms
R6
2.0 milliohms
HyperLynx Simulation - Vias
Simulation results for various frequencies
OSCILLOSCOPEDesign file: 1_2___1_2_UP_ONLY_VIA.FFS Designer: Shifman
HyperLynx V7.5
Date: Wednesday Apr. 18, 2007 Time: 18:03:51Show Latest Waveform = YES
-2500.0
-2000.0
-1500.0
-1000.0
-500.0
0.000
500.0
1000.0
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0.000 2.000 4.000 6.000 8.000 10.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
@500MHzOSCILLOSCOPE
Design file: 1_2___1_2_UP_ONLY_VIA.FFS Designer: ShifmanHyperLynx V7.5
Date: Wednesday Apr. 18, 2007 Time: 18:02:12Show Latest Waveform = YES
-2500.0
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-1000.0
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0.000
500.0
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0.000 2.000 4.000 6.000 8.000 10.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
@1000MHz
HyperLynx Simulation - Vias
Running a simulation without modeling the vias(with same total length of the transmission line)
OSCILLOSCOPEDesign file: 1_2___1_2_UP_ONLY.FFS Designer: Shifman
HyperLynx V7.5
Date: Wednesday Apr. 18, 2007 Time: 17:47:21Show Latest Waveform = YES
-2500.0
-2000.0
-1500.0
-1000.0
-500.0
0.000
500.0
1000.0
1500.0
2000.0
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0.000 2.000 4.000 6.000 8.000 10.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
OSCILLOSCOPEDesign file: 1_2___1_2_UP_ONLY.FFS Designer: Shifman
HyperLynx V7.5
Date: Wednesday Apr. 18, 2007 Time: 17:46:27Show Latest Waveform = YES
-2500.0
-2000.0
-1500.0
-1000.0
-500.0
0.000
500.0
1000.0
1500.0
2000.0
2500.0
0.000 2.000 4.000 6.000 8.000 10.000Time (ns)
Vol
tag
e -m
V-
Probe 1:U1.1 (at pin)Probe 2:U2.1 (at pin)
@500MHz @1000MHz
HyperLynx Simulation - Conclusion
• Impedance Coordination & Reflections
• Delays
• Crosstalk
• Via’s influence
The FPGA
Field Programmable Gate Array
FPGA Design
Opcode structure:
Mode (1bit) Pulse_editmode (2bit) Pulse_width (10bit) Pulse_offset (11bit)
Mode (1bit)Pulse_workmode (3bit)
Edit Mode:
Work Mode:
0
1
Field Size(bit) Name Comment
Opcode(23)1 Mode 0 – Edit mode
1 – Work mode
Opcode(22-21) 2 Pulse_editmode Chosen Pulse module
Opcode(20-11) 10 Pulse_width [500ps . . 4000ps]
Opcode(10-0) 11 Pulse_offset [4500ps . . 18500ps]
Opcode(22-20) 3 Pulse_workmode Chosen pulse-module/s
FPGA Design
The FPGA – VHDL Design
The FPGA – VHDL Design
The FPGA – VHDL Design
Delay 1
Delay 2
Delay 3
LEN
LEN
LEN
offset_temp <= pulse_offset - const_440; PROCESS(clk) BEGIN if (offset_temp(10) = '1') then first_offset <= const_1023; second_offset <= offset_temp(9 downto 0) + "0000000001"; else first_offset <= offset_temp(9 downto 0); second_offset <= const_0; end if; END PROCESS;
delay1 <= first_offset; delay2 <= second_offset; delay3 <= second_offset +const_450- pulse_width;
Delay Decode
The FPGA – Delay Set:
The FPGA – TESTBENCH:
The FPGA – TESTBENCH:
VHDL Simulation:
VHDL Simulation:
VHDL Simulation:
Supplemental Value:
The project gave us experience in performing a large scale product, which involves several development groups, and provided us systemic vision.
In the process of developing the project we enriched ourselves with techniques of high-speed systems and high-frequency phenomena.
We experienced working with design & simulation tools such as: ORCAD, HDL Designer and HyperLynx.
One of the most valuable principles we’ve learned is board design.
Future possibilities:
The elementary step now would be sending our design to printing and testing it when it’s ready.
In order to make the product user-friendly, we would have now built a graphical interface which translates the desired pulses shapes to appropriate sets of opcodes. The opcodes should be sent to the FPGA via USB connection.
Supplemental Value:
The project gave us experience in performing a large scale product, which involves several development groups, and provided us systemic vision.
In the process of developing the project we enriched ourselves with techniques of high-speed systems and high-frequency phenomena.
We experienced working with design & simulation tools such as: ORCAD, HDL Designer and HyperLynx.
One of the most valuable principles we’ve learned is board design.