Trigger and DAQ SystemZhao Jing Wei

Sept. 2002, BESIII review, Beijing

Outline Trigger system

Event rate estimation Principle of design Scheme Monte Carlo simulation

DAQ system Read Out Online Slow Control

Details

Trigger System __ Estimation of event rate

Purpose To select all interested events for

physics from backgrounds To suppress background as

possible Event rate after Level 1 can be

sustainable for DAQ system

Trigger System__ Estimation of event rate

Total trigger rate

= good event rate (~2000, LBEPCII = 1 1033 cm-2 s-1)

+ bhabha rate (~800,to be pre-scaled)

+ cosmic event rate (<200,from 1500)

+ beam background rate (<2000Hz,from 13MHz)

= ~ 4000 Hz

Trigger System__ Estimation of event rate

Backgrounds rate vs beam current At BESII/BEPC

Trigger System__Principle

Challenges to BESIII trigger design High good event High Backgrounds Multi-bunches=93, small bunch spacing=8ns

No dead time design in trigger system Pipeline processing must be used

(Latch-process-decision mode not possible in 8ns) Latency of trigger signal necessary

Trigger System__Principle

Hardware trigger + software trigger(filter)

FEE signal is splitted totrigger + FEE pipeline

L1 signal 3.2 s latency FEE pipeline clock 40MHz FEE Control Logic checks L1

with FEE pipeline clock L1 YES

moves pipeline buffer data L1 No

overwritten by new data

Detector

switch

Level 1FEEpipeline

Readoutbuffer

Farms

Disk

Time Reference

0 s

3.2s

Ev.Filter

PowerPC

Block Diagram of BES III Trigger

Glo

bal T

rigg

er L

ogic

3.2 s

TOF

MDC

EMC

MU

DISC

DISC

Mu trackDISC

TrigSum

Track Finder

Etotal Sum

Hit/Seg Count

Track Seg. Finder

RF TTC

TC Sum

L1P

CLOCK

Track Match

Energy Balance

Cluster Counting

Trigger System__Scheme

One way of the detector signal from FEE is sent to trigger system.

TOF trigger hit, time and topology information

MDC trigger checks for a track segment looks for a track with track segments counts the number of tracks.

EmC trigger makes a sum of 24 Crystal signals to form a trigger cell uses trigger cells to make energy balance

Trigger System__Scheme

Track match The messages from TOF, EmC, MDC will be used in tr

ack Matching to check whether there are matched tracks.

Global trigger All messages will be sent to global trigger, based on tri

gger conditions if the event is good is determined. Level 1 signal

Global trigger will send L1 signal to readout modules of electronics if it is good event.

MDC trigger schemes

GLT

TSF cards

On FEEGTSF

BLT

PTD/TF

90082008

Axial&

stereo

TRK CNT

•Scheme A(AX only):

•TSF + TF + TRKCNT

•Scheme B(AX+ST):

•TSF + GTSF +BLT+PTD+TRKCNT

Feasibility of trigger scheme study

Trigger efficiency study

Wire in-efficiency influence study

Backgrounds rejecting ability study

Production of configuration data

Track Segment Finding

Track Finding/PTD

MDC trigger simulation

Trigger efficiency vs Pt and wire efficiency

Configuration:

Pt > 120 MeV

tracks with Pt>130MeV + Weff>95%

TrigEff>95%

tracks with Pt>130MeV + Weff>95%

TrigEff>95%

TSF:Ncomb=8

TSF:Ncomb=24

BESIII EMC trigger scheme

Gain Adj.

FEE 8ch sum

EMC Simulation

<20% difference acceptable Gain adjustment for each cry

stal+PD+PreAmp chain

• Trigger Cell should be at least 4X4 =16 crystals.

• 4X6=24 is taken

Summary of Trigger System Hardware trigger + software filter L1 latency : 3.2 s Pipeline clock: 40 MHz Monte Carlo simulation going well

backgrounds, MDC, EMC trigger schemes Design scheme drafted Some modules designed/designing Further/detailed designing undergoing

BESIII DAQ system__Tasks

Event readout from FEE Event building

(fragments → sub-events → a full event) Online event filtering

(L3 trigger, 50% backgrounds suppressed) Event recording to persistent media Run control of DAQ system Monitoring (event, histogram display ...) Message reporting functions

Data Rate Estimation

Sub-detector Number of Channel s

Event Si ze(bytes)

Readout Data Rate(Mbytes/s)

Record Data Rate(Mbytes/s)

MDC（T+Q） 18000 7200 29 21.8 EmC 9864 4000 16 12 TOF+CCT 912 400 1.6 1.2 μ 10000 400 1.6 1.2 Trigger 400 200 0.8 0.8 Sub-total 39288 12200 49 37 BESI I 20000 2000 0.04 0.04

Data Volume Estimation Electronic Channels to be Readout: 40K(30K TDC plus

ADC)

Level-1 Trigger Rate: 4KHz (2KHz Good Events)

Event Size: 12KBytes

Data rate after Level 1 will be 49MByte/sec Data rate to be recorded on tape 37MByte/sec 1000 times than BESII DAQ System(0.04MByte/sec) Data volume will be 240TByte/5year

Technologies & Challenges Multi-level Buffering(module,crate,PC) Switch Network(Gigabit) Parallel Computing Readout from VME Easy to Upgrade and Port Data/Message storage and good management

Database is needed. System integration: Easy to operating Software Engineering: guarantee good quality

Readout Scheme

. . .

Branch 1

PowerPC VME Modul e

. . .

Tape

Branch M

.. .

VME Crate VME Crate

Tri gger System

.. .

VME Crate. . .

100MEthernet

1000MEthernet

Tri ggerSi gnal

Fi l e Server

Farm Node 1 Farm Node 2 Farm Node N

1000M Swi tch

Readout PC

100M Swi tch

Readout PC

100M Swi tch

Readout PC

100M Swi tch

Farm Supervi sor

Run Control Event Di spl ay Hi stogram Di spl aySl ow Control

100M Swi tch

Readout R&D and Result Test for VME bus and Network

3MByte/sec for programming I/O 13MByte/sec for DMA 100M Network is OK, it is possible that VME bus

readout will be a “bottle-neck” if HPTDC is used. Require

Readout plus transmitting from VME to PC Good performance of FEE board, DMA must be

adopted Other techniques R&D, such as S-link plus ROM VME64x bus

Online System__Event Builder

... ... ...

... ...

DataSegment

DataBlock

Event

Event Bui l der

FEEs

ReadoutCrates

ReadoutPCs

OnlineFarm

Hardware

Level-1 trigger

1 GbSwitch

100 MbSwitch

Online system__Data flow

A B C D E F G HSELECTED

ON-LINE

Farm Node 1

Readout PC

111

2

3 3 3

4 5

6

666

Farm Supervi sor1000M Swi tch

A B C D E F G HSELECTED

ON-LINE

100M Swi tch

Run Control Event Di spl ay

Hi stogram Di spl ay

Fi l e Server

Tape

6

3

Network Connecti on

Control Command

Event Data

Farm Node 2 Farm Node N

Online system__Functions

Online Farm Node• Event Building• Event Data Formatting• Online Event Filtering• Histogram Filling• Event Classification

Farm Supervisor• Keep track of events currently buffered in readout PC• Keep track of events currently processed in Farm

Node• Distribute physics events to Online Farm Nodes• Maintain the event record number

Slow Control Along with BESIII sub-systems designing A Complex System

Monitoring(temperature, humidity, voltage, gas etc) Controlling(high voltage, gases etc) Save/Display history/status information

Purpose Guarantee safety of device and personnel Useful information

Slow Control Strategy

Mature techniques One wire bus USB bus for common devices Database and Web accessing

Commercial Devices Scheme

Not determined, but Consideration going

Summary of DAQ system Determined principal part of DAQ

scheme Slow Control scheme will be soon R&D of DAQ going

Readout model, Online model Key techniques of Slow Control

Improving software process

Details The trigger report of Z.A, Liu The DAQ report of K.J, Zhu The Slow Control of C.S, Gao

Thanks!