15
Trigger Interface and Distribution J. William Gu Jefferson Lab 1. What is TID 2. TID Structure and functions 3. Possible usage in the system 4. TID related boards (Mezz and FANIO) 5. Status
Trigger Interface and Distribution
J. William GuJefferson Lab
1. What is TID2. TID Structure and functions3. Possible usage in the system4. TID related boards (Mezz and FANIO)5. Status
04/19/2023 27/1/2010J. W. GU, Data Acquisition Group
2
1. What is TID
Trigger Interface (TI) + trigger Distribution (TD) = TIDTID has some Trigger Supervisor functions
TS
SD
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
VME
CTP
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
CTP
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
Upto 127 front end crates
04/19/2023 37/1/2010J. W. GU, Data Acquisition Group
3
2. TID Structure and functions
0
2
1
1098
76
54
32
10
12
34
12
12
12
21
12
12
12
12
21
21
21
1 2
12
12
12
1 2
1 2
21
21
21
2 1
21
21
21
21
212
12
1 12
12
121
2
12
12
21
12
12
12
12
21
2121
21
21
21
21
2 1
21
1 2
21
21
21
21
21
21
2 121
21
21
21
21
12
21
21
2 1
21
2 1
12
21
21
2 1
2 1
2 1
21
21
2 1
2 1
2 1
21
21
21
21
21
21
21 2 1
2 1
21
2 1
2 1
2 1
2 1
2 1
21
21
2 1
2 1
2 1
2 1
2 1
2 1
21
21
21
2 1
21
21
21
21
21
2 1
2 1
2 1
21
12
1 2
2 1
1 2
12
21
212
1
21
21 2
1
21
21
21
21
1 2
1 2
1 2
1 2
21
2 1
21
2 1
21
12
12
12
12
21
21
21
21
23
45
67
8
101112131415
1718
1920
2122
2324
26 27 28 29 30 31
1
91625 32
17
21
2 1
12
1 2
1 2
12
12
12
12
12
12
12
12
12
12
21
2 1
2 1
2 1
2 1
1 2
12
12
21
21
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
12
1 2
12
2 1
21
12
12
12
2 1
1 2
2 11
2
1 2
12
21
12
2 1
12
21
1 2
1 2
1 2
12
12
21
12
12
2 1
1 2
2 11
2
1 2
12
21
2 1
2 112
21
1 2
12
1 2
12
2 1
21
12
12
12
2 1
1 2
2 11
2
1 2
12
21
2 1
2 112
21
1 2
1 2
1 2
12
21
2 1
21
12
12
2 1
1 2
2 11
2
1 2
12
21
2 1
12
12
21
1 2
12
21
12
2 1
21
12
12
12
2 1
1 2
2 11
2
1 2
12
21
2 1
2 112
21
1 2
12
1 2
12
21
2 1
21
12
12
12
2 1
1 2
2 11
2
1 2
12
1 22 1
1212
21
1 2
12
1 2
12
2 1
21
12
12
12
2 1
1 2
2 11
2
12
1 2
12
2 1
12
21
1 2
2 1
2 1
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
211 2
21
21
1 221
21
1 221
1 2
21
211 2
211 2
21
21
1 2
2 1
12
2 1
12
21
211 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
21
21
21
21
21
2 1
21
21
21
21
21
21
2 121
21
21
21
2 1
2 1
2 12 1
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
12
12
12
12
12
1 2
1 212
1 2
1 2
12
21
21
21
21
21
1 2
1 2
2 1
1 2
21
2 1
21
21
21
1 2
21
12
12
12
12
21
12
121
21
2
12
21
21
21
21
21
12
21
21
21
21
2 1
2 1
2 1
2 1
2 1
2 1
12
21
21
21
21
21
21
12
2 1
2 1
1 2
12
2 1
21
21
21
2 1
2121
21
21
21
21
21
21
21
21
12
12
1 2
1 2
12
12
2 1
2 1
21
21
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
17
12
12
2 1
1 2
12
12
1212
21
21
21
21
21
33
212 1
2 1
2 1
12
12
12
12
12
12
1 2
1 2
12
34
87
56
2 1
21
21
2 1
21 1
2
12
1 2
12
2525
2525
G2
G6 F6 E6 C6 B6 A6
D11
D10
D9D8
D7D1
G11
G10
G9
G8
G7
F11
F10
F9F8
F7
E11
E10
E9E8
E7
C11
C10
C9C8
C7
B11
B10
B9B8
B7
A11
A10
A9A8
A7
G5
G4
G3
G1
F5F4
F3F1
E5E4
E1
C5C4
C3C1
B4B3
B1
A5A4
A3A2
A1
123
4
12
8
910111213141516
1718
1920
2122
2324
25 26 27 28 29 30 31 32
56
74
3
4
3 1
EPEP
G6 F6 E6 C6 B6 A6
D11
D10
D9D8
D7D1
G11
G10
G9
G8
G7
F11
F10
F9F8
F7
E11
E10
E9E8
E7
C11
C10
C9C8
C7
B11
B10
B9B8
B7
A11
A10
A9A8
A7
G5
G4
G3
G2
G1
F5F4
F3F1
E5E4
E1
C5C4
C3C1
B4B3
B1
A5A4
A3A2
A1
EP
G11
G10
G9
G8
G7
G6
F11
F10
F9F8
F7F6
E11
E10
E9E8
D11
D10
D9D8
E7E6
E1
D7 C7C6
C5C4
C3C1 B1 A1
A2A3
A4A5
B3B4E4
E5
F1F3
F4F5
G1
G2
G3
G4
G5
A7A8
A9A1
0A1
1
B7B8
B9B1
0B1
1
C8C9
C10
C11
D1
A6B6
1717
17
3 12
4 5 6
65
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
910111213141516
87654321
7
910
1112
1314
1516
86
54
32
11
23
45
67
8
1615
1413
1211
109
1816
1412
108
6
1
2220
2317
1913
11
24
57
915
24
321
651 2 3 4
21
12
B1B4
B7B1
0B1
3B1
6B1
9B2
2B2
5B2
8B3
1B2
B6B5
B9B8
B12
B11
B15
B14
B18
B17
B21
B20
B24
B23
B27
B26
B30
B29
B32
Z1A1
Z4Z7
Z10
Z13
A4A7
A10
A13
Z16
Z19
Z22
Z25
A16
A19
A22
A25
Z28
Z31
A28
A31
C1
D1
C4
C7
C10
C13
D4
D7
D10
D13
C16
C19
C22
C25
D16
D19
D22
D25
C28
C31
D28
D31
Z3Z2
A3A2
Z6Z5
A6A5
Z9Z8
A9A8
Z12
Z11
A12
A11
Z15
Z14
A15
A14
Z18
Z17
A18
A17
Z21
Z20
A21
A20
Z24
Z23
A24
A23
Z27
Z26
A27
A26
Z30
Z29
A30
A29
Z32
A32
C3
C2
D3
D2
C6
C5
D6
D5
C9
C8
D9
D8
C12
C11
D12
D11
C15
C14
D15
D14
C18
C17
D18
D17
C21
C20
D21
D20
C24
C23
D24
D23
C27
C26
D27
D26
C30
C29
D30
D29
C32
D32
B3
D32
C32
D29
D30
C29
C30
D26
D27
C26
C27
D23
D24
C23
C24
D20
D21
C20
C21
D17
D18
C17
C18
D14
D15
C14
C15
D11
D12
C11
C12
D8
D9
C8
C9
D5
D6
C5
C6
D2
D3
C2
C3
A32
Z32
A29
A30
Z29
Z30
A26
A27
Z26
Z27
A23
A24
Z23
Z24
A20
A21
Z20
Z21
A17
A18
Z17
Z18
A14
A15
Z14
Z15
A11
A12
Z11
Z12
A8A9
Z8Z9
A5A6
Z5Z6
A2A3
Z2Z3
D31
D28
C31
C28
D25
D22
D19
D16
C25
C22
C19
C16
D13
D10
D7
D4
C13
C10
C7
C4
D1
C1
A31
A28
Z31
Z28
A25
A22
A19
A16
Z25
Z22
Z19
Z16
A13
A10
A7A4
Z13
Z10
Z7Z4
A1 Z1
B32
B29
B30
B26
B27
B23
B24
B20
B21
B17
B18
B14
B15
B11
B12
B8B9
B5B6
B2B3
B31
B28
B25
B22
B19
B16
B13
B10
B7B4
B1
33
2525
25
12
21
2 1
2 121
2 1
2 112
21
2 1
2 112
21
2 1
2 1
2 1
2 121
2 112
1 2
2 1
12
12
12
12
12
12
21
21
21
2 1
21
21
12
12 1 2
12
2 1
2 1
2 1
1 2
1 2
21
21
21 21
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
21
12
12
21
21
12
12
212 1
12
121 2
2 1
2 112
21
21
21
12
1 212
12
121
2
12
12
12
1 212
12
2 1
21
21
12
21
21
21
21
21
2 1
2 1
21
2 1
2 1
2 1
12
12
21
2 1
2 1
2 1
2 112
12
12
12
12
12
12
12
12
12
12
12
12
12
21
21
2 1
12
1 2
EP
2 1
12
12
1 2
1 2
1 2
1 2
2 1
21
21
21
2 1
21
21
21
12
12
12
12
21
21
21
21
21
21
12
12
12
12
12
12
12
211 2
212
1
EP
12
12
12
12
12
12
12
12
12
12
21
21
1 2
21
21
21
21
1 2
21
2 1
2 1
21
21
2 1
21
21
12
21
21
21
21
2 1
21
21
21
2 1
2 1
21
21
21
2 1
2 1
21
21
2 1
21
12
1 2
1 2
1 2
1 2
12
12
1 2
1 2
1 2
1 2
12
1 2
1 2
12
1 2
1 2
1 2
1 2
21
12
1 2
1 2
1 21 2
12
1 2
12
12
121
2
1 2
21
12
121
2
21
21
21
2 1
2 1 2 1
21
1 2
1 212
1 2
1 212
21
21
12
12
12
12
1 2
21
21
1 2
1 2
12
12
12
21
21
12
21
21
21
21
12
21
12
12
12
21
12
12
12
12
12
12
1 2
21
21
12
12
2 1
12
1 2
1 2
12
21
21
21
21
17
12
21
21
21
21
1 21
2
2 1
2 1
2 1
2 1
2 1
21
21
2 1
21
1 2
12
12
1 2
12
21
12
12
12
21
21
21
2 1
21
12
12
12
12
12
12
12
12
12
1 212
1 2
1 2
2 1
21
12
12
12
21
1 2
21
1 2
1 2
21
21
12
2 1
12
12
12
12
12
12
1 2 3 4 5 6 7
14 13 12 11 10 9 8
21
21
21
21
21
21
21
12
Optical IOHFBR-7924#1,#2,#3,#4,#5,#6,#7,#8
TrgSv Rev. 2 interface
External I/O
(trg, clk…)
VMEPROM (FPGA firmware)
Emergency/remotere-programming
VXS P0TD mode: from SDTI/TS mode: to SD
VME 64x
One dedicated link for
redundant data collection
Trg/Clk/Sycoutputs
On row_C
Xilinx Virtex-5LX30T-FG665
04/19/2023 47/1/2010J. W. GU, Data Acquisition Group
4
2. TID Structure and functions
P0_SD_CLK_IN MC100LVEP111
TID_SELECT
CLK250_1
HFBR_1
CLK2ADSyncCLK
HFBR_8
HFBR_7
HFBR_6
HFBR_5
HFBR_4
HFBR_3
HFBR_2
AD9510 O
N_N
B4N840
& SY55857
CLK250_2CLK125
ASEL[1:0]
BSEL[1:0]
P0_CLKA
P0_CLKB
P0_CLKC
P0_CLKDM
C100EP57
CLK2_in CLK2AD
External_In
CLK_OSC
SUBSYS_CLK
TS_CLK
CLKFPGAR
CLK250_3
CLK_FREQ1
CLK3125CLK_FREQ2
CLKSEL[1:0]
SY58607
CLKFPGACLK250_P2
CLKTDC_P2CLKTDC
CLKADC_P2CLKADC
2.1 Clock Distribution
CLK1_in
04/19/2023 57/1/2010J. W. GU, Data Acquisition Group
5
2. TID Structure and functions
FPGA
Front Panel
Mezz. (Rev2)
MC100LVEP14
SY58607ADN2805P0M
C100LVEP14M
C100LVEP14SD_TRG_IN
FPGA_TRIG_1
GTP#1_TX
GTP#5_TX
GTP#3_TX
TS2_TRG_IN
Ex_TRG_IN
GTP#1_RX
GTP#5_RX
HFBR#5HFBR#6
HFBR#7HFBR#8
HFBR#2
HFBR#3HFBR#4
TRG1B
F1_TRG
FADC_TRG
TRG1A
P2_TRG1
HFBR#1
Sel1
Sel3
Sel2
2.2 TD mode, trigger fanout
04/19/2023 67/1/2010J. W. GU, Data Acquisition Group
6
2. TID Structure and functionsHFBR-7934
#1
RX
TX
FPGAXC5VLX30T
MC100EP14
HFBR-7934#4
RX
TX
HFBR-7934#5
RX
TX
HFBR-7934#8 RX
TX
MC100EP14
MC100EP11TS_SD_P0_FAN_IN
GTP#8
GTP#1
GTP#4
GTP#5
GTP#2GTP#3
GTP#6GTP#7
TRIG1
TRIG2
WARNING/BUSY
GTP connection details:All the eight fibers are connected to the FPGA, they are status input and trigger output in TD mode; and trigger input and status output in TI mode.(different FPGA firmware)
04/19/2023 77/1/2010J. W. GU, Data Acquisition Group
7
2. TID Structure and functions
I_delay
I_delay
Encoding
Manchesterdecoding
Syncdecoding
Manchesterencoding O_delay
O_delayMux
TD_CLKSYNC
FPGA
Ext_Sync
P0_CLKSYNC
MC100LVEP111
MC100EP14
SELP0_SyncA
HFBR7924#1
P0_SyncB
P2_Sync
FP_Sync1
FP_Sync2
HFBR7924#8
HFBR7924#2
2.3 Sync signal distributionThe encoding/decoding is implemented in the FPGA, synchronized to the 250MHz clock
04/19/2023 87/1/2010J. W. GU, Data Acquisition Group
8
2. TID Structure and functions
Trigger synchronization on trigger interface using SYNC signal
A FIFO (built in the FPGA) is used to compensate for the DES. latency
T-WO
RD
12
WO
RD 0
T-WO
RD
14
T-WO
RD
13 Ser
Fiber 1THFBR
Fiber nTHFBR
FIFO 1
Des.
Fiber nRHFBR
Fiber 1RHFBR
Des. FIFO n
WO
RD 1
WO
RD 0
WO
RD 1
WO
RD 4
WO
RD 5
WO
RD 2
WO
RD 3
WO
RD 4
WO
RD 2
WO
RD 3
WO
RD 7
WO
RD 8
WO
RD 5W
ORD
6W
ORD
7W
ORD
8 WO
RD 6W
ORD
10W
ORD
11
WO
RD 9
04/19/2023 97/1/2010J. W. GU, Data Acquisition Group
9
2. TID Structure and functions
The front panel will look like the drawing at the right. There are eight optical transceivers in TD mode, and one (or two) optical transceivers plus copper cable connectors in TI mode.
2.4 Front panel:
(always availableTM ) VME remote loading firmware;Serial links to switch slot#A, switch slot#B;Potential fast data link to SD;
2.5 Other features:
04/19/2023 107/1/2010J. W. GU, Data Acquisition Group
10
3. Possible usage in the system3.1 Standard experiment setup: This is the same content drawing as in page 2
TS SD
TID1
TID16
TID2
TID1
TID2
TID8
SD
ADC/TDC
ADC/TDC
ADC/TDC
BUSYTrg/Clk/Sync
Trg/Clk/Sync
Trg/Clk/SyncTrg/Clk/SyncTrg/Clk/SyncBUSY
BUSYBUSYBUSY
Up to 16
Up to 16
Up to 8
Global Trigger Distribution Crate
Front End Readout Crate
TID Boards
One Distribution Crate;Up to 127 Front End Crate,Plus the global trigger crate.
04/19/2023 117/1/2010J. W. GU, Data Acquisition Group
11
3. Possible usage in the system
SD
TID
/TS
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
Front End Crates
Up to 8 crates
3.2 Commissioning/testing setup (or a small DAQ system)
Up to 9 (front end) crates in total
TID as TI (this crate) and TD (up to 8 other crates) with TS function
Front End Crate
04/19/2023 127/1/2010J. W. GU, Data Acquisition Group
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3. Possible usage in the system
TS
SD
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
TI
D
VME
SD
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
TID/TS
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
SD
TID
ADC/TDC
VME
ADC/TDC
ADC/TDC
ADC/TDC
TID/TS
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
ADC/TDC
Global Distribution Crate
Front End Crates
Up to 8 crates Up to 8 crates
Up to 16 TIDs
One global distribution crate,Up to 127 front end crates
One TID/TS per subsystem with Up to 8 crates(It is not required for the subsystem to have its global inputs from the same TID)
3.3 Luxury option: parallel subsystem and global control; doubling the number of optical transceivers (expensive)
04/19/2023 137/1/2010J. W. GU, Data Acquisition Group
13
4. TID related boards (Mezz and FANIO)
4.1 Mezzanine board for TS_Rev2 interface
1
2
2 1
2 1
2 1
2
1
1
2
24
22
16
2
12
14
18
1
34
6
8
10
5
7
9
11
13
15
17
1920
21
23
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
12
34
56
78
910
1112
1314
1516
12
34
56
78
910
1112
1314
1516 3
10
9
8
7
6
5
4
2
1
3
10
9
8
7
6
5
4
2
1
1920
2122
2324
2526
1516
1718
2728
1314
2930
3132
78
910
34
56
MH1
MH2
12
1112
3334
1920
2122
2324
2526
1516
1718
2728
1314
2930
3132
78
910
34
56
MH1
MH2
12
1112
3334
12
34
56
78
910
1112
1314
1516
2 1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
910111213141516
87654321
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
Same connector and jumpers, same component (different package type) as TI_rev2 board;With the Mezzanine board, this TID will behave like a TI_Rev2 board, to work with TS_rev2.Board size: 2¼” x 3¼”
How many mezz. Boards do we need?_____
04/19/2023 147/1/2010J. W. GU, Data Acquisition Group
14
4. TID related boards (Mezz and FANIO)4.2 Fan out board (VME sized board) for CAEN 1290 TDC
9
87
65
14
1717
17
1
11
1
1
11
1 1
1
2 1
21
2 121
21
21
21
2 1
2 1
2 1
21
212
1 21
21
21
212
1
21
21
212 1
212 1
21
2 1
21
1 2
12
12
12
12
1 2
12
12
12
12
12
3456
2 1
2 1
2 1
2 1
2 1
2 1
212 1
2 1
12
34
87
65
56
78
43
21
12
34
87
65
2 121
212 1
21
21
2 121
21
2 121
21
21
21
21
12
2 1
21
2 1
12
2 1
21
2 1
212 1
2 1
21
2 1
21
2112
21
2 1
21
21
21
21
21
21
21
21
2 1
21
2 1
21
21
2 12
1
2 1
2 1
21
2 1 21
2 1
21
2 1
21
2 1
12
34
56
78
910
11
12
13
14
15
16
1718
1920
2122
2324
25
26
27
28
29
30
31
32
12
34
56
78
910
11
12
13
14
15
16
1718
1920
2122
2324
25
26
27
28
29
30
31
32
5758
5960
1920
2122
2324
2526
1516
1718
2728
1314
5556
6162
78
910
34
56M
H1
MH
2
12
1112
6364
2930
5152
5354
3536
3738
3940
3132
3334
4546
4748
4950
4142
4344
5758
5960
1920
2122
2324
2526
1516
1718
2728
1314
5556
6162
78
910
34
56M
H1
MH
2
12
1112
6364
2930
5152
5354
3536
3738
3940
3132
3334
4546
4748
4950
4142
4344
B1B4
B7B1
0B1
3B1
6B1
9B2
2B2
5B2
8B3
1B3
B2B6
B5B9
B8B1
2B1
1B1
5B1
4B1
8B1
7B2
1B2
0B2
4B2
3B2
7B2
6B3
0B2
9B3
2
Z1A1
Z4Z7
Z10
Z13
A4A7
A10
A13
Z16
Z19
Z22
Z25
A16
A19
A22
A25
Z28
Z31
A28
A31
C1
D1
C4
C7
C10
C13
D4
D7
D10
D13
C16
C19
C22
C25
D16
D19
D22
D25
C28
C31
D28
D31
Z3Z2
A3A2
Z6Z5
A6A5
Z9Z8
A9A8
Z12
Z11
A12
A11
Z15
Z14
A15
A14
Z18
Z17
A18
A17
Z21
Z20
A21
A20
Z24
Z23
A24
A23
Z27
Z26
A27
A26
Z30
Z29
A30
A29
Z32
A32
C3
C2
D3
D2
C6
C5
D6
D5
C9
C8
D9
D8
C12
C11
D12
D11
C15
C14
D15
D14
C18
C17
D18
D17
C21
C20
D21
D20
C24
C23
D24
D23
C27
C26
D27
D26
C30
C29
D30
D29
C32
D32
5758
5960
1920
2122
2324
2526
1516
1718
2728
1314
5556
6162
78
910
34
56M
H1
MH
2
12
1112
6364
2930
5152
5354
3536
3738
3940
3132
3334
4546
4748
4950
4142
4344
5758
5960
1920
2122
2324
2526
1516
1718
2728
1314
5556
6162
78
910
34
56M
H1
MH
2
12
1112
6364
2930
5152
5354
3536
3738
3940
3132
3334
4546
4748
4950
4142
4344
D32
C32
D29
D30
C29
C30
D26
D27
C26
C27
D23
D24
C23
C24
D20
D21
C20
C21
D17
D18
C17
C18
D14
D15
C14
C15
D11
D12
C11
C12
D8
D9
C8
C9
D5
D6
C5
C6
D2
D3
C2
C3
A32
Z32
A29
A30
Z29
Z30
A26
A27
Z26
Z27
A23
A24
Z23
Z24
A20
A21
Z20
Z21
A17
A18
Z17
Z18
A14
A15
Z14
Z15
A11
A12
Z11
Z12
A8A9
Z8Z9
A5A6
Z5Z6
A2A3
Z2Z3
D31
D28
C31
C28
D25
D22
D19
D16
C25
C22
C19
C16
D13
D10
D7
D4
C13
C10
C7
C4
D1
C1
A31
A28
Z31
Z28
A25
A22
A19
A16
Z25
Z22
Z19
Z16
A13
A10
A7A4
Z13
Z10
Z7Z4
A1 Z1
B32
B29
B30
B26
B27
B23
B24
B20
B21
B17
B18
B14
B15
B11
B12
B8B9
B5B6
B2B3
B31
B28
B25
B22
B19
B16
B13
B10
B7B4
B1
21
12
21
12
2019
31
30
29
28
27
26
2423
2221
1817
15
14
13
12
11
10
12
34
56
78
916
25
32
2019
31
30
29
28
27
26
2423
2221
1817
15
14
13
12
11
10
12
34
56
78
916
25
32
12
21
12
12
12
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 212
12
12
12
21
21
1
345 2
1
345 2
1
345 2
1
345 2
1
345 2
1
345 2
1
345 2
1
345 2
1
345 2
1
34 5
2
1
345 2
1
34 5
2
12
121 2
12
121 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
34
56
78
1615
1413
1211
109
12
12
2 1
21
12
21
2 1
21
12
25
EP
12
12
21
12
VME
P2
#1 #5
#2 #6
#3 #7
#4 #8
#9 #13
#10 #14
#11 #15
#12 #16
It fans out the TRIGGER, CLOCK (41.7MHz), RESET signals;It merges the BUSY signals (OR);It communicates with VME P2 connectors (with TID);It supports up to 16 CAEN TDCs;One 64-pin cable (on FANIO board) four 16-pin cables (on CAEN 1290)
How many fanout boards do we need?________
04/19/2023 157/1/2010J. W. GU, Data Acquisition Group
15
4 pieces are manufactured, two PCBs are being assembled;Board test starts next week
5. Status
