TRIO-CINEMA 1 UCB, 2/08/2010

Cinema Stein Interface FPGA (CSI)

[Part II]

Karthik Lakshmanan

CINEMA - EE Team

Space Sciences Laboratory

University of California, Berkeley

TRIO-CINEMA 2 UCB, 2/08/2010

Cinema Stein Interface FPGA - Agenda

AGENDA

Overview Block Diagrams Requirements CSI Components Development Plan

TRIO-CINEMA 3 UCB, 2/08/2010

Overview (1/2)

Clyde Space10 x 1U Solar

Arrays

Clyde Space3U EPS

PumpkinPIC33

Computer

MHX2400Spread-

SpectrumTransceiver

Antenna*2

InstrumentInterface

Emhiser1W S-band

ScienceTransmitter

Antenna*2

MAG Sensors

StacerActuator

Preamp /Shaper / ADC

STEIN

+/-2KV HVPS,Bias

ShutterActuator

Torque Coils(2)

V-Slit SunSensor

MAGICElectronics

ClydeSpace30Wh

Battery

UmbilicalConnect.

Stacer

InstrumentLVPS

Overall Context

CSI is an Actel FPGA that resides in the STEIN electronics.

TRIO-CINEMA 4 UCB, 2/08/2010

Overview (2/2)

SHAPER

SHAPER

SHAPER

SHAPERDetector

1

Detec tor 2

Detec tor 3

Det ect or 4

CSI

FPGA

Peak

LLD

ULD

Peak

LLD

ULD

Peak

LLD

ULD

Peak

LLD

ULD SCLK

CDI

ADCCNTL

DEFLECTEDPARTICLES

DAC

Sweep DACSWVolt

TO ACTEL FPGA

ADC

ADC

2X

DATA[15:0]BUSY

ADC

ADC

SYNCH

(BUSED)

SERiAL DAC BUS

DACBIAS

DAC

Test Pulser

READCONVST

SHDN

READCONVST

SHDN

READCONVSTSHDN

READCONVSTSHDN

(Dedicated)

4X

Functional Description of CSI

TRIO-CINEMA 5 UCB, 2/08/2010

CSI Block Diagram

LUT MemoryLUTM

Event ProcessingEVPC

Test PulserGenerator

TPGN

Fixed DAC Control(LLD Thresholds)

FDAC

Sweep DAC ControlSDAC

Fixed DAC Values (4)

SCLKRST

Global

Overall Block DiagramCSI FPGA

02 February 2010

CMDCLK

REGS_CMDPARMS

SDAC DiagMode[1:0]BIAS[15:0]TESTPULSER[15:0]ENBSWEEPDACREGVALS (Diag)

TKPR_ACCUMINT

TKPR_CYCCOUNTS

REGS_PARERR

REGS_CMDPARMS

DETENB(3:0)

Peak (3:0)

SYNCH

REG_CMDPARMS

FDAC(CK, LD, CLR, DAT, CS)

SWDAC(CK, LD, CLR, DAT)

ADCDAT(15:0)

TKPR_CYCCOUNTS

TKPR_ACCUMINT

REGS_CMDPARMS

TPENBTPFREQSEL

TPULSE

READ (3:0)

CONVST(3:0)

SHDN (3:0)

TimekeeperTKPR

TKPR_ACCUMINT

TKPR_CYCCOUNTS

LLD (3:0)

ULD (3:0)

REGS

CMDDATREGS_FRAMERR

EV - FIFO

EVWR FULL

REGS_CMDPARMS

MSIF

ENBTLM REGS_CMDPARMS

TKPR_CYCCOUNTSTKPR_ACCUMINT

NOTE: CMDCLK = SCLK = 8.34MHz

RST = Conditioned PowerOnReset

REGS_SRAMADR/CNTLREGS_SRAMDATIN[15:0]

LUTM_SRAMDATOUT[15:0]SDAC_SRAMADR/CNTL

SDAC_SRAMADR/CNTL

TKPR_TK1STKPR_TK1S

TKPR_TK1S

TKPR_TK1S ENBSWEEP

TRIO-CINEMA 6 UCB, 2/08/2010

Requirements

ID Title Requirement

STE-05 STEIN Count Rate Count up to 30,000 events/sec/detector (TBR)

SFE-03 ADC 4 channels 16 bit >100KHz ADC

SFE-04 Threshold 4 channels programmable LLD DACs, 8+ bits

SHV-02 Sweep Programmable up to 16 (TBR) steps/second with < 4 ms (TBR) timing jitter with 1% (TBR) of full scale resolution. Outputs are independently programmable (TBR)

CDI Interface 16 bits/ADC-Conv, 80KHz events = 1.28Mbps+ 16 bits descriptive tag = 32 bits per event recordInterface bit rate = 8.4MHz, Data rate = 4Mbps (includes CDI Protocol and Message Tag Overhead, “fixed message size” mode)

TRIO-CINEMA 7 UCB, 2/08/2010

CSI Components (1)

Cinema STEIN Interface FPGA Modules

FIXED DAC CONTROL

 

Handles all the LLD Threshold DAC values.

6 DACS onboard

Inputs: SYNCH REGS_CMDPARMS

Registers: Fixed DAC Values(4)

 

Outputs: FDDAC: (CK, LD, CLR, DAT) Load DACs with updated voltage value.

TRIO-CINEMA 8 UCB, 2/08/2010

CSI Components (2)

Cinema STEIN Interface FPGA Modules

SWEEP DAC CONTROL

 

Controls 2 Sweep DACs which increment the detector voltage periodically.

It also periodically (once/second) loads two fixed DACs (BIAS and TestPulser).

IDLE

SYNCH & ACCUMINT

ENABLE SWEEP

RESET

SYNCH

RD LUT

LD DAC

DONEACCUMINT

DONE

DONE

128 steps/second => 32 steps/sweep and 4 sweeps/second. Lookup table based => reconfigurable

InputsACCUMINT:. At every rising edge the SWEEP DAC voltage is updated from the LUT. CYCCOUNTS: CMDPARMSSRAMDATIN: Next voltage value read from LUT.

OutputsSWDAC: (CK, LD, CLR, DAT) Load DACs with updated voltage value.

TRIO-CINEMA 9 UCB, 2/08/2010

CSI Components (3)

LUT MEMORY

It stores the voltage pattern that the Sweep DAC has to follow. 512 bytes of memory (out of 4.25kB available) Loaded by REGS module Read by SWEEP DAC module

Inputs:SRAMDATIN(15:0) Input to memory. This is used when the table is loaded.REGS_ADR Address Input from REGS moduleSDAC_ADR Address Input from SDAC moduleREGS_WR: Write to LUTMSDAC_RD: Read from LUTMENBSWEEP: State of Sweep Subsystem (LUT Write-protected when Sweep is Active)

Outputs:SRAMDATOUT(15:0): Voltage data read from table

TRIO-CINEMA 10 UCB, 2/08/2010

CSI Components (4)

REGS (Command Interface)

Handles interfacing with off-board systems via CDI (Command Data Interface)Interface bit rate = 8.4MHz, Data rate = 4Mbps (includes CDI Protocol)Stores all command parameters. Commands become active at the 1 second tick after they were set.

InputsCMDCLK: Command Clock. Possibly the same as SCLK. The target frequency is 8.34MHz.CMDDAT: Command Data

OutputsREGS_CMDPARAMS: Command Parameters. These include all Register data. Parity and Framing Errors are detected, and commands discarded if an error is present. No feedback is given regarding error-detection or command rejection.

* A detailed description of this interface can be found in pages 10-11 of Reference 3 (MAVEN PFDPU to Instrument ICD).

TRIO-CINEMA 11 UCB, 2/08/2010

Start Bit MSB LSB

Stop Bit CMD

CLK

23 22 21 20 19 1 0 P

Parity Bit

CSI Components (5)

Serial Command Timing

CDI (Command Data Interface) *

Falling Clock Edge to prevent conflict between CMD and CLK signals System synchronises using Start/Stop bits The parity is odd and includes the 24 command bits but not the start bit Command Format is as shown below:

* A more detailed description of this interface can be found in pages 10-11 of Reference 3 (MAVEN PFDPU to Instrument ICD).

TRIO-CINEMA 12 UCB, 2/08/2010

Development Plans

Development

Specification : Revision A just released

FPGA coding language : VHDL

Coding of modules: To begin shortly

Testing: All modules will be unit tested in VHDL