Abstract—The conventional tripole HVDC system, which usesthyristor converters, has some inherent defects. This paper pro-poses an improved scheme which uses the full-bridge submodules-based modular multilevel converters to replace the thyristor con-verters in pole 3, and the converters in pole 1 and 2 are also re-placed by the modular multilevel converters based on half-bridgesubmodules. In order to obtain good performance among threepoles, coordination control is proposed. This paper also proposesvoltage-inverse control and a control strategy of keeping currentzero in pole 3 to suppress overvoltage and to minimize the groundcurrent in transition processes. The performance of the proposedtripole HVDC system is evaluated through PSCAD/EMTDC. Sim-ulation results show that based on the control strategy, the tripoleHVDC system can achieve satisfactory response characteristics intransition processes, maintain the balance of capacitor voltages,and minimize the ground current in the meantime.
Index Terms—Coordination control, F-MMC, full-bridge sub-module (FBSM), keeping current zero, tripole HVDC structure,voltage-inverse control.
I. INTRODUCTION
W ITH THE rapid growth of power demand, it has beenmore difficult for the existing alternating current (ac)
system to meet the requirements of loads. In some areas, dueto the constraints of safe operation, transmission capacities ofac lines are approaching their limits. Although the constructionof new lines is a universal solution to this problem, the lack ofcorridor resources makes it more and more difficult [1]–[3]. Asa result, it is necessary to find other effective ways to expandthe capacities of ac lines.In recent years, researchers have found several methods to
expand the line capacity, such as compact transmission lines,higher temperature wires, and the application of flexible actransmission systems (FACTS) devices [1], [4]. However, itis more attractive to convert the existing ac lines to dc lines[5]–[7], which has not only greater potential for a transmissioncapacity upgrade, but also the capability of rapid power-flowcontrol and network segmentation. In this way, some of the
Manuscript received April 19, 2013; revised September 16, 2013; acceptedMarch 31, 2014. Date of publication April 24, 2014; date of current version July21, 2014. This work was supported by the National High Technology Researchand Development Program of China under Project 2012AA050205. Paper no.TPWRD-00467-2013.The authors are with the Department of Electrical Engineering, Zhe-
at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TPWRD.2014.2315640
Fig. 1. Proposed tripole HVDC system. (a) Structure of the proposed tripoleHVDC system. (b) Topology of F-MMC. (c) Topology of H-MMC.
problems in ac systems may bemitigated and optimized, such asfault extending and aggravation of low-frequency oscillations.In order to convert ac lines to dc and simultaneously expand
the transmission capacity as much as possible, a tripole HVDCstructure with a corresponding current modulation strategy wasproposed in [8]. As shown in Fig. 1(a), the tripole HVDC struc-ture is comprised of a bipole structure and a monopole struc-ture, which are connected in parallel. Compared with the widelyused bipole and monopole HVDC structure, the tripole HVDCstructure has advantages of lower losses, larger transmission ca-pacity, and better overload capability [8]–[10].In the original tripole HVDC structure [8], poles 1 and 2
adopt line-commutated converters (LCC), and pole 3 uses a spe-cial converter comprised of antiparallel thyristors or anti par-allel valves owing to their bidirectional operational requirement.However, the application of thyristors leads to some similar de-fects to the conventional HVDC system, such as dependenceon the ac system voltage, reactive power consumption, filter re-quirements, commutation failures, etc. [11], [12]. In addition,the current modulation strategy of the tripole HVDC structuremight lead to some other defects as follows.
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TABLE IOPERATION STATE OF HBSM AND FBSM
1) In the transition process, the variation of reactive powercannot be compensated in time by reactive compensatorsbecause of their relatively slow actions, which will lead toac voltage fluctuations.
2) In each transition process, converters of pole 3 will expe-rience blocking and deblocking processes. If the blockingand deblocking are not carried out in strict time sequence,it will be prone to arouse overcurrent and overvoltage.
In recent years, the voltage–source converter (VSC) hasemerged as a new force in HVDC transmission, owing to itsfavorable features, such as having no demand for reactivepower supply, operating with a weak or passive ac system,and having no risk of commutation failures. In [13] and [14],VSCs were adopted for pole 1 and pole 2 to optimize operationcharacteristics, but the problems of pole 3 have never beenovercome or mitigated.In this paper, two different types of VSCs will be used as the
converters, that is, the full-bridge submodules (FBSM)-basedmodular multilevel converter (F-MMC) used in pole 3 and thehalf-bridge submodules (HBSM)-based modular multilevelconverter (H-MMC) used in pole 1 and pole 2. As shown inFig. 1(b), F-MMC has bidirectional operation capability ofdc voltage and dc current, and contributes to optimize theoperation characteristics of the tripole HVDC. Moreover,compared with the conventional two-level or three-level VSCs,H-MMC shown in Fig. 1(c) has the merits of modular design,low switching frequency, high efficiency, and excellent outputvoltage waveforms [15]–[17]. By using H-MMC in pole 1 andpole 2, and selecting F-MMC in pole 3 as shown in Fig. 1(a),the operation characteristics of the tripole HVDC systemcould be optimized, and the defects mentioned before could beovercome well.The rest of this paper is organized as follows. Section II intro-
duces the circuit topology and current modulation strategy of theproposed tripole HVDC system. Section III presents the coordi-nation control. Section IV introduces the pole control, includingthe voltage-inverse control and the control strategy of keepingcurrent zero, and the inserted control strategy for FBSMs is alsodiscussed. The simulation result and conclusion of this paper aregiven, respectively, in Sections V and VI.
Fig. 2. Operational characteristics of the tripole HVDC system.
II. CIRCUIT TOPOLOGY AND CURRENTMODULATION STRATEGY
A. Circuit Topology of the Proposed Tripole HVDC System
Fig. 1(a) is the main circuit configuration of the proposedtripole HVDC system. In each converter station, three con-verters are connected to the same commutation bus via Y/transformers, and one dc end of each converter is tied tothe ground point. Similar to the conventional HVDC, the dcpotentials on valve-side windings will be about half of theHVDC line voltage and, therefore, the converter transformers,which are able to withstand dc bias voltages, should be applied.Smoothing reactors are inserted between converters and dclines, which are used to suppress dc current ripples and preventsurges from lines that may cause damage to devices. In theproposed tripole HVDC system, H-MMC shown in Fig. 1(c),is used for pole 1 and pole 2, and F-MMC, shown in Fig. 1(b),is adopted in pole 3.
B. Operation Principle of the FBSM
The topologies of FBSM and HBSM are illustrated inFig. 1(b) and (c), and Table I presents the operation states ofthese two submodules (SMs). HBSM has two different workingmodes: the positively inserted mode and the bypassed mode,while FBSM has an extra negatively inserted mode. In thepositively inserted mode, the operation states of HBSM are al-most the same as FBSM, such as switch states of insulated-gatebipolar transistors (IGBTs), current directions, output voltages,etc., so that the control strategy of HBSM can be applied toFBSM when the arm voltage is positive in F-MMC. The oper-ation states of the negatively inserted mode are opposite of thepositively inserted mode, which gives F-MMC the capabilityto produce negative voltage and operate in bidirectional dcvoltages and dc currents.
C. Current Modulation Strategy
With the reference directions of currents and voltages on thethree poles shown in Fig. 1(a), Fig. 2 demonstrates the voltageand current waveforms of each pole in steady states, where thetransition processes are elaborated in Fig. 5. is a highercurrent level; is a lower current level; is the operationperiod; and is the time interval of the normal process be-tween two transition processes, which is almost equal to /2., illustrated by the blue dashed line, is the dc voltage on each
pole.
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Fig. 3. Operation range of the tripole HVDC system.
In the period , currents of pole 1 and pole 2 change be-tween and , and the current of pole 3 changes between
and to keep the ground current zero,which is dependent on the current variation between pole 1 andpole 2. The current loops of pole 3 are shown in Fig. 1(a), wherethe blue dashed line and red dashed line representand , respectively. Therefore, in order to maintainthe same power transmission direction, the voltage polarity ofpole 3 must be reversed after each transition, while the voltagesof poles 1 and 2 keep constant.
D. Operation Range
Assuming that the absolute values of dc voltages on each poleare equal and constant, that is, , andsetting as the reference voltage, the normalization values ofabove dc voltages are 1.0 p.u. Based on , which representsthe thermal limit of the existing ac conductors, the followingequations can be derived:
(1)
(2)
where and are the normalization values of currentsflowing through the three poles, respectively. In this paper, allvariables refer to their normalization values, which will not beindicated in the following sections.The dc transmission power is described by
(3)
In steady state, the ground current should be limited to aboutzero, so by applying Kirchhoff’s current law (KCL) to theground point, the relationship among three currents can beexpressed as
(4)
According to (1), (2), and (4), the operation range of thetripole HVDC is shown in the shaded area of Fig. 3. Combining(3) and (4), if , otherwise, . It can beseen from Fig. 3 that if the maximum power is expected tobe achieved, 1.37 p.u., 0.37 p.u., and the ampli-tude of will be 1.0 p.u. At this time, is 2.73 p.u., which is1.37 times of the bipole HVDC. Since is larger than ,the cycle between and must be short enough to keepconductor temperature within thermal limits and, in general, theperiod can be taken as 4–5 min [10].
Fig. 4. Control layers of the tripole HVDC system.
Fig. 5. Sequence chart of the coordination control layer.
III. COORDINATION CONTROL UNDER NORMAL OPERATION
Referring to the control system of traditional HVDC systems,the control structure of the tripole HVDC system can be dividedinto three layers: 1) coordination control layer; 2) pole controllayer; and 3) valve control layer. Fig. 4 illustrates the relation-ship among three control layers, where is the modulationindex and is the phase angle. The clock provides the refer-ence of time sequence. After receiving the clock signal and feed-back signals – from the pole control layer, the coordina-tion controller sends control sequence – to the pole controllayer, which is the transition command of voltages and currents.The current order regulator is used as a coordinator of currenttransition orders, such as current amplitudes and changing ratesin different poles.As shown in Fig. 3, in each operation period, there are two
transition processes, in which the currents and voltages of threepoles accomplish their changes. Fig. 5 illustrates the currentcommands of each pole and the voltage command of pole 3 indetail. It can be seen that the commands change gradually toreduce the impact on the system, and the transition process in-cludes three parts: 1) current regulation process 1; 2) voltage-in-verse process; and 3) current regulation process 2. In the cur-rent regulation process 1, current in pole 1 or pole 2 in-creases to with a specific slope given by the current orderregulator, and changes to zero simultaneously, preparing forthe voltage inverse. In the voltage-inverse process, currents ofpole 1 and pole 2 are kept unchanged, and since has beenzero, the change of will not cause the fluctuation of trans-mission power theoretically. In current regulation process 2, the
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Fig. 6. Control block diagram of F-MMC.
current which is not changed in process 1 (current of pole 1 orpole 2), decreases to , and changes to ( or( .The processes mentioned before are triggered by signals– or – . and signify the completion of tran-
sition processes, and provide confirmation signals for otheroperational states, such as power adjustment or reverse powertransmission. Since state variables of the system change vio-lently during the transition process, it is quite undesirable foradditional operations, except for emergencies.
IV. POLE CONTROL AND MODULATION UNDERNORMAL OPERATION
H-MMCs adopted in pole 1 and pole 2 can be controlled bythe method described in [18] and, therefore, this paper focuseson the control of F-MMC in pole 3 only. The control diagramof F-MMC is shown in Fig. 6, where representsone of the three phases, is the -axis component or-axis component in the -frame coordinate, andrepresents the upper arm or lower arm. The control strategy canbe divided into a fundamental layer and a modulation layer.
A. Fundamental Layer
Except for the difference of SMs, the basic operationaltheory of H-MMC is also fit for F-MMC. The equivalent circuitand mathematic model of H-MMC had been elaborated in [18]and [19], and the outer- and inner-loop control are applied forF-MMC. The inner-loop control can be represented as shownin (5), at the bottom of the page, where andare the measured values and reference values of the -axis and-axis current, respectively; and , , and arethe measured values and reference values of the -axis and-axis voltage.As for the outer-loop control, F-MMC needs to control the
dc current and dc voltage, and maintain the stability of reac-tive power. Therefore, one side (converter station 1 or 2) shouldtake constant current control (CCC) and constant reactive power
control (CRC), and the other side takes constant voltage control(CVC) and CRC.
B. Modulation Layer
1) Modified Phase-Shifted Carrier-Based PWM: As shownin Fig. 6, , produced by the fundamental layer, is the innerpotential generated in phase . The modulation signals, that is,the arm voltages, are described as follows:
(6)
where is the rated dc voltage, and represents the polarityof dc voltage. When the voltage is positive, ; otherwise,
.For an F-MMC with FBSMs per arm, the modulation
signal is compared with triangular carriers, and the phaseof each carrier wave is shifted by an angle of 360 . Thecarrier wave is monopolar, and its amplitude is , The desiredarm switching function of an F-MMC can be determined asfollows:
(7)
where function means that when ,and when is the th triangular carrierwave.The voltage modulation ratio is defined as
(8)
where is the amplitude of . Compared with H-MMC,F-MMC has the capability to operate in an overmodulated state,so that can be larger than 1. According to the range of and, the relationship can be described as follows:
andand or
(9)
It can be seen from (9) that might be negative, especiallywhen dc voltage is negative . In this case, it has ex-ceeded the range of triangular carrier waves ( , and themodulation problem will be caused. Therefore, (6) should be re-vised as follows to solve this problem:
(10)
2) Inserted Control Strategy for FBSMs: Take the upper armof phase A for example. Assuming that the number of positivelyinserted SMs is , and the number of negatively inserted SMs is
(5)
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, then the number of bypassed SMs is . The desiredarm switching function through the phase-shifted carrier-basedmodulation is
(11)
The number of SMs with different voltage levels shouldcomply with the following restrictions:
(12)
Assuming that is even, and according to (11) and (12), itcan be derived as
floor or (13)
where function floor rounds the element of to the nearestinteger which is not larger than .According to (11), is proportional to , whichmeans andwill reach their maximum or minimum values at the same
time. When is determined by , and whenis determined by , which can be expressed as
floorfloor
(14)
It can be seen from (12) that the F-MMC has various opera-tion modes with the same desired arm switching function . Themost common modes are: 1) in the condition of ,if is set to 0, the number of SMs with zero voltage levelwill reach the maximum value, which can be called the max-imum zero-level mode and 2) if reaches their maximumvalue, the number of SMs with zero voltage level will be 0 or1 (decided by the parity of ), which is named as the minimumzero-level mode.The operation mode of the F-MMC will have an influence on
the loss of converters, which will not be discussed here. In thispaper, the minimum zero-level mode is adopted.
C. Additional Control in the Transition Process
In the current regulation process, the currents can be con-trolled by CCC without any additional control. But with thevoltage-inverse process, two additional controllers have to beadded: 1) voltage reverse control, that is, balancing the capacitorvoltage and reversing the voltage of pole 3 simultaneouslyand 2) keeping current zero in pole 3, to keep the ground currentbalanced and reduce the fluctuations of transmission power.1) Voltage Inverse and Capacitor Voltage Balancing: The
rise of capacitor voltages might cause damage to insulation,and the decrease of capacitor voltages might disable the voltagecontrol of F-MMC, which indicates the importance of capac-itor voltage stability. Moreover, since DC voltage is supportedby capacitor voltages, capacitor voltage balancing of SMs is thepremise of successful voltage inverse, and their controls are in-terrelated and interact with each other.
Regardless of the capacitor voltage difference among SMs,the arm voltages in phase can be expressed as
(15)
where and are the integer type of and .The output DC voltage is
(16)
Combining (7) and (10), can be rewritten as
floor
floor(17)
If is quite large or the frequency of carrier waves is highenough, the following equation can be given by substituting (16)with (17) :
(18)
Since is ramped in the voltage-inverse process shownin Fig. 5 and is defined to be a constant, (18) is not satisfied.In order to keep constant and make the dc voltage changesmoothly like what is described in Fig. 5, (18) should be satis-fied, so that in (10) should be replaced by a dc voltage order
, which is changeable and ramped in the voltage-inverseprocess. Equation (10) can be rewritten as
(19)
Fig. 7 illustrates a representative simplified voltage-inverseprocess of the upper arm in phase A, where each arm onlycontains six SMs, the modulation ratio is 0.9, and the fre-quency of carrier waves is 50 Hz. It can be seen that when the dcvoltage order changes from the positive to the negative (in Fig. 7(a)), the variation trend of the sum of arm switchingfunction ( in phase A is similar to ). If isquite large or the frequency of the carrier waves is high enough,it can be concluded from (16) that can be treated constant inthis voltage-inverse process, so capacitor voltage balancing ofSMs is realized.2) Keeping Current Zero in Pole 3: Assuming that converter
station 1 adopts CCC and converter station 2 adopts CVC, whenthe voltage of pole 3 starts changing, the voltage in converterstation 2 will be changed by CVC immediately, but in station 1,the voltage will not be changed with station 2 synchronously.The reason is that CCC acts only when current deviation is de-tected. Therefore, the current of pole 3 will fluctuate aroundzero, which causes the fluctuation of dc transmission power andaffects the normal operation of the ac system. On the other hand,the fluctuant current flowing through the ground point will havenegative effects on the underground metal components and acsystems.In order to suppress the fluctuation of current on pole 3, a new
additional controller is applied to CCC. Fig. 8 illustrates the con-trol strategy, where and are the measured voltage
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Fig. 7. Voltage-inverse process of the upper arm of phase A. (a) Modulationprocess. (b) Desired arm switching function.
Fig. 8. Control structure of keeping current zero in pole 3.
and current on pole 3, is the current order of pole 3, andis used for selecting control modes. In the normal process andcurrent regulation process, the CCC mode is selected and thecorresponding proportional coefficient and integral coeffi-cient of the PI controller are selected. In the voltage-inverseprocess, the CVC mode, proportional coefficient , and in-tegral coefficient are selected. In order to achieve the samevoltage response characteristic on both sides of pole 3 and sup-press the current fluctuation to the highest degree, andof converter station 1 should be almost equal to the propor-tional-integral (PI) parameters of CVC in converter station 2.
notes the direction of voltages. When is larger thanzero, 1; otherwise, 0.
V. SIMULATION RESULT
In order to verify the feasibility of the proposed tripole HVDCsystem and corresponding control strategy, a detailed modelbased on the time-domain simulation tool PSCAD/EMTDC isbuilt as shown in Fig. 1. The simulation parameters are listed inTable II where the Bergeron line model is adopted. Except forthe different topologies of SMs (F-MMC for pole 3 andH-MMC
TABLE IISIMULATION PARAMETERS
for pole 1 and 2), the three poles adopt the same system param-eters, and the reactive power of both sides in the poles is 20Mvar. The reference value of power, dc voltage, and dc currentare 40 MW, 40 kV, and 1 kA, respectively. Electric power istransmitted from converter station 1 (sending end) to converterstation 2 (receiving end). In pole 3, the control strategy shownin Fig. 8 is adopted at the sending end, and the receiving enduses CVC.Fig. 9 illustrates the voltage and current characteristics of the
tripole HVDC system in steady state. Actually, if overvoltageand the temperature limit of conductors are taken into consider-ation, the duration for the transition process should be more than4 s, and the periodic time is about 4–5 min [10]. For conve-nience of observation, the simulation time has been shortened. Itcan be seen from Fig. 10 that the system has been in steady stateat 1.0 s. The first transition process is from 1.0 to 3.8 s, 3.8–6.0 sis the normal process, and the second transition process is from6.0 to 8.8 s. The entire transition process is smooth and steady.In the current regulation process, dc voltages of the three
poles in the receiving end are constant because of the CVC,while in the sending end, dc voltages will change with the cur-rents in a small range due to current modulation, as shown inFig. 10. The changing rate of currents should be reasonable forthe prevention of high which may cause overvoltage oninductive components. In addition, with the change of currents,the fluctuation range of dc voltages along the dc lines is certain,which should be taken into consideration in the planning stageto eliminate the possibility of overvoltage.Fig. 11 shows the power curves in the first transition process.
The total active and reactive powers are given in Fig. 11(a) and(b), and Fig. 11(c) illustrates the active and reactive power de-livered by pole 3. It can be seen that in the transition process, thetotal reactive power of three poles and reactive power producedby pole 3 are constant, which benefits from the decoupling con-trol of active and reactive power, and it contributes to the reac-tive power stability and voltage stability of the ac/dc system. As
XU et al.: TRIPOLE HVDC SYSTEM 1689
Fig. 9. Simulation waveforms of the studied system. (a) Currents on pole 1 andpole 2. (b) Current on pole 3. (c) Voltages on pole 1 and pole 2. (d) Voltage onpole 3.
Fig. 10. Simulation waveforms of dc voltages in the sending end. (a) Voltageson pole 1 and pole 2. (b) Voltage on pole 3.
shown in Fig. 11(a) and (c), in the current regulation process, theactive power of pole 3 changes with dc current, and the total ac-tive power varies in a small range from 2.68 to 2.74 p.u. slowly,which is about 2.2% of the rated active power (2.73 p.u.). Thetotal active power at 1.0 s and 2.0 s , and theirdeviation are described as shown in (20), as shown at thebottom of the page, where is the line resistance. It can beseen that the fluctuation of total active power is directly causedby the existence of line resistance, which brings a subtle changeto the dc voltage at the sending end. Compared with the fluctu-ation of total active power in the current regulation process, thefluctuation of total active power in the voltage-inverse processis relatively severe, which varies between 2.63 and 2.74 p.u.,that is, about 4.0% of the rated active power. In Fig. 11(c), from
Fig. 11. Simulation waveforms in the first transition process. (a) Active powerof the tripole HVDC. (b) Reactive power of the tripole HVDC. (c) Active andreactive power of pole 3.
2.0 to 3.0 s, the active power, which should be zero, is also fluc-tuating. It can be ascribed to the charging and discharging ofcapacitors.Fig. 12 illustrates the voltage-inverse process in detail. In
Fig. 12(a), the voltage of pole 3 changes from 1.0 to 1.0p.u. smoothly, which indicates the success of voltage inverse.Figs. 12(b) and 13(a), respectively, show the ground currentwith and without the control strategy of keeping current zero.With the proposed control, the ground current fluctuates in asmall range from 0.03 to 0.03 p.u., while the range will befrom 0.3 to 0.15 p.u. without the control. The control signalsof active currents in the sending end and receiving end of pole3 are shown in Fig. 12(d) and Fig. 13(b). It can be seen inFig. 12(d) that the control signals of active currents in bothends are almost the same with the control strategy of keepingcurrent zero, which contributes to control dc voltages of bothends to be equal and suppressing the ground current. On thecontrary, the control signals of active currents in both ends havea significant difference without the control strategy, as shownin Fig. 13(b).Fig. 12(c) shows the capacitor voltage of an FBSM. It is ob-
vious that the capacitor voltage is balanced in this process, andits fluctuation range reduces with the decrease of the absolutevalue of dc voltage in pole 3. Fig. 12(e)–(h) shows the resultsof phase-shifted carrier-based modulation in the upper arm ofphase A. Since the minimum zero-level mode is adopted, thenumber of inserted SMs with zero voltage level is 0 or 1.The duration of the voltage-inverse process in Fig. 12(a) is
0.8 s. Fig. 14 presents four cases with a different duration time,which is s, s, s, and s, respectively.
(20)
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Fig. 12. Simulation waveforms in the process of voltage transition. (a) Voltageon pole 3. (b) Ground current. (c) Capacitor voltage. (d) Control signals of activecurrents (sending end) and (receiving end). (e) Voltage and itsabsolute value of the upper arm of phase A. (f) Desired arm switching function.(g) Numbers of SMs in an arm with positive voltage level and negative voltagelevel. (h) Numbers of SMs in an arm with zero voltage level.
Fig. 13. Simulation waveforms in the process of voltage transitionwithout con-trol strategy to keep current zero. (a) Ground current. (b) Control signals of ac-tive currents (sending end) and (receiving end).
In order to present the features clearly, the start time of thesefour cases is set to be 2.0, 2.2, 2.4, and 2.6 s. It can be seenfrom Fig. 14 that the shorter the duration time is, the more se-vere the overvoltage and overcurrent will be. This phenomenonis mainly caused by the line capacitance. The current flowingthrough a capacitor is determined by the capacitance and theratio du/dt. When the duration is shortened, that is, du/dt getting
Fig. 14. Simulation waveforms in a voltage-inverse process with different du-ration time. (a) Voltages on pole 3. (b) Currents on pole 3.
larger, the current flowing through a capacitor will increase con-sequently. As a result, overvoltage will be aroused when the cur-rent flows though inductance components. Moreover, the cur-rent will also influence the ground point and the occurrence ofsystem disturbances. In practical engineering projects, the dura-tion time of the voltage-inverse process has to be selected care-fully because of a higher voltage level and larger line capaci-tance, especially when cables are adopted (generally speaking,the capacitance of cables is tens of times greater than that ofoverhead lines). As a result, the overvoltage and overcurrent arequite sensitive to the duration time of voltage reversal, and theycould be prevented if the time is properly selected.
VI. CONCLUSION
This paper proposes a tripole HVDC system which adoptsF-MMCs in pole 3 and H-MMCs in poles 1 and 2. By makinguse of the inherent advantages of MMC, the proposed tripoleHVDC system has merits of no commutation failures, decou-pling control of active and reactive power, reactive power bal-ance in transition process, etc.The operation principle of FBSM is analyzed, and the
bidirectional operation capability of F-MMC is emphasized.In order to obtain good performance among the three poles,the coordination control strategy is put forward. In order toensure normal operation of the tripole HVDC system duringthe normal process, the modified phase-shifted carrier-basedPWM modulation and the inserted control strategy of FBSMsare proposed. Another contribution of this paper is the controlstrategies of voltage inverse and keeping current zero in pole3, which also contributes to the balance of capacitor voltagesand the minimization of the ground current in the transitionprocess. A tripole HVDC system based on H-MMCs andF-MMCs is built in PSCAD/EMTDC to verify the feasibility ofthe system and the proposed control strategies. The simulationresults demonstrate that satisfactory responses of the systemare achieved with the proposed controllers in the transitionprocess and normal process.
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Feng Xu (S’13) was born in Zhejiang, China, inFebruary 1988. He received the B.S. degree inelectrical engineering from Zhejiang University,Hangzhou, China, in 2010, where he is currentlypursuing the Ph.D. degree in electrical engineering.His research interests include HVDC and flexible
ac transmission systems.
Zheng Xu (M’00) was born in Zhejiang, China,in September 1962. He received the B.S., M.S.,and Ph.D. degrees in electrical engineering fromZhejiang University, Hangzhou, China, in 1983,1986, and 1993, respectively.He has been with the Department of Electrical En-
gineering, Zhejiang University, since 1986 and hasbeen a Professor there since 1998. His research areasinclude HVDC, flexible ac transmission systems, andgrid integration of renewable energy.
Huan Zheng was born in Fujian, China, in June1988. She received the B.S. and M.S. degrees inelectrical engineering from Zhejiang University,Hangzhou, China, in 2010 and 2014, respectively.Her research interests include dc distribution sys-
tems and flexible ac transmission systems.
Geng Tang was born in Fujian, China, in August1988. He received the B.S. degree in electricalengineering from Zhejiang University, Hangzhou,China, in 2011, where he is currently pursuing thePh.D. degree in electrical engineering.His research interests include HVDC and flexible
ac transmission systems.
Yinglin Xue (S’13) was born in Hebei, China, inApril 1986. He received the B.S. degree in electricalengineering from Zhejiang University, Hangzhou,China, in 2009, where he is currently pursuing thePh.D. degree in electrical engineering.His research interests include HVDC and flexible
