TRIUMF Qweak Electronics and Its Application to the 12

GeV Møller Measurement

Des Ramsay14 August 2008

800 MHz

20 p.e.per event

x 2500

50,000 eper event

6.4 !A

VME digitalsignal integrator

6.4 V

1 M" I-V

to DAQ

in shielding outside hall

Nature of the Current Mode Signalsfor Qweak

QIBi n 22 #shot noise:

! integrates for 4 ms! stored as four 1 ms integrals! Tsettle as short as 50 !s allowed

Possible DAQ pattern

one spin state – (1/250) second

1 ms

t

next spin state

$200 !s settling time(not to scale)

NIM gate NIM gate

Rapid spin flip reduces noise from target boiling.

Existing Ion Source Signals

• Integration triggered by MPS• signals derived from 20 MHz crystal clock• Qweak integrator uses this clock as well

TRIUMF VME integrator details

FPGA

FPGA Prog/Debug Ports

VME Module SelectSwitches

Status LEDsVME AccessExt Clock EnbExt Gate Enb

Ext NIM Gate

Ext NIM Clock

DC-DCConverter

ADC

8 inputs

filter

Aliasing

• sample at the center of each interval (n samples)• Q = (sum of samples) x (%t)• band limit signal to small fraction of sampling frequency toeliminate the wiggles and kinks.

• we impose an analog cutoff at 1/10 the sampling frequency

Integral From Samples(we want the analog bandwidth low)

Averaging of Digitization Noise(we don’t want the analog bandwidth too low)

• The 18 bit ADCs have ~0.5 LSB rms noise per sample.• This is reduced by averaging ~500 samples per integration.• This will only work if raw signal spreads over enough channels.

• Assuming equivalent noise bandwidth 47 kHz (f3db= 30 kHz)and 18 bit ADC at mid range:

condition Q rms noise before channels channels(e) integration (&) (FWHM)

beam ON 50,000 69 mV 1420 3339best possible 1 0.31 mV 6.3 15

" So this is OK even for very quiet signals." Averaging makes integral equivalent to about 21 bits

! 8 channels, each takes a -10 to +10 volt signal.

! Module triggered by external NIM signal (e.g. MPS)

! Integrates for the selected time (up to 1/30 second)

! Stores sum as 1,2,3, or 4 blocks plus the total sum

! All modules are clocked by the same 20 MHz clock so all are exactly synched

! Internally, 18-bit ADC runs at up to 500 ksps

! 50 kHz sharp-cutoff analog anti-aliasing filter precedes ADC

Oversimplified description of VME Integrator

August, 2008

Comparison of Different Noise Sources for Qweak

Assuming:• 800 MHz event rate• 20 p.e. per event• 2500 PMT gain• 6.4 !A to preamp

Noise source Charge Quantum noise (ppm)beam-ON shot noise 50,000 e 280shot noise during LED tests 2,500 e 63Lowest possible 6.4 !A noise 1 e 1.2

Current source + 1 M" preamp + TRIUMF integrator 2.3Only cable + 1 M" preamp + integrator 1.4

“noise” = Asymmetry width with 16 ms quartets [4 x (1/250)s]

electronic noise is small compared to counting statisticseven the current source test would reach 10-9 (one ppb) in a day

35 GHz

vacuumphotodiode

56 nA

VME digitalsignal integrator

10 p.e.per event

8.4 V

150 M" I-V

to DAQ

in shielding outside hall

A Possible Møller Configuration

QIBi n 22 #shot noise:

Hamamatsu R2046PT vacuum photodiode

Outer diameter: 76 mmLength : 55 mmEffective dia. : 67 mm min.Window : BorosilicatePhotocathode : S-20 multialkaliWavelength : 300 nm – 700 nm

(peak at 420 nm)Sensitivity : 60 !A/Lm min,

80 !A/Lm typDark Current : 100 pA max at 90 VStandard Voltage: 90 V

• TRIUMF ran these at around 50 nA, as did npdgamma.• At 35 GHz, 10 p.e. per event would be 56 nA

Signals from the current mode scanning polarimeter

Peak photodiode current about 50 nA into a 150 M" transimpedance preamplifier

Comparison of Different Noise Sources for Møller

Noise source Charge Quantum noise (ppm)†

beam-ON shot noise 10 e 42lowest possible 56 nA noise 1 e 13

cable +150 M" preamp + integrator ~2

“noise” = Asymmetry width with 16 ms quartets [4 x (1/250)s]

† (divide by ~2 for 1/15 second integral)

(Note that the beam-on shot noise is the same as counting statistics and can only be reduced by increasing the count rate.)

Assuming:• 35 GHz event rate for one octant• 10 p.e. per event from vacuum photodiode• 56 nA to preamp• preamp noise 2 ( referred to input). • note that at 20 C and 150 M"'(

HzV /! HzfA /13HzVkTR /6.14 !#

Other Noise Thoughts for the Møller Measurement

• For the whole detector the counting statistics noise is divided by )8 , butI expect the electronic noise is divided by )16.

• Dave Mack points out that, for the current monitors, the relevant noise is forwhole detector (42 ppm / )8 = 15 ppm for 16 ms quartets). We should be OKfrom an electronics standpoint.

• We might need ~4 ppm normalization from the Lumis to remove target densityfluctuations. Assuming several detectors, we are probably still OK here froman electronics standpoint.

• For low noise and high speed the detector-to-preamp distance mustbe kept small. This will be particularly important if we need high-gain preamps.

END

Main VME registers

August, 2008

Sample Frequency = system clock / (PERIOD_MULT + 40)0 ! PERIOD_MULT ! 255

• Number of Blocks per integral (1,2,3, or 4)• Samples per Block : 1 ! SAMPLE_PER_BLOCK ! 16383• Gate to Trigger Delay = 2.5 !s + (sample period x GATE_DELAY)

0 ! GATE_DELAY ! 255• Gate Source: 0=internal, 1=external• System Clock Source: 0=internal, 1=external• Internal Gate Frequency = (100 kHz) / (INT_GATE_FREQ)

1 ! INT_GATE_FREQ ! 65535• Individual block sums and total sum for each channel• Firmware Revision Date: REV_DATE always shows the release date of the current firmware revision running in the module

! Quasi-differential isolated BNC connectors – 100 k" from BNC outer conductor to ground.

! Input range -10 V to +10 V. Input impedance 12 K".

! Eight integrators per single width VME module.

! Module clocked by 20 MHz signal from ion source. Sampling rate set as a fraction of the clock. Range 68 ksps to 500 ksps with 20 MHz clock.

! Integration time software selectable – set as a fixed number of samples. (e.g. 2000 samples = 4 ms at 500 ksps)

! Module gated by external NIM signal (e.g. MPS). Integration starts a selected time (gate-to-trigger delay) after the leading edge of the gate and runs for preset number of samples.

! 32 bit overall sum available to the DAQ via VME bus. This sum can be divided into 1,2,3, or 4 sub- blocks (time intervals) as selected through VME. At full scale, the sum fills up in 1/30 s at 500 ksps.

! Internal gate and internal 20 MHz clock provided for testing.! 50 kHz, 5-pole anti-aliasing filter! 18 bit ADC, sample rate up to 500 ksps! Buffered output permits reading previous integral during integration.! Crate power 0.5 A at +12 V and 1.0 A at +5 V

Short description of VME Integrator

August, 2008

time

current

3.6 pA(0.6 ppm p-p)( ppm)

6 !Ahelicity- + - + - + -

3.0

Size of Qweak Signal

• figure shows regular spin flip; in practice use + - - + or - + + -

• for 50 kHz noise bandwidth, rms shot noise is 70 nA

• on a scope the noise band would be $ 100,000 x the signal !

*$zA

Signal loss at start of spin states

! If polarization has not settled by start of integration, some signal is lost

! In the case of the above (+ - - +) quartet, more (+) is lost than (-)

! For the parity signal itself, this is only a small part of an already small signaland is likely OK

! In the case of helicity correlated current or position it may be a problem

+ +

- -

++

+ +

• sample at the sides of each interval (n+1 samples)• Q = (average of first and last samples plus sum of others) x (%t)• band limit signal to small fraction of sampling frequency toeliminate the wiggles and kinks.

• we impose an analog cutoff at 1/10 the sampling frequency

Integral From Samples(trapezoidal rule)

TRIUMF VME integrator

solder side:component side:

VME Integrator Front End

Full-differential Quasi-differential

Offset adjust

Chan 1

Chan 2

OutIN

Chan 1 gain

Chan 2 gain

+5 V DC

502510.5

0.512550

M"

M"

Location of adjustments on TRIUMF MK2 “lumi”-style preamp:

Offset adjust

Chan 1

Chan 2

OutIN

Chan 1 gain

Chan 2 gain

+5 V DC

4210.5

0.5124

M"

M"

Location of adjustments on TRIUMF MK2 “main”-style preamp:

Input Cables

Large input capacitance increases the noise gain of the first stage.For Qweak we should limit the input cable capacitance to ~200 pf, for example 5m of RG-62.

Some typical cables:TYPE Z0(ohm) C(pF/M) diameter(mm)RG-58 53 94.4 5.0RG-62 93 44.3 6.2RG-63 125 32.8 10.3

chan 1chan 2Input side

Output side

megohms 50 25 1 0.5 0.5 1 25 50

• In the above example, both channels are set for 0.5 M" transimpedance.

• To change gain move the set switch back towards the input side and move theone you want towards the output side. Note the gains increase away from the center.

• The offset is set for 1.0 volts when shipped, but can be changed with the offset pot

Changing gains and offset on the TRIUMF “lumi”-style preamp

To open the preamp for adjustment, remove the hex nuts from the OUTPUTside and remove the black screws from the INPUT side.

chan 1chan 2Input side

Output side

megohms 4 2 1 0.5 0.5 1 2 4

• In the above example, both channels are set for 0.5 M" transimpedance.

• To change gain move the set switch back towards the input side and move theone you want towards the output side. Note the gains increase away from the center.

• The offset is set for 1.0 volts when shipped, but can be changed with the offset pot

Changing gains and offset on the TRIUMF “main”-style preamp

To open the preamp for adjustment, remove the hex nuts from the OUTPUTside and remove the black screws from the INPUT side.

Firmware Running Modes

• Integration starts at the preset time (set via VME) after the gate.• We have tried three modes:1. No conversion until gate received.2. Continuous conversion – integration starts at next sample period.3. Continuous conversion, but timing is re-synched on each gate.

We noticed, for 4 ms integrals, 500 ksps, and 4 x 1 ms blocks:• Mode 1 – first block in four block integral was low (~25 mV).• Mode 2 – no difference in blocks, but phase of two modules could

differ by half a sample period (1 !s at our 500 ksps).• Mode 3 – initially seemed to solve both problems, but with long runs,

detected small residual block difference (1.5 !V with500-sample blocks).

Neither the block offset or small time offset can affect the asymmetry

Nevertheless, it looks like we can eliminate both by using scheme 3with sufficient gate-to-trigger delay.

E497 DAQ Sequence for One Spin State

150 M" I to V Amplifier