't'rte :° - / I r e otter,=~. , aka AD / r? r f BHARTEND-...

HIGH PERFORMANCE UNIVERSAL ACTIVE ELEMENTS FOR ANALOG SIGNAL PROCESSING

ABSTRACT~--.- .

° "THESIS, = =

SUBMITiTEO)FOR'THE AWARD-O:FTHE, DEGREE OF

't'rte :° -

/ I r e ~ryw ~ t„ ~

otter,=~. , aka AD

-~ ^ _te e - ~l~~ ~• .~

r, J IN ill

f r 1 •L--

(ELECTONICS ENGINEERING

/ r? r

f

BHARTEND-UC-H=i1URVE~DI ce

Under the Supervision of

DR. SUDHANSHU MAHESHWARI

DEPARTMENT OF ELECTRONICS ENGINEERING Z.H. COLLEGE OF ENGINEERING'& TECHNOLOGY

ALIGARH MUSLIM UNIVERSITY ALIGARH (INDIA)

2013

4

'Muslim

ABSTRACT

The field of analog signal processing has developed and matured for the past few decades. The

implementation of analog signal processing circuits in the current domain offers the potential

advantages of higher bandwidth capability, less circuit complexity, wider dynamic range, and

higher operating speed. Consequently, current-mode approach has been accepted as an

alternative means besides the traditional voltage-mode circuits. It is playing an important role in

the development of many new high-performance circuits for signal processing applications. In

addition, current-mode active elements, which comprise voltage and current variables in their

port relations of input and output, haye_p'roved..to, pbssess favorable balance of operational

flexibility and simplicity over -their conventional op-amp counterparts. They are suitable to

operate with signals in currentmode and in voltage-mode, rapidly gaining the acceptance of

researchers as active elements in.1high-performance circuit designs. Current conveyors have

proved to be useful current-mode active. elements, for realizing high performance analog signal

processing circuits. The usability is further extended by employing Differential Voltage Current

Conveyor (DVCC), Differential Difference Current Conveyor (DDCC), Voltage Controlled

Differential Difference Current Conveyor (VC-DDCC), second generation Dual-X Current

Conveyor (DXCC-II).

This Thesis deals with the design and applications of high performance universal active

elements usable in the area of analog signal processing and their various aspects. Some of the

earlier named elements can be called universal since they are versatile enough to realize many

other active elements available in the literature. The Thesis proposes the design of new active

building blocks in form of DXCC-11 with buffered output. The new circuit of Digitally

Controlled DXCC-II (DC-DXCCII) with buffered output is further proposed. The aim of these

proposed active blocks is the realization of analog networks with ease of cascading and

possibility of digitally controlling the parameters of the analog circuits designed around these

building blocks.

Furthermore, a number of applications are realized using DVCCs, DDCCs and DXCC-IIs

as active element along with R-C components. The proposed analog signal processing circuits

THESIS

Jude voltage/current/mixed-mode analog filters, quadrature oscillators and multiphase

usoidal oscillators. Several bilinear networks with the advantageous features of grounded and

v component with appropriate input and output impedances are proposed. First order all-pass

ers and second order filters with diverse features are further introduced in the Thesis. Several

isoidal oscillators with either multiphase or quadrature outputs are also proposed in the work.

active-RC proposal in the Thesis can be easily adopted for CMOS implementation by

lacing the resistors with their active equivalents in form of voltage controlled resistors. The

posed realizations are thus extended to the tunable active-C networks, making them a feasible

economical choice for various analog signal processing functions. With this view some case-

lies are further presented to demonstrate the tunability as well as integration aspects of the

suits. Furthermore, some experimental results are also given.

A complete study of the proposed realizations is carried out both theoretically as well as

ough PSPICE simulations. The discrepancies and the causes have been commented upon. The

esis is expected to enhance the existing knowledge on the subject.

PUBLLSRED PAPERS FROM THE THESIS

P1. S. Maheshwari, B. Chaturvedi, "High input low output impedance all-pass filters using one

active element", JET Circuits, Devices and Systems, vol. 6, pp. 103-110, 2012.

P2. B. Chaturvedi, S. Maheshwari, "Simple voltage mode quadrature oscillator using CMOS

DDCC", International Conference on Multimedia, Signal Processing and Communication

Technologies: IMPACT-2017, IEEE Doi: 978-1-4577-7111, pp. 220-223, 2011.

P3. J. Mohan, B. Chaturvedi, S. Maheshwari, "Grounded components based voltage-mode

quadrature oscillators", International Conference on Multimedia, Signal Processing and

Communication Technologies: IMPACT-2013, IEEE Doi: 978-1-4799-1205-6/13, pp. 241-

245, 2013.

P4. B. Chaturvedi, S. Maheshwari, "Current mode biquad filter with minimum component

count", Active and Passive Electronic Components, vol. 2011, pp. 1-7, 2011.

P5. S. Maheshwari and B. Chaturvedi, "Additional High Input Low Output Impedance Analog

Networks",Active and Passive Electronic Components, vol. 2013, Article ID 574925, 9

pages, 2013. (Doi:10.1155120131574925)

P6. B. Chaturvedi, S. Maheshwari, "Second order mixed mode quadrature oscillator using

DVCCs and grounded components", International Journal of Computer Applications, vol.

58, pp. 42-45, 2012.

P7. 3. Mohan, B. Chaturvedi, S. Maheshwari, "Novel current-mode all-pass filter with

minimum component count", International Journal of Image, Graphics and Signal

Processing, vol. 5, pp. 32-37, 2013.

P8. B. Chaturvedi, S. Maheshwari, "An ideal voltage mode all-pass filter and its applications",

Journal of Communication and Computer, vol. 9, pp. 613-623, 2012.

P9. B. Chaturvedi and S. Maheshwari, "Third-Order Quadrature Oscillator Circuit with Current

and Voltage Outputs", ISR.N Electronics, vol. 2013, Article ID 3 85062, 8 pages, 2013.

(Doi:10.1155/2013/385062)

P10. B. Chaturvedi, S. Maheshwari, "Cascadable band-pass filters using single active element

for low-Q applications", Chinese Journal of Engineering, 2013. (Communicated)

P11. B. Chaturvedi, S. Maheshwari, "Digitally controlled DXCC-II and its application",

International Journal of Circuit Theory and Applications, 2013. (Communicated)

,r

HIGH PERFORMANCE UNIVERSAL ACTIVE ELEMENTS FOR ANALOG SIGNAL PROCESSING

SUBMIT'TEDFOR THE AWARD_OF'T_FE,DEGREE

~ (\\'\\

OF

~~~' ' (f `~ • ~±L 'Pf;~ by { ~ .9 ~

AETa~csl. YEY3 (I /

(LJ i`fJ f f ! I

1~ ~1 \'rr A ~

~ ~~ ; ~7i BYE ~',_,';. •~ ~~ ,~~ rr r

B HART FJNiDcU=GH}AT,UIWE~DI

Under the Supervision of THESIS

DR. SUDHANSHU MAHESHWARI

DEPARTMENT OF ELECTRONICS ENGINEERING Z.H. COLLEGE OF ENGINEERING & TECHNOLOGY

ALIGARH MUSLIM UNIVERSITY ALIGARH (INDIA)

2013

1J, NOV 2014

(Dedt'cated:to

~FamiCy

certificate

It is certified that the Thesis entitled "HIGH PERFORMANCE UNIVERSAL ACTIVE

ELEMENTS FOR ANALOG SIGNAL PROCESSING". submitted by Mr. BHARTENDU

CHATURVEDI, for the award of the degree of DOCTOR OF PHILOSOPHY IN ELECTRONICS

ENGINEERING from Aligarh Muslim University, _Aligarh, .India is a record of candidate's

own work, carried out by him under my supervision. To the best of my knowledge, the

advances embodied in the Thesis have not been used-for..the award of any other degree.

Dated: 2-Q,2.2013 . (Dr. Sudhanshu Maheshwari) DEPART161ENTOF ELECTRONICS ENGINEERING

7.11. COLLEGE OF ENGINEERING & TEcIL 0LoGv ALIGARI% MUSLIM UNIVERSH Y,

AUGARH (INDU) - 202002

11

ABSTRACT

The field of analog signal processing has developed and matured for the past few decades. The

implementation of analog signal processing circuits in the current domain offers the potential

advantages of higher bandwidth capability, less circuit complexity, wider dynamic range, and

higher operating speed. Consequently, current-mode approach has been accepted as an

alternative means besides the traditional voltage-mode circuits. It is playing an important role in

the development of many new high-performance circuits for signal processing applications. In

addition, current-mode active elements, which comprise voltage and current variables in their

port relations of input and output, have proved to possess favorable balance of operational

flexibility and simplicity over their conventional op-amp counterparts. They are suitable to

operate with signals in current-mode and in voltage-mode, rapidly gaining the acceptance of

researchers as active elements in high-performance circuit designs. Current conveyors have

proved to be useful current-mode active elements for realizing high performance analog signal

processing circuits. The usability is further extended by employing Differential Voltage Current

Conveyor (DVCC), Differential Difference Current Conveyor (DDCC), Voltage Controlled

Differential Difference Current Conveyor (VC-DDCC), second generation Dual-X Current

Conveyor (DXCC-II).

This Thesis deals with the design and applications of high performance universal active

elements usable in the area of analog signal processing and their various aspects. Some of the

earlier named elements can be called universal since they are versatile enough to realize many

other active elements available in the literature. The Thesis proposes the design of new active

building blocks in form of DXCC-II with buffered output. The new circuit of Digitally

Controlled DXCC-II (DC-DXCCII) with buffered output is further proposed. The aim of these

proposed active blocks is the realization of analog networks with ease of cascading and

possibility of digitally controlling the parameters of the analog circuits designed around these

building blocks. Furthermore, a number of applications are realized using DVCCs, DDCCs and DXCC-IIs

as active element along with R-C components. The proposed analog signal processing circuits

include voltage/current/mixed-mode analog filters, quadrature oscillators and multiphase

sinusoidal oscillators. Several bilinear networks with the advantageous features of grounded and

low component with appropriate input and output impedances are proposed. First order all-pass

filters and second order filters with diverse features are further introduced in the Thesis. Several

sinusoidal oscillators with either multiphase or quadrature outputs are also proposed in the work.

The active-RC proposal in the Thesis can be easily adopted for CMOS implementation by

replacing the resistors with their active equivalents in form of voltage controlled resistors. The

proposed realizations are thus extended to the tunable active-C networks, making them a feasible

and economical choice for various analog signal processing functions. With this view some case-

studies are further presented to demonstrate the tunability as well as integration aspects of the

circuits. Furthermore, some experimental results are also given.

A complete study of the proposed realizations is carried out both theoretically as well as

through PSPICE simulations. The discrepancies and the causes have been commented upon. The

Thesis is expected to enhance the existing knowledge on the subject.

iv

OJ 1 ''i ii i 1:n 1 vi

I am very much grateful and have immense pleasure in expressing my deep sense of gratitude

to my supervisor Dr. Sudhanshu Maheshwari, Department of Electronics Engineering

Aligarh Muslim University, Aligarh for his innovative ideas, constructive guidance and

expert advice. His advice and research attitude has inculcated me a model for my entire future

career. Without him, this work would have not been completed. He was always available for

his valuable suggestions and critical evaluation of theoretical and simulated results. Working

with him is an invaluable experience and his contribution to this work is more than what can

be expressed in words. For this and much more, I am deeply indebted to him.

I would like to thank Prof. M. Salim Beg, Chairman of the Department of Electronics

Engineering, Aligarh Muslim University, Aligarh.

I would also like to thank Prof. Z. A. Abbasi and Prof. M. A. Siddiqui, who were the

Chairman of the Department of EIectronics Engineering, AIigarh Muslim University, Aligarh

during the course of my work.

I would also like to thank Prof. Iqbal A. Khan for his help in the earlier stages of my

work.

Special thank goes to Management of Jaypee Institute of Information Technology, Noida

for providing excellent research environment and facilities for research activities. I am also

very thankful to the Director of this Institute Prof. Hariom Gupta for his support and

valuable guidance during the writing of my Thesis.

I wish to thank my colleague, Dr. Jitendra Mohan. His work and my technical

discussions with him have improved the quality of this work tremendously.

All of this was made possible by the love and encouragement of my all family members. I

would like to acknowledge the Iove and continual encouragement of my father Dr. Sooraj

Bhan Chaturvedi and my mother Dr. Kaushey Chaturvedi for their moral support and

continue blessings during my entire career. I whole-heartedly express my feeling of

appreciation to my younger brother Dr. Sumit Chaturvedi for his help throughout my

research work. I would also like to thank my elder sister Pinky Sharma for her blessings and

motivation.

v

It is an honour and privilege to express my earnest and profound gratitude to my In-laws

Smt. and Shri Rajesh Lavania for their blessings and constant support.

I have no words in vocabulary to express my deep sense of gratitude to my best friend

and soul mate, my beloved wife Manisha who stood alone and faced the trouble of my

family in my absence which helped me to carry out my research work unperturbed. Her

Ioving and caring support, ungrudged help, unfaltering moral support and constant

reassurance helped me in preparation of Thesis. Finally, I am extremely thankful for the

immense love and understanding from the part of my heart, my son Advit.

I therefore express, once again, my gratitude to all these above mentioned persons as

well as to many others who could not be named in this short, but important paragraph.

Above all, I have done this work by the grace of Almighty God who served as a

beacon light during the course of entire study.

kL4 c -{ (Bhartendu Chaturvedi)

vi

CONTENTS

ABSTRACT iii

ACKNOWLEDGEMENTS v

CONTENTS vii

PUBLISHED PAPERS FROM THE THESIS xii

LIST OF ABBREVIATIONS xiv

LIST OF SYMBOLS xvi

1. INTRODUCTION 1

1.1 Analog signal processing 1

1.2 Historical perspectives 3

1.3 State-of-the-Art 8

1.4 Organization of the Thesis 8

2. UNIVERSAL ACTIVE ELEMENTS 11

2.1 Differential Voltage Current Conveyor (DVCC) 11

2.2 Differential Difference Current Conveyor (DDCC) 22

2.3 Voltage Controlled DDCC (VC-DDCC) 34

2.4 Dual-X Current Conveyor-II (DXCC-I1) 36

2.5 Proposed Dual-X Current Conveyor-II (DXCC-I1) with 48

buffered output

2.5.1 CMOS implementation 48

2.5.2 Non-idealities 50

2.5.3 Simulation results 50

2.6 Proposed digitally controlled active element 60

2.6.1 CMOS implementation 61


2.7 Concluding remarks 62

vii

3. PROPOSED FIRST ORDER ALL-PASS SECTIONS 63 3.1 Voltage-mode circuit using DDCC 64

3.1.1 Circuit description 64 3.1.2 Non-ideal effects 65 3.1.3 Effects of parasitics 65 3.1.4 Simulation results 66

3.2 Voltage-mode circuits using DXCC-II 68 3.2.1 Topology-I 68

3.2.1.1 Filter 1 69 3.2.1.2 Filter 2 69 3.2.1.3 Filter 3 70 3.2.1.4 Filter 4 70

3.2.2 Non-ideal effects 72 3.2.3 Parasitic study 73

3.2.4 Design and verification 74

3.2.5 Experimental realization using AD-844 76 3.3 Voltage-mode circuits using port interchange in DXCC-II 78

3.3.1 Topology-II 78 3.3.1.1 Filter 1 78

3.3.1,2 Filter 2 79 3.3.1.3 Filter 3 79

3.3.1.4 Filter 4 80

3.3.2 Non-ideal analysis 81

3.3.3 Parasitic study 83


3.4 Current-mode all-pass sections using DXCC-II 85

3.4.1 Circuit description 85 3.4.2 Non-ideal analysis 86 3.4.3 Effects of DXCC-II parasitics 87 3.4.4 Design and verification 88

3.5 Conclusion 90

viii

4. PROPOSED SECOND ORDER FILTER CIRCUITS 92 4.1 All-pass filters based on simulated inductor 93

4.1.1 Circuit-I 94

4.1.1.1 Circuit analysis 94

4.1.1.2 Non-ideal analysis 95

4.t-1.3 Parasitic considerations 96

4.1.2 Circuit-II 97



4.1.2.3 Parasitic study 99


4.2 All-pass filters using frequency transformation 101

4.2.1 Circuit-I 102



4.2.2 Circuit-II 104




4.3 Current-mode biquad filter 107

4.3.1 Circuit analysis 108


4.3.3 Parasitic study Ill


4.4 Voltage-mode band-pass filters 114

4.4.1 Proposed circuits 114


4.4.3 Parasitic considerations 117


4.5 Concluding remarks 120

ix

5. PROPOSED OSCILLATOR CWCMTS

5.1 Voltage-mode multi-phase oscillator using DDCC

5.1.1 Circuit description

5.1.2 Non-ideal analysis

5.1.3 Simulation results

5.2 Voltage-mode quadrature oscillator using DDCC



5.2.3 Effects of parasitics

5.2.4 Design and verification

5.3 Grounded components based voltage-mode quadrature

oscillators using DDCC

5.3.1 Circuits description


5.3.3 Parasitic study


5.4 Voltage-mode quadrature oscillator using DXCC-II




5.5 Voltage-mode oscillator using DXCC-II

5.5.1 Proposed circuit


5.5.3 Design and simulation

5.6 Mixed-mode quadrature oscillator using DVCC

5,6.1 Proposed circuit


5,6.3 Parasitic considerations


5.7 Third order mixed-mode quadrature oscillator using DVCC

122

123

123

125

125

127

127

128

129

129

132

132

134

135

136

138

138

139

140

141

141

143

143

144

144

146

147

148

150

x

5.7.1 Proposed circuit 150 5.7.2 Non-ideal analysis 153 5.7.3 Parasitic considerations 153 5.7.4 Design and simulation 154 5.7.5 Circuit enhancement 157

5.8 Conclusion 158 6. INTEGRATION AND TUNING ASPECTS 160

6.1 Resistors 160 6.2 Capacitors 162

6.3 Tunable resistors 165

6.4 Case studies 169 6.4.1 Case study-I 169

6.4.2 Case study-11 173

6.4.3 Case study-III 176 6.4.4 Case study-IV 178

6.5 Concluding Remarks 181

7. CONCLUSION AND FUTURE SCOPE 182 7.1 Contribution to the Knowledge 182

7.2 Suggestions for future work 184

REFERENCES 185

XI

PUBLISHED PAPERS FROM THE THESIS

P1. S. Maheshwari, B. Chaturvedi, "High input low output impedance all-pass filters using one

active element", JET Circuits, Devices and Systems, vol. 6, pp. 103-110, 20I2.

P2. B. Chaturvedi, S. Maheshwari, "Simple voltage mode quadrature oscillator using CMOS

DDCC", International Conference on Multimedia, Signal Processing and Communication

Technologies: IMPACT-2011, IEEE Doi: 978-1-4577-7/11, pp. 220-223, 2011,

P3. J. Mohan, B. Chaturvedi, S. Maheshwari, "Grounded components based voltage-mode quadrature oscillators", international Conference on Multimedia, Signal Processing and

Communication Technologies: AIPACT-2013, IEEE Doi: 978-1-4799-1205-6/13, pp. 241-

245, 2013.

P4. B. Chaturvedi, S. Maheshwari, "Current mode biquad filter with minimum component

count", Active and Passive Electronic Components, vol. 2011, pp. 1-7, 2011.

P5. S. Maheshwari and B. Chaturvedi, "Additional High Input Low Output Impedance Analog

Networks", Active and Passive Electronic Components, vol. 2013, Article ID 574925, 9

pages, 2013. (Doi:10.115512013 /574925)

P6. B. Chaturvedi, S. Maheshwari, "Second order mixed mode quadrature oscillator using

DVCCs and grounded components", International Journal of Computer Applications, vol.

58, pp. 42-45, 2012.

P7. J. Mohan, B. Chaturvedi, S. Maheshwari, "Novel current-mode all-pass filter with

minimum component count", International 'Journal of Itnage, Graphics and Signal


P8. B. Chaturvedi, S. Maheshwari, "An ideal voltage mode all-pass filter and its applications",

Journal of Corrnrrunication and Computer, vol. 9, pp. 613-623, 2012.

XI

P9. B. Chaturvedi and S. Maheshwari, "Third-Order Quadrature Oscillator Circuit with Current

and Voltage Outputs", ISRN Electronics, vol. 2013, Article ID 385062, 8 pages, 2013.

(Doi; 10.1155/2013/385062)

P10. B. Chaturvedi, S. Maheshwari, "Cascadable band-pass filters using single active element

for low-Q applications", Chinese Journal ofEngineering, 2013. (Communicated)

P11. B. Chaturvedi, S, Maheshwari, "Digitally controlled DXCC-II and its application",

International Journal of Circuit Theory and Applications, 2013. (Communicated)

3

LIST OF ABBREVIATIONS

AC Alternating Current

BiCMOS Bipolar Complementary Metal Oxide Semiconductor

CC Current Conveyor

CC-I First Generation Current Conveyor

CC-U Second Generation Current Conveyor

CC-III Third Generation Current Conveyor

CDBA Current Differencing Buffered Amplifier

CFA Current Feedback Amplifier

CFOA Current Feedback Operational Amplifier

clk Clock

CM Current-Mode

CMAPF Current-Mode All-Pass Filter

CMOS Complementary Metal Oxide Semiconductor

CO Condition Of Oscillation

dB Decibel

DC Direct Current

DDCC Differential Difference Current Conveyor

DDA Differential Difference Amplifier

DVCC Differential Voltage Current Conveyor

DXCC-II Dual X Second Generation Current Conveyor

FDCCII Fully Differential Second Generation Current Conveyor

FDNR Frequency Dependent Negative Resistance

Fig Figure

FO Frequency of Oscillation

IC Integrated Circuit

ICC-II Inverting Second Generation Current Conveyor

KCL Kirchhoff Current Law

MOS Metal Oxide Semiconductor

OP-AMP Operational Amplifier

OTA Operational Transconductance Amplifier

xiv

PSPICE Simulation Program with Integarted Circuit Emphasis

RC Resistor Capacitor

sin Sine Waveform

THD Total Harmonic Distortion

TSMC Taiwan Semiconductor Manufacturing Company

VC Voltage Controlled

VCVS Voltage Controlled Voltage Source

VLSI Very Large Scale Integration

VM Voltage-Mode

VMQO Voltage-Mode Quadrature Oscillator

xv

LIST OF SYMBOLS

a Non-ideal Current Transfer Gain

fj Non-ideal Voltage Transfer Gain

y Non-ideal Voltage Transfer Gain

E; Current Tracking Error

~v Voltage Tracking Error

0 Phase

H Gain

coo Pole or Angular Frequency

Degree

um Micrometer

p Mobility of Carriers

C Capacitance

Cox Gate Oxide Capacitance per Unit Area

Hz Hertz

ID Drain Current

I Current Flowing in the Transistor, MM

k Boltzmann Constant

K Transconductance Parameter Of The Transistor

MM CMOS Transistor

Q Quality Factor

R Resistance

C Capacitance

Cc Coupling Capacitance

xvi

L Inductance

L31, Simulated Inductance

g„r Transconductance

D Frequency Dependent Negative Resistance

CD Capacitance of the FDNR

S Sensitivity

s =jw Complex Parameter-Laplace Operator

I Current

V Voltage

VC Control Voltage

VBB Biasing Voltage

VDT, Vss Supply Voltages Of CMOS Structures

VDS Drain to Source Voltage

VAS Gate to Source Voltage

VG Gate Voltage

VT Threshold Voltage

W, L Channel Width and Length of CMOS Transistor

Z Impedance

% Percentage

S2 Ohm

KS~ Kilo Ohm

MI) Mega Ohm

pF Pico Farad

nF Nano Farad

VF Micro Farad

mH Mili Henry

xvii

mV Mili Volt

V Volt

µA Micro Ampere

mA Miii Ampere

A Ampere

MHz Mega Hertz

GHz Giga Hertz

LP Low Pass

HP High Pass

BP Band Pass

xviii

CHAPTER 1

INTRODUCTION

During the last many decades, analog and digital circuit designers considered voltages as the

most important circuit variable, although many of the signals encountered in circuits and systems

are actually currents in their initial state. The reason, why current signal processing was not able

to establish itself until now, was the missing high performance current processing circuits.

Although there are numbers of well established building blocks for voltage processing circuits,

e.g. operational amplifiers, comparators, etc., there was not enough attention paid to the design

of similar building blocks for current processing circuits.

A current conveyor belongs to the category of current processing building blocks. It is

very useful building block consisting of both voltage and current sub-blocks. Current conveyors

were introduced in the late sixties by Sedra and Smith. They were considered to be used as

controlled voltage and current sources, impedance converters, function generators, amplifiers,

filters etc. In the beginning of their appearance, the performance of current conveyors was

limited by the available technologies, which did not allow well-matched devices on fabricated

chips. Since the technologies have improved, the current processing blocks have also gained

attention of many analog designers. Today the current conveyors have developed to very useful

building blocks of analog signal processing and their main application areas are in high-speed,

high frequency circuits for both voltage-mode and current-mode signals.

1.1 Analog Signal Processing

Nowadays, the design of analog integrated circuits is an area of significance. As the

technology forges ahead, the performance/cost potential of the complete system cannot be fully

realized until integrated circuits with analog input and output can be implemented. Many new

high-performance devices have now been integrated with different advancements in IC

processing techniques. This in turn has led to a renewed interest in the analog circuit design

techniques. In the last decade, huge numbers of high performance devices were reported for this

purpose. An example is the development of "current-mode" techniques [1], many of which have

1

only become practically feasible with the development of true complementary bipolar and MOS

technology processes.

Voltage-mode analog circuit design is called a "traditional" nowadays. Current-mode

signal processing circuits have recently demonstrated many advantages over their voltage-mode

counterparts including higher bandwidth capability, greater Iinearity, higher operating speed and

wider dynamic range [1]. In addition, current-mode processing often leads to simpler circuitry

and lower power consumption. It is playing a significant role in the development of many new

high-performance circuits for signal processing application.

In the current scenario, CMOS VLSI is used to perform information processing more and

more in the digital area. However, the interface between the analog outside world and the digital

processor will continue to be analog in nature. Analog circuits are only competitive with digital

circuits in performance and area. Analog circuit design has historically been viewed as a voltage

dominated form of signal processing. Recently, current-mode analog circuits have emerged in

the implementation of analog functions. Due to many potential advantages [1-3], the current-

mode circuits have received considerable attentions as an alternative for signal processing

applications.

In CMOS technology, developments have centered on a new generation of analog

sampled data processing that may be referred to as switched or dynamic current circuits. These

circuits include switched current filters, dynamic current mirrors and memory cells. On the other

hand, novel special analog building blocks have been developed opposite to voltage-mode

classical blocks. These blocks, including current amplifiers, current followers, current conveyors

and others, can be called as "adjoint" to voltage amplifiers, voltage comparators, followers and

so on.

CMOS technology has become a dominant analog technology because of good quality

capacitors and switches. Furthermore with growing CMOS VLSI, current-mode analog design

techniques play an important role in successfully exploiting this technology in the analog

domain. As a consequence many of the early current-mode circuit techniques are enjoying a new

beginning and a new generation of current-mode analog building blocks and systems.

r

01

The advancement of the semiconductor technology in the last few decades had significant

impact to the research and development activities on electronic circuit and systems with

enormous coverage on analog signal processing. The impact had further renewed with

introduction of the versatile monolithic Integrated Circuit (IC) building block termed as

operational amplifier (op-amp) [2, 4]. The op-amp device is essentially a Voltage Controlled

Voltage Source (VCVS) element. Since its beginning, the op-amp element had been widely used

for various voltage mode circuit design covering widespread areas of applicabilities in analog

signal processing [2, 4]. Among these, the design of passive inductor-less active op-amp-RC

function circuits, e.g., integrators/differentiators, active filters, phase equalizers, wave generators

are quite popular, useful and IC-adaptable, since passive inductances are not compatible to IC

technology. The approach subsequently gave way to synthesize active immittance functions by

op-amp RC methods. During this track of research activity, Bruton suggested a new type of

immittance function known as the Frequency Dependent Negative Resistance (FDNR) [5]. In

this way of progress on analog signal processing circuit and system design, there emerged newer

types of active building block viz., the Operational Transconductance Amplifier (OTA) and the

Current Conveyor (CC), Many researchers had contributed elegant schemes on analog signal

processing circuit design using the OTA and the current conveyor in its various forms in the

recent past [1].

Recently, another new device, known as the Current Feedback Amplifier (CFA) had been

introduced, which is a versatile building block compatible to both voltage-mode and current-

mode functioning [1]. This is essentially a unity gain current transfer device wherein the voltage

across its trans-impedance can be copied at voltage source output nodes. The unique property of

the device is now commercially available as an off the shelf items as AD-844 IC. The CFA

element is receiving considerable interest on the R&D activities also in areas of analog signal

processing circuits [6, 7].

1.2 Historical perspectives

One of the most basic building blocks in the areas of current-mode analog signal

processing is the Current Conveyor (CC). It is a four (in basic form) terminal device which when

arranged with other electronic elements in specific circuitry can perform many useful analog

signal processing functions. In many ways current conveyor simplifies circuit design in current- 3

mode, in a manner similar to the conventional operational amplifiers (op-amp) in voltage-mode.

The current conveyor offers an alternative way of abstracting complex circuit functions, thus

aiding in the creation of new and useful implementations. Moreover, current conveyor is a

mixed-mode universal building block, which can substitute classical op-amps in voltage-mode

applications as well and provides an option to transform these applications to current-mode.

A lot of work has demonstrated the universality, advantages and novel applications of the

current conveyor since its first introduction in 1968 [8]. Concurrently with these works, a

number of researchers have outlined improved implementations designed to enhance the

performance and utility of this building block. Some existing current conveyors are discussed

below.

D First generation current conveyor (CC-1)

The current conveyor was originally introduced as 3-port device [8]. The

operation of this device can be described as: if a voltage is applied to input terminal Y, an equal

potential will appear on the input terminal X. In a similar fashion, an input current being forced

into terminal X will result in an equal amount of current flowing into terminal Y. Finally, the

current flowing into terminal X will be conveyed to output terminal Z. Note that Z output

terminal has characteristics of a current source with high output impedance. Voltage at X

terminal is independent on the current forced into this port. Similarly, the current flows through

input Y is fixed by current through X terminal and is independent on Y potential. The

functionality of CC-I can be described by following matrix;

ly 0 1 0 VI - 1 0 0 Ix I2 0 ±1 0 VZ

where ± denote positive and negative types of CC-1, respectively.

4

I

The symbol of CC-I is shown in Fig. I.I.

zY Vy Y CC-I

Iz_ z-- ±— V. a-

X

Ix

Figure 1.1 Symbol of CC-I

➢ Second generation current conveyor (CC-If)

To increase the versatility of the current conveyor, second generation in which no

current flows in terminal Y, was introduced [9]. This building block has proven be more useful

than CC-I. CC-II can be described by following matrix:

f,. 0 0 0 Vr Vx = 1 0 0 IX (1.2) IZ 0 ±1 0 Vz

where ± denote positive and negative types of CC-II, respectively.

The symbol of the CC-II is shown in Fig. 1.2.

Iz+

Iv

Y CC-II I.

(_-0 V z- x

T1C

Figure 1.2 Symbol of CC-II 5

r

From equation (1.2), it is clear that terminal Y exhibits infinite input impedance. The voltage at

X terminal follows the voltage of Y terminal, X exhibits zero input impedance, and current flows

through X port is conveyed to the high impedance output terminal Z. Current flows through Z

terminal with same orientation as current through the terminal X (CCII+) or opposite polarity in

case of CCII-. CC-II has proven to be considerably more useful type of the current conveyor

family. Wide range of applications was reported. It is very suitable building block for design of

the active-RC filters or number of special immittance (admittance) or/and simulators. CC-II is

also used as a powerful building block for low voltage applications.

➢

Third generation current conveyor (CC-Ill)

Current conveyor-III was reported in 1995 [10]. The operation of the third

generation current conveyor (CC-III) is similar to that of the first generation of current conveyor

(CC-i), with the exception that the currents in ports X and Y flow in opposite directions (A= -1).

As the input current flows into the Y-terminal and out from the X terminal, the CC-III has high input

impedance with common-mode current signals, i.e. identical currents are fed both to Y and X terminals.

Therefore common-mode currents can push the input terminals out from the proper operation range.

Therefore this conveyor is used as current probing. CC-III can be described by following matrix:

_TY o —1 d VY

VX = 1 0 0 IX (1.3)

L' ] 4 ±1 oiLi VZ where ± denote positive and negative types of CC-III, respectively.

The symbol of CC-III is shown in Fig. 1.3.

Iz}

Z+ Vz~ Iy

V' Y CC-III Iz-

Z— ~! Vz- x

Figure 1.3 Symbol of CC-III 6

➢ Inverting second generation current conveyor (ICC-II)

The first inverting current conveyor i.e. the inverting second-generation current

conveyor (ICC-II) was described in [11]. The general matrix description of the second generation

inverting current conveyor is as:

Ir 0 0 0 VY VX _ —1 0 0 I X IZ 0 ±1 0 Vz

where th denote positive and negative types of ICC-II, respectively.

The symbol of ICC-II is shown in Fig. 1.4.

TZ+

IY

Vy 4 ICC II

I2_

IX

VX

Figure 1.4 Symbol of ICC-TI

Current conveyors with differential inputs

The most used type of the current conveyors is the second generation current

conveyor (CC-II) [12]. A number of very important analog building blocks can be realized with

CC-II, e.g. all types of control sources, impedance inverters and converters, and many others.

However, one disadvantage of CC-II in some cases can be observed. Conventional CC-II can not

be used in applications demanding differential or floating inputs like impedance converter

circuits and current-mode instrumentation amplifiers. The design of such an amplifier requires

two or more CC-Ils. This problem has been solved with the help of special current conveyors-

current conveyors with differential inputs, e.g. Differential Voltage Current Conveyor (DVCC) 7

(1.4)

[ 13], Differential Difference Current Conveyor (DDCC) J14] etc. The DVCC and DDCC are

relatively simple and useful building blocks, which keep all advantages of CC-II and cancel the

disadvantage of single high-impedance input terminal.

In this section a number of current conveyor types were presented. Some of them could

become powerful functional building blocks for monolithic ICs.

1.3 State-of-the-Art

Research in analog integrated circuits has recently gone in the direction of low-voltage

and high-speed design, especially in the environment of the portable systems where a low supply

voltage, given by a single-cell battery, is used. In this area, traditional voltage-mode techniques

are going to be substituted by the current-mode approach, which has to be advantageous to

overcome the gain-bandwidth product limitation, typical of operational amplifiers. Inside the

current-mode architectures, CC-II can be considered as basic circuit block because all active

devices can be made of a suitable connection of one or two CC-IIs. CC-II is particularly

attractive in portable systems, where low voltage constraints have to be taken into account. In

fact it suffers less from the limitation of low current utilization, while showing full dynamic

characteristics at reduced supplies (especially CMOS versions) and good high frequency

performance. Recent advances in integrated circuit technology have also highlighted the

usefulness of CC-ll solutions in large number of signal processing applications.

In the present days a number of trends can be noticed in the area of analog filter and

oscillator design, namely reducing the supply voltage of integrated circuits and transition to the

F current-mode [1]. On the other hand, voltage-mode and mixed-mode circuit design still receives

considerable attention of many researchers. Therefore, the proposed circuits in this Thesis are

working in current-mode or voltage-mode or mixed-mode.

1.4 Organization of the Thesis

The Thesis is elaborated in seven chapters. The organization of this Thesis is described

below.

Chapter 2 starts with the overview of active devices namely Differential Voltage Current

Conveyor (DVCC), Differential Difference Current Conveyor (DDCC), Voltage Controlled-

0

Differential Difference Current Conveyor (VC-DDCC) and second generation Dual-X Current

Conveyor (DXCC-II) along with their CMOS implementation. Detailed performance study and

device verification are also given. This chapter further proposes DXCC-II with buffered output

and Digitally Controlled DXCC-II (DC-DXCCII) with buffered output. Implementation of

DXCC-II with buffered output and DC-DXCCII with buffered output in CMOS technology

along with non-ideal study and simulation results is also proposed. These active building blocks

are further used in Thesis for the realization of various applications.

Chapter 3 proposes different novel first order all-pass sections. Firstly, a new circuit of

first order voltage-mode all-pass filter using DDCC is proposed. Eight new first order voltage-

mode all-pass filters based on new proposed topologies are also included. Finally, two novel first

order current-mode all-pass filters employing a single DXCC-I1 are proposed. All the circuits

possess appropriate impedance levels.

Chapter 4 is focused on the design of new second order filters. Firstly, two all-pass filters

based on simulated inductor are proposed. Floating simulators have been employed to overcome

the drawbacks of passive inductors. Next, two circuits of all-pass filter using frequency

transformation are proposed. Transformation technique has been also employed in this chapter to

realize simpler alternative with lesser circuit complexity. Furthermore, a new second order

current-mode filter circuit employing grounded components is proposed. The circuit uses a

minimum number of components required to achieve a second order transfer function. Three

types of transfer functions are available at once, without any circuit modification. In the last,

-r

single active element based two new second order band-pass filters with the feature of high input

and low output impedance are proposed. Both the circuits are simple and contain a minimum

number of active components required to achieve a second-order transfer function. The proposed

circuits benefit from low active and passive sensitivities. Although the proposed circuits are

designed for low-quality factor property, they can be used for cascading in different applications

at high frequency also. Extensive simulations are performed to validate the proposed theory.

Chapter 5 deals with several new oscillator circuits. Most of the proposed circuits are

simple and contain a minimum number of components required to achieve quadrature

oscillations or multi phase oscillations. All the circuits enjoy the feature of low active and

passive sensitivities. P7

Chapter 6 explores the integration and tuning aspects. The passive elements in form of

resistors and capacitors can also be made compatible in CMOS technology. This chapter

discusses the fabrication possibilities of these passive components in CMOS technology. This

chapter further presents case studies whereas tunability aspects of some of the circuits are

studied.

In Chapter 7, conclusions are drawn and the original contributions of this Thesis are

summarized. Finally suggestions for further research are given.

The non-ideal analysis as well as the effects of parasitics is also included to complete the

study of performance of the all proposed circuits. All the proposed circuits are designed and

simulated using PSPICE. One experimental setup is also given for presentation of the results.

10

CHAPTER 2

UNIVERSAL ACTIVE ELEMENTS

Second-generation current conveyors (CCIIs) [12] have been found very useful in many

applications. This is attributed to their higher signal bandwidths, greater linearity, and larger

dynamic range than those of the operational-amplifiers (op-amps) based ones. Ever since its

introduction, many modifications have been made to increase the versatility of the active

element, such as differential voltage current conveyor (DVCC) [13], differential difference

current conveyor (DDCC) [14], dual X current conveyors (DXCC-II) [16] etc. In the most

modern high performance analog integrated circuits, differential circuits are needed since it

improves the performance of analog systems in terms of noise rejection, dynamic range through

the cancellation of even harmonics, as well as to suppress the effect of coupling between various

blocks. DVCC, DDCC and DXCC-II are versatile active elements which can simplify the design

of active networks. Most of the active elements named above (CC-II, DVCC/DDCC etc.) can be

called universal in the sense that these can be used stand alone to realize several other current-

mode active elements being used and introduced in literature.

This chapter includes the brief introduction of DVCC, DDCC, VC-DDCC, DXCC-II,

DXCC-II with buffered output and DC-DXCCII. In section 2.1, implementation of DVCC in

CMOS technology is given. In section 2.2, CMOS implementation of DDCC is presented. VC-

DDCC is discussed in section 2.3. The CMOS implementation of DXCC-Ii is presented in

section 2.4. Furthermore, two new active elements are proposed. In section 2.5, implementation

of DXCC-II with buffered output in CMOS technology along with non-ideal study and

simulation results is proposed. In section 2.6, CMOS implementation of DC-DXCCII is

proposed. This chapter also presents the PSPICE simulated results for all active elements, which

verifies the dc, ac and transient behavior of these universal active elements.

2.1 Differential Voltage Current Conveyor (DVCC)

The Differential Voltage Current Conveyor (DVCC) is an extension of the second-

generation current conveyor (CC-ll) introduced by Sedra and Smith [12]. The CC-II has a

disadvantage that only one of input terminals has high input impedance (Y terminal). This

disadvantage becomes evident when CC-II is required to handle differential signals, as in the

11

case of instrumentation amplifier. The design of such an amplifier requires two or more CC-II's.

The DVCC is a building block specially defined to handle differential signals [13].

➢ CMOS implementation of DVCC

The DVCC is a five-port building block which is defined by the following matrix

equation:

VX 1 r 0 1 —1 0 0 I X 'Y , 0 0 0 0 0 v~, 'Y2 = 0 0 0 0 0 VY2 (2.1)

Iz} 1 0 0 0 0 VZ+

IZ_ —I 0 o 0 0 Vz_ where,

VY1= Voltage at Yi terminal IY2 = Current at Y2 terminal

'VY2 = Voltage at Y2 terminal Iz+ = Current at Z+ terminal

Vx = Voltage at X terminal Iz_ = Current at Z- terminal

lyi = Current at Yi terminal Ix = Current at X terminal

The difference of the Y1 and Y2 terminal voltages is conveyed to the X terminal; the current

input at the X terminal is conveyed to the Z,. terminal with the same polarity and to the Z-

terminal with inverse polarity. The DVCC is characterized by high input impedance at the Y1

and Y2 terminals, high output impedance at the Z+ and Z- terminals and low impedance at the X

terminal.

The symbol of the DVCC is shown in Fig. 2.1.

r IY1 IZ+

VYl 7['i

DVCC zZ_

VY2 0 Y2 z- 0 Vrj-

1Y2x

z

TIX

A'x

Figure 2.1 Symbol of DVCC

12

VI

The DVCC is a versatile building block for applications demanding floating inputs. The CMOS

implementation of the DVCC [13] is shown in Fig. 2.2.

Vss

Figure 2.2 CMOS implementation of DVCC [13]

All transistors operate in saturation region and the sources are connected to bulk/substrate.

Transistors M5 and M6, work as a current mirror which are set to drive two differential

amplifiers consisting of transistors MI, M2 and M3, M4 respectively. Transistors M7 and MI4

provide the necessary feedback action to make the voltage Vx independent of current drawn

from the terminal X. The current through terminal X is conveyed to the Z+ terminal with the help

of transistors M7, M8, M14 and M15. By using extra current mirror the current is conveyed in an

inverted manner to the Z- terminal.

➢ Non-ideal analysis

Taking the non-idealities of the DVCC into account, the relationship of the

terminal voltages and currents of the DVCC can be rewritten as:

13

Vx 0 flkt — )3k2 0 0 I X 'Y, 0 0 0 0 VY,

Ire 1=1 0 0 0 0 0 VY2 1 (2.2)

1z► aki 0 0 0 0 Yz+ z_ — c k2 0 0 0 0 Vz-

where, /3k/(S), flu(s) represent the frequency transfers of the internal voltage followers and akf(s), ak2(s) represent the frequency transfers of the internal current followers of the kth-DVCC,

respectively. If DVCC is working at frequencies much less than the corner frequencies of/3k!(s),

/3k2(s), akl (s) and ak2(s), namely, then /iki(s) = uk1=1-ckv f where, sk,j (Ick„!J <<I) denotes the

voltage tracking error from the Y, terminal to the X terminal of the kth—DVCC; /3k2(s) = &2=I-

EL-v2 where, ah 2 (k 2I <<1) denotes the voltage tracking error from the Y2 terminal to the X

terminal of the kth—DVCC; akl(s) = aki =1-aklr where, E f (Ieki1f <<1) denotes the current tracking

error from the X terminal to the 7.+ terminal and ak2(s) = ak2 =1-sk,2 where, 2k12 (Is. 2[ «l) denotes

the current tracking error from the X terminal to the Z- terminal of the kth—DVCC.

➢ Parasitic effects

The parasitic model of DVCC is shown in Fig. 2.3. It is shown that the real

DVCC has parasitic resistors and capacitors at port Z in form of R7JICz, at port Y in form of

Ry//Cy and at port X parasitic are in form of series combination of resistance Rx and capacitor

Cx. Ideally, the DVCC is used at frequencies much lower than the corner frequencies of a; (i=1,

2) and J3 (i=l, 2). For typical applications built around DVCC, the external resistors (R) are

much smaller than the parasitic resistors at the Y and Z terminals of DVCC, i.e. R<<Ry or RZ

and the external resistors are much greater than the parasitic resistor at the X terminal of DVCC,

i.e. Rx<<R. IYi Iz+ _____

dry] Sri = Cyl [ Rvt Z+_C=.1] Rz.

DVCC

VYZ Y2 Z- __ ZY2 = CY21 [ Rra

ThEE!

cx Figure 2.3 Parasitic model of DVCC

14

> Simulation results

The performance of the presented DVCC is verified using the SPICE simulation

program. The MOS transistors are simulated using 0.18µm TSMC process parameters as given

in Table 2.1. The aspect ratios of the transistors used in the simulation are given in Table 2.2.

The supply voltages and biasing voltage are given by VDD = -VS5 = 2.5V and VBB = -1.9V,

respectively.

Table 2.1: 0.18µm TSMC model parameters used for simulation

NMOS:

+ LEVEL=7 VERSION = 3.1 TNOM = 27 TOX = 4,1E-9 XJ = 1E-7 NCH = 2.3549E17 VTEIO = 0.3719233 +Kl = 0.5847845 K2 = 1.987508E-3 K3 = I E-3 K3B = 3.846051 WO = I.00001E-7 NLX = 1.66359E-7 +DVTOW =0 DVTI W = 0 DVT2W = 0 DVTO = 1.616073 DVTI = 0.4422105 DVT2 = 0.0205098 +U0=276.4769418 UA=-1 .287181E-9 UB=2.249816E-18 UC=5.695845E-11 VSAT=1.050018E5 A0=1.8727159 +AGS = 0.4223855 B0= -8.46061 8E-9 B1= -1E-7 KETA= -6.583564E-3 Al = 0 A2 = 0.8925017 RDSW = 105 +PRWG =0.5 PRWB =-0.2 WR = 1 WINT =0 LINT = 1.509138E-8 XL= 0 XW = -1E-8 DWG = -3.993667E-9 +DWB = I.211 844E-8 VOFF = -0.0926198 NFACTOR = 2.4037852 CIT =0 CDSC = 2.4E-4 CDSCD =0 +CDSCB = 0 ETAO = 2.64529E-3 ETAB = -1.I 13687E-5 DSUB = 0.0107822 PCLM = 0.7114924 +PDIBLC1 = 0.1861265 PDIBLC2 = 2.341517E-3 PDIBLCB = -0.1 DROUT= 0.708139 PSCBEI = 8E10 +PSCBE2= 9.I 86022E-10 PVAG = 5.128699E-3 DELTA = 0.01 RSH = 6.5 MOBMOD = I PRT = 0 +UTE = -1.5 KTI = -0.11 KT1L = 0 KT2 = 0.022 UA1= 4.31E-9 UB 1 = -7.61 E-18 UC I= -5.6E-11 AT= 3.3E4 +WL=OWLN=I WW=0WWN=1 WWL=OLL =0LLN=ILW=0LWN=I LWL=0CAPMOD=2 +XPART 0.5 CGDO= 7.9E-10 CGSO = 7.9E-10 CGBO = IE-12 CJ = 9.604799E-4 PB = 0.8 MJ= 0.3814692 +CJSW =2.48995E-10 PBSW= 0.8157576 MJSW = 0.1055989 CJSWG = 3.3E-10 PBSWG = 0.8157576 -4-MJSWG =0.I055989 CF= 0 PVTHO = -4.358982E-4 PRDSW= -5 P1(2= 2.550846E-4 WKETA = 1.466293E-3 +LKETA = -7.702306E-3 PUG = 23.8250665 PUA = 1.058432E-10 PUB= 0 PVSAT = 1.294978E3 +PETAO= 1.003158E-4 PKETA =-3.857329E-3

PMOS:

+ LEVEL=7 VERSION = 3.1 TNOM = 27 TOX = 4.1E-9 XJ = 1E-7 NCH = 4.1589E17 VTHO = -0.3955237 +K1= 0.5694604 K2 = 0.0291529 K3 = 0.0997496 K3B = 13.9442535 WO = 1.003165E-6 NLX = 9.979192E-8 +DVTOW =0 DVTI W =0 DVT2W = 0 DVTO = 0.5457988 DVTI = 0.2640392 DVT2 = 0.1 U0=1 18.0169799 +UA=1 .59191 8E-9 UB=1.129514E-21 UC=-1E-10 VSAT=1.545232E5 A0= 1.6956519 AGS = 0.3816925 +B0=4.590751E-7 B1=1.607941E-6 KETA=0.0142165 A1=0.4254052 A2=0.3391698 RDSW = 168.2822665 +PRWG =0.5 PRWB=-0.5 WR 1 WINT=O LINT=3.01I839E-8 XL= 0 XW=-lE-8 DWG =-4.05222E-8 +DWB = 4.813652E-9 VOFF = -0.099839 NFACTOR =1.8347784 CIT =0 CDSC = 2.4E-4 CDSCD =0 +CDSCB=O ETAO=0.20 L776 ETAB=-0. 1409866 DSUB=1.0474138 PCLM=1.4195047 PDI13LCI=2.422412E-4 +PDIBLC2=0.022477 PDIBLCB=-1 E-3 DROUT=1.228009E-3 PSCBEI=1.245755E10 PSCBE2= 3.598031E-9 +PVAG= 15.04I4628 DELTA= 0.01 RSH=7.5 MOBMOD= 1 PRT=0UTE=-1.5 KTI =-0.11 KT1L=0 +KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UCI=-5.6E-1I AT 3.3E4 WL= 0 WLN=I WW=O WWN=I +W WL= 0 LL = 0 LLN = 1 LW = 0 LWN =1 LWL = 0 CAPMOD = 2 XPART = 0.5 CGDO= 6.34E-10 +CGSO = 6.34E-10 CGBO = 1E-12 CJ = 1.177729E-3 PB = 0.8467926 MJ= 0.4063096 CJSW =2.417696E-10 +PBSW= 0.851762 MJSW = 0.3387253 CJSWG = 4.22E-l0 PBSWG = 0.851762 MJSWG =0.3387253 CF= 0 +PVTHO=1.406461E-3 PRDSW=1 1.5261879 P1(2=1.71 8699E-3 WKETA=0.0353107 LKETA= -1.277611E-3 +PUO=-1.4642384 PUA=-6.79895E-1 I PUB=1E-21 PVSAT=50 PETAO=1.003152E-4 PKETA=-3.103298E-3

15

60mV-

4 0mV

OV Os 20ns o V(1) o V(2) V V(3)

s ue"

40ns 60ns 80ns 100ns

Table 2.2: Aspect ratios used

Transistors W(.m) L(µm)

M 1, M2, M3, M4 0.29 0.18

M5, M6 1.44 0.18

M7, M8, M9, M 10, Mu 3.6 0.18

M12, M13 5.22 0.18

M14,MI5,M16,M17, MIS 16.19 0.18

•.* DC analysis

DC analysis has been done to verify the current and voltage relationships

separately. Fig. 2.4 to Fig. 2.9 shows the DC characteristic of DVCC. Fig. 2.4 shows that when

DC voltage of 60mV is applied at input terminal Yt and DC voltage of 40mV is applied at input

terminal Y2 then DC voltage of 20mV is available at terminal X. In this way, the voltage relation

of equation (2.1) is verified.

Time

Figure 2.4 Verification of input voltages (Vx=VY1-'VY2)

Fig. 2.5 and Fig. 2.6 show the variation in voltage at X terminal (Vx) against the input voltage at

Y, terminal (Vy1) and the input voltage at Y2 terminal (Vy2), respectively. Fig. 2.5 and Fig. 2.6

prove that equation (2.1) is correct. It is obtained by just putting VY2 fixed at OV and by varying

Vy1 from -IV to +IV in the case of Fig. 2.5 and vice versa in the case of Fig. 2.6. Fig. 2.5 and

Fig. 2.6 show good linearity range of voltage at X terminal (Vx) against the input voltages.

16

-1.ov. -1. CV

D V(3)

1. OV

ov

III IIII III .I

X

-0 -5V Dv o.5v 1.Ov

L

VIN1

Figure 2.5 X terminal voltage (Vx) against input voltage (Vy1 )

I I I I I II

IIIIJIIII ----------

-0. 5V Ov 0. 5V 1. CV

VIN2

Figure 2.6 X terminal voltage (Vx) against input voltage (VY2)

Next, Fig. 2.7 and Fig. 2.8 show the responses of the currents at the output terminals Z+ and Z- of

DVCC against input voltages Vy, and VY2, respectively. It can be obtained just by putting VY2 as

constant and by varying Vyi from -IV to 1V in the case of Fig. 2.7 and by putting Vy1 as

constant and by varying Vy2 from -1V to IV in the case of Fig. 2.8. It clearly shows that

current's variations are linear between -TV to IV and after this range current is getting saturated.

1. DV

Dv.

-1.ov.

u V (3)

17

-4 0Ou -LOV

0 I (Vz+)

4 OOuA

OA

12:- 1

-0. 5V 0V I(Vz-

VIN1

0. 5V 1.0v

Figure 2.7 Output currents (I + and la-) against input voltage (Vyl)

I I

Iz+

* - ------------ -0.5v 011 0.511 1.011

G I(Vz-) VIN2

Figure 2.8 Output currents (Jz+ and Iz-) against input voltage (VY2)

Fig. 2.9 shows the variations in output currents at terminals Z+ and Z- with respect to the current

at X terminal. Fig. 2.9 shows good linear range of output currents. Fig. 2.9 also verifies the

current relationships of equation (2.1).

4 OOuA

CA

-400uA-

I(Vz+)

18

i

= i s

=

S

1

I

t

=

1 ~

1 =

OA 100uA 200uA

I(R1)

Figure 2.9 Output currents (Iz+ and Iz-) against input current (Ix)

❖ AC analysis

AC analysis is also done by applying AC input signals at the input terminals of

DVCC. AC responses are shown in from Fig. 2.10 to Fig. 2.14. Fig. 2.10 verifies the voltage

relationship of equation (2.1) in frequency domain and Fig. 2.11 verifies the current relationships

of equation (2.1) in frequency domain. These responses also show the range of frequency

suitable for operation. Fig. 2.10 and Fig. 2.11 clearly indicate that voltages and currents

t ..... ----------- 1

Vyl ------------------------

.

------------; -----------

1

----------'

1

' ------------ ----------- 1

1

----------- ------------ .

+

VY2 ---- -'------------

--- r

1

----------- ------------------------ 1 ------------------------ ~ - - -------,---- ----

Vx ----------

-----------

------------;----------- 1

-----------=------------ ~ 1 1

----- - ----;----------__ 1

.--------- -----------

----------_ •-----------+------------------------

1

J------------

~

--------_ _J________'--_.

1. drniz 100IIHz 10GHz

Frequency

Figure 2.10 Voltages in frequency domain

400uA-

0A•

-400uA -200uA -100uA

D I(Vz+) o I(Vz-}

relationships are accurate up to 250MHz. 2.011

1.011

OV 1.0KHz 10KHz

❑ Vt1) o V(2) v V(3)

LPJ

20'

G a i o- n

i n

-20- ci B

-40-11 1

10KHz o DB(V(3)/(V(1)-V(2)))

1.0MHz 100MHz 10GHz

100•

1.0KHz 10KHz 1.0MHz 100MHz 10GHz 0 I (R1) * I (Vz+) V I (Vz-)

Frequency

Figure 2.11 Currents in frequency domain

Fig. 2.12 shows the voltage gain in dB. Fig. 2.12 also shows that the bandwidth of DVCC is

quiet good and up to 250MHZ.

Frequency

Figure 2.12 Voltage gain [VI (V1-Vy2)] in dB

Fig. 2.13 and Fig. 2.14 show the positive current gain and negative current gain in dB,

respectively. These responses show the good bandwidth range of DVCC.

20

20

G a i 10 n

d

1

1.0KHz 10KHz 1.0MHz 100NHz 10GHz C DB(I(Vz+)/I(R1))

Frequency

Figure 2.13 Current gain (Iz+/ Ix) in dB

20

G a i n

1 n

-20 d B

-401 -1

1.0KHz 10KHz 0 DB(I(Vz-)/1(R1))

1.0MHz 100MHz 10GHz

Frequency

Figure 2.14 Current gain (Iz-/ Ix) in dB

•. Transient analysis PSPICE simulation is next carried out for sinusoidal inputs. These results also

give a good agreement between expected and simulated results. These results also verify the

basic equations for DVCC in time domain and are shown in Fig. 2.15 and Fig. 2.16. The total

I. harmonic distortion (THD) is found to be less than 0.88%.

21

-20

20fl -

Y1=

.rri.r....•.xi. .........:....--~-- .r:. _~._-~ - _ _ ...x...._.....xu....-.«. _ -- _

vY2

100ns 150ns 200ns

I Time

Figure 2.15 Input/output voltages at 10MHz

1.Ov-

c Y -

-1.OV Os 5Ons o V(1) o V(2) v V(3)

Os 50ns 100ns 150ns ❑ I(R1) ¢ I(Vz+) v I(Vz-)

Time

Figure 2.16 Input/output currents at 10MHz

2.2 Differential Difference Current Conveyor (DDCC) DDCC was proposed in 1996 by Chiu et al. [14]. DDCC enjoys the advantages of CC-II

and differential difference amplifier (DDA) such as larger signal bandwidth, wider dynamic

range, greater linearity, low power consumption, simple circuitry and high input impedance.

➢ CMOS implementation of DDCC The DDCC is a six-part building block which is defined by the following matrix

equation:

22

VX 0 1 —1 1 0 0 J.

'Ti 0 0 0 0 0 0 V 1 IY2 0 b 0 0 0 0 Vrz 1y3 0 0 0 0 0

(2.3) 0 VY3

Iz+ 1 0 0 0 0 0 VV* Iz_ —1 0 0 0 0 0 VZ_

where,

VYi = Voltage at Yi terminal IY2 = Current at Y2 terminal

VYZ = Voltage at Y2 terminal IY3 = Current at Y3 terminal

VY3 = Voltage at Y3 terminal Iz+ = Current at Z+ terminal

VX = Voltage at X terminal IZ_ = Current at Z. terminal

Iy = Current at Yl terminal Ix = Current at X terminal

The difference of the Yi and Y2 terminal voltages in addition with the voltage at Y3 terminal is

conveyed to the X terminal; the current input at the X terminal is conveyed to the Z+ terminal

with the same polarity and to the Z- terminal with inverse polarity. In a DDCC, terminals Y1, Y2

and Y3 exhibit infinite input impedance. Thus, no current flows in terminals Y1 , Y2 and Y3. The

terminal X exhibits zero input impedance. The terminals Z+ and Z- have infinite output

impedance.

The symbol of the DDCC is shown in Fig. 2.17.

I-1

i Yt y1 IZ+ IY2 I Z+ ^

VY2 ' y2 DDCC

Figure 2.17 Symbol of DDCC 5

23

1

11

Y2

V

The CMOS implementation of the DDCC [14] is shown in Fig. 2.18. -tT

Vss

Figure 2.18 CMOS implementation of DDCC [14]

All transistors operate in saturation region and the sources are connected to

bulk/substrate. Transistors M5 and M6, work as a current mirror which are set to drive two

differential amplifiers consisting of transistors M1, M2, M3 and M4. Transistors M7 and M14

provide the necessary feedback action to make the voltage Vx independent of current drawn

from the terminal X. The current through terminal X is conveyed to the Z+ terminal with the help

of transistors M7, M8, M14 and M15. By using extra current mirror the current is conveyed in an

inverted manner to the Z- terminal.

Non-ideal analysis

Taking the non-idealities of the DDCC into account, the relationship of the terminal

voltages and currents of the DDCC can be rewritten as

24

VX 0 )9ki — )'k2 Pk3 0 0 -[x In 0 0 0 0 0 0 Vri 'V2 0 o o o o 0 VY2 IY3 - 0 0 0 0 0 0 VY3

(2.4)

1z+ aki 0 0 0 0 0 v IZ- -a 0 0 0 0 0 yZ-

where, Jikl(s), 13k2(s) and &3(s) represent the frequency transfers of the internal voltage followers

and akl(s), ak2(s) represent the frequency transfers of the internal current followers of the kth-

DDCC, respectively. If DDCC is working at frequencies much less than the corner frequencies

of flkr(s),13kz(S), 603(s), akJ(s) and ak2(s), namely, then /kl(s) =fikr=I -E,! where, Ems► (Ic wI <<1) denotes the voltage tracking error from the Y1 terminal to the X terminal of the kth—DDCC;

= fik2=1 where, Fh2 (IEk,21 <<1) denotes the voltage tracking error from the Y2 terminal

to the X terminal of the kth—DDCC; Qkj(s) = f k3= I -ck,3 where, Ekv3 (Is3I <<1) denotes the voltage

tracking error from the Y3 terminal to the X terminal of the kth—DDCC; ak,(s) = ak; =1- j

where, sk,f (Iski4 <<I) denotes the current tracking error from the X terminal to the Z{ terminal

and ak2(s) ak2 =I-Eki2 where, sk j2 (1c,42I <<1) denotes the current tracking error from the X

terminal to the Z- terminal of the kth—DDCC.

Parasitic effects

The parasitic model of DDCC is shown in Fig. 2.19. It is shown that the real

DDCC has parasitic resistors and capacitors at port Z in form of Rz//CZ, at port Y in form of

Ry/ICy and at port X parasitic are in form of series combination of resistance Rx and capacitor

C. Ideally, the DDCC is used at frequencies much lower than the corner frequencies of a1 (i=l,

2) and f (i=1, 2, 3). For typical applications built around DDCC, the external resistors (R) are

much smaller than the parasitic resistors at the Y and Z terminals of DDCC, i.e. R<<Ry or Rz

and the external resistors are much greater than the parasitic resistor at the X terminal of DDCC,

i.e. RX<<R.

25

`Y1 Cyi I I RYl IY2

Y2

Z12 .. CY2IIRy2 IY3

Vy3

zy3 - cY3 I I RY3

1

2 DDCC

x

Rx

IZ+

Z =Cz+I! R .~

u- z- '

ZC I Rz

Figure 2.19 Parasitic model of DDCC

Simulation results

The performance of the presented DDCC is verified using the SPICE simulation

program. The MOS transistors are simulated using 0.18µm TSMC process parameters and are

given in Table 2.3. The aspect ratios of the transistors used in the simulation are given in Table

2.4. The supply voltages and biasing voltage are given by VDD = -V5s = 2.5V and VBB = -1.6V,

respectively.

Table 2.3: 0.18im TSMC model parameters used for simulation

ui1 + LEVEL=7 VERSION = 3.1 TNOM = 27 TOX = 4.1 E-9 XJ = IE-7 NCH = 2.3549E17 VTHO = 0.3719233 +K1 = 0.5847845 K2 = 1.987508E-3 K3 = IE-3 K3B = 3.846051 WO = 1.00001E-7 NLX = 1.66359E-7 +DVTOW = 0 DVTIW = 0 DVT2W = 0 DVTO =1.616073 DVT1 = 0.4422105 DVT2 = 0.0205098 +1JO=276.4769418 UA=-1.287181E-9 UB=2.249816E-18 UC=5.695845E-1 I VSAT=1.050018E5 A0=1.8727159 +AGS = 0.4223855 B0= -8.460618E-9 Bl= -1E-7 KETA= -6.583564E-3 Al = 0 A2 = 0.8925017 RDSW = 105 +PRWG =0.5 PRWB =-0.2 WR = I WINT =0 LINT= 1,509138E-8 XL= 0 XW = -1E-8 DWG = -3.993667E-9 +DWB = 1,211844E-8 VOFF = -0.0926198 NFACTOR = 2.4037852 CIT =0 CDSC = 2.4E-4 CDSCD =0 +CDSCB = 0 ETAO = 2,64529E-3 ETAB = -1.1 13687E-5 DSUB = 0.0107822 PCLM = 0.7114924 +PDIBLCI = 0.1861265 PDIBLC2 = 2.341517E-3 PDIBLCB = -0.1 DROUT = 0.708139 PSCBEI = 8E1 0 +PSCBE2= 9.186022E-10 PVAG =5. 128699E-3 DELTA = 0.01 RSH = 6.5 MOBMOD = I PRT =0 +CITE = -1.5 KT I = -0.11 KT 1 L = 0 KT2 = 0.022 UA1= 4.31 E-9 LIB 1 =-7.61E-18 UC 1= -5.6E-11 AT= 3.3E4 +WL= 0 WLN = 1 WW= 0 WWN = 1 WWL= 0 LL = 0 LLN = 1 LW = 0 LWN = 1 LWL = 0 CAPMOD = 2 +XPART = 0.5 CGDO= 7.9E-10 CGSO = 7.9E-10 CGBO = IE-12 CS = 9.604799E-4 PB = 0.8 MJ= 0.3814692 ±CJSW =2.48995E-I0 PBSW= 0.8157576 MJSW = 0.1055989 CJSWG = 3.3E-10 PBSWG = 0.8157576 +MJSWG =0.1055989 CF= 0 PVTHO = -4.358982E-4 PRDSW= -5 P1(2= 2.550846E-4 WKETA = 1.466293E-3 +LKETA = -7.702306E-3 PUO = 23.8250665 PUA = 1.058432E-10 PUB= 0 PVSAT = 1.294978E3 +PETAO= 1,003158E-4 PKETA =-3.857329E-3

M

PMOS:

+ LEVEL=7 VERSION = 3.1 TNOM = 27 TOX = 4.1E-9 XI = I E-7 NCR = 4.1589E17 VTHO = -0.3955237 +1(1= 0.5694604 K2 0.0291529 1(3 = 0.0997496 K3B = 13.9442535 WO = 1.003165E-6 NLX = 9.979192E-8 +DVTOW = 0 DVTI W =0 DVT2W =0 DVTO = 0.5457988 DVT1 = 0.2640392 DVT2 = 0.1 U0=118.0169799 +UA=I.591918E-9 UB=1.1295I4E-21 UC=-IE-10 VSAT=1.545232E5 A0= 1.6956519 AGS = 0.3816925 +B0=4.590751E-7 B1=1.607941E-6 KETA=0.0142165 A1-0.4254052 A2=0.3391698 RDSW =168.2822665 +PIRWG =0.5 PRWB=-0.5 WR=1 WINT=O LINT-3.01 ] 839E-8 XL= 0 XW=-1E-8 DWG -4.05222E-8 +DWB = 4.813652E-9 VOFF = -0.099839 NFACTOR = 1.8347784 CIT = 0 CDSC = 2.4E-4 CDSCD =0 +CDSCB=O ETA0-0.201776 ETAB=-0.1409866 DSUB=1.0474138 PCLM=1.4195047 PDIBLC1=2.4224121 4 +PDIBLC2=0.022477 PDIBLCB=-1E-3 DROUT=1.228009E-3 PSCBE1=1.245755E10 PSCBE2= 3.598031E-9 +PVAG = 15.0414628 DELTA = 0.01 RSH = 7.5 MOBMOD = I PRT = 0 UTE = -1.5 KT1 = -0.11 KTI L = 0 +KT2=0.022 UAI=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT= 3.3E4 WL= 0 WLN=l WW=O WWN=1 +WWL=0LL=0LLN=1LW=0LWN=1LWL=0CAPMOD=2XPART=0.5CGDO=6.341;-10 +CGSO = 6.34E-10 CGBO = 1E-12 CJ = 1.177729E-3 PB = 0.8467926 MJ= 0.4063096 CJSW =2.4176961:-10 +PBSW= 0.851762 MJSW = 0.3387253 CJSWG = 4.22E- 10 PBSWG = 0.851762 MJSWG =0.3387253 CF= 0 +PVTHO=1.406461E-3 PRDSW=1 1.5261879 PK2=1.718699E-3 WKETA=0.0353107 LKETA= -1.277611E-3 +PUO=- 1.4642384 PUA=6.79895E-11 PUI3=1E-21 PVSAT=50 PETAO=1 .0031 52E-4 PKETA=-3.103298E-3

Table 2.4: Aspect ratios used

Transistors W(µm) L(µm)

M1, M2, M3, M4 0.29 0.18

M5, M6 1.44 0.18

M7, M8, M9, M10, M11 3.6 0.18

M12, M13 5.22 0.18

M14,M]5,M16,M17, M18 16.19 0.18

•«• DC analysis


separately. Fig. 2.20 to Fig. 2.24 shows the DC characteristic of DDCC. Fig. 2.20 shows that

when DC voltage of 80mV is applied at input terminal Y1, DC voltage of 40mV is applied at

input terminal Y2 and DC voltage of 20mV is applied at input terminal Y3 then DC voltage of

60mV is available at terminal X. In this way, the voltage relation of equation (2.3) is verified.

Fig. 2.21, Fig. 2.22 and Fig. 2.23 show the variation in voltage at X terminal (Vx) against

the input voltage at Y1 terminal (Vyi), the input voltage at Y2 terminal (VY2) and the input

voltage at Y3 terminal (VY3), respectively.

27

-1.Ov. -1.Ov

ri V(4)

1-Ov.

0J

-0. 5V Ov 0. 5v 1.OV

BOrnV

4 OmV

V1

Y2 - - - - - __ -

- -

- - - - --

Y3 - - - - -

Os 20ns 40ns 60ns sons 100ns o V(1) o V(2) v V(3) A V(4)

Time

Figure 2.20 Verification of input voltages (Vx Vy1-Vy2~Vy3)

Fig. 2.21, Fig. 2.22 and Fig. 2.23 prove that equation (2.3) is correct. It is obtained by just

putting Vy2 and VY3 fixed at OV and by varying Vy r from - IV to +1V in the case of Fig. 2.21, by

just fixing Vy and V 3 at OV and by varying VY2 from -IV to +IV in the case of Fig. 2.22 and in

Fig. 2.23 by just putting Vy1 and Vy2 fixed at OV and by varying Vy3 from -IV to +IV. Fig. 2.21,

Fig. 2.22 and Fig. 2.23 show good linearity range of voltage at X terminal (Vx) against the input

voltages.

VIN1

Figure 2.21 X terminal voltage (Vx) against input voltage (Vyi)

28

Ov-

IIIIIIIIIIIIIIIcI —1_ov— —1.0V —0.5V OV 0.5V 1.OV

o V(4) v1N2

- Figure 2.22 X terminal voltage (Vx) against input voltage (Vy2)

1.

OF —1.OV —0.5V OV 0.5v 1.OV

V(4) VIN3

Figure 2.23 X terminal voltage (Vx) against input voltage (VY3)

Fig. 2.24 shows the variations in output currents at terminals Z, and Z- with respect to the

current at X terminal. Fig. 2.24 shows good linear range of output currents. Fig. 2.24 also verifies

the current relationships of equation (2.3).

29

f 1

~ ~ Y

IIIII2III±IIII1I III

OA 100uA 200uA

I(R1)

Figure 2.24 Output currents (Iz+ and Iz-) against input current (Ix)

❖ AC analysis

AC analysis is also done by applying AC input signals at the input terminals of

DDCC. AC responses are shown in Fig. 2.25 and Fig. 2.26. Fig. 2.25 verifies the voltage

relationship of equation (2.3) in frequency domain and Fig. 226 verifies the current relationships

of equation (2.3) in frequency domain. These responses also show the range of frequency

suitable for operation. Fig. 2.25 and Fig. 2.26 clearly indicate that voltages and currents

relationship is accurate up to 250MHz.

2. 0V

1.CV•

OV 1.0KHz 10KHz 1.0MHz 100MHz 10GHz

o V(1) 4 V(2) v V(3) a V(4) Frequency


200uA-

OA

-200uA -200uA -100uA o Itvz-) a t(Vz+)

µ VYl

: . ____ ...

VX

30

Iz-

Ix

..

100MHz 10GHz

Frequency

Figure 2.26 Currents in frequency domain

Fig. 2.27 shows the voltage gain in dB. Fig. 2.27 also shows that the bandwidth of DDCC is up

to 250Mliz.

50OUA

250uA

OA 1.0KHz 10KHz 1.0MHz

En 1(R1) c' I(Vz+) V IVz-)

G a I n

-2 i Ti

d B

-40+- 1.0KHz 10KHz 1.0MHz

D DB(V(4)/(V(1)-V(2)+V(3) )) Frequency

100MHz 10GHz

Figure 2.27 Voltage gain [V/ (Vy i-Vy2+Vy3)1 in dB


respectively. These responses show the good bandwidth range of DDCC.

31

F4I]

G 10 a i n

0 i n

d -10 B

-201 1

1.0KHz 10KHz ❑ DB(I(Vz+)/I(R1))

1.0MHz

Frequency

100MHz 10GHz

Figure 2.28 Current gain (Iz~/ Ix) in dB

T-

20

G 10 a i n

0 i n

d _10 B

-20 1.OKHz 10KHz

o DB(I(Vz-)/I(RI)) 1.0MHz 100MHz 10GHz

Frequency

Figure 2.29 Current gain (Iz-/ Ix) in dB

-:* Transient analysis

PSPICE simulation is also carried out for sinusoidal inputs. These results also

give a good agreement between expected and simulated results. These results also verify the 4

32

-LOVr- -

Os 5Ons o V(1) V(2) v V(3) & V(4)

1. Ov•

ov. MOSOMEMMMIA

lOOns 150ns 200ns

basic equations for DDCC in time domain and are shown in Fig. 2.30 and Fig. 2.31. The total

harmonic distortion (THD) is found to be less than 0.96%.

lOOuA

DA

Time

Figure 2.30 Input/output voltages at 10MHz

- nil. mill. 200ns 250ns 300ns

Time

Figure 2.31 Input/output currents at 10MHz

-lOOuA-, I

Os 50ns lOOns o £(R1) o I(Vz±) V I(Vz-)

33

2.3 Voltage Controlled DDCC (VC-DDCC)

The Voltage Controlled Differential Difference Current Conveyor (VC-DDCC) is the

tunable version of DDCC (Fig. 2.18). The parasitic resistance of X terminal of DDCC is actually

dependent on the biasing voltage VBB and shows moderate variation with it. Thus, the X terminal

resistance of DDCC is controlled by the external voltage V$a and hence DDCC is re-named as

VC-DDCC. Keeping this in consideration, the ports Y to X relationship is modified as:

VX = (Vyr-Vy2+ Vy3) + IxRx It may be noted that the possibility of tuning Rx in DVCC was given in [15].

➢ Ports relationship of VC-DDCC

The VC-DDCC is defined by the following matrix equation:

VX RX 1 —1 1 0 0 IX In 0 0 0 0 0 0 Vrt IY2 0 0 0 0 0 0 VY2

1Y3 0 .0 0 0 0 0 VY3

Iz+ 1 0 0 0 0 0 Vz+ IZ_ -1 0 0 0 0 0 VZ _

(2.5)

where,

Vy1 = Voltage at Y1 terminal

VY2 = Voltage at Y2 terminal

Vy3 = Voltage at Y3 terminal

Vx = Voltage at X terminal

Iyl = Current at Y1 terminal

lye = Current at Y2 terminal

IY3 = Current at Y3 terminal

IZ+ = Current at Z+ terminal

I. = Current at Z_ terminal

Ix = Current at X terminal

R>=Parasitic resistance at terminal X

The difference of the Y1 and Y2 terminal voltages in addition with the voltage at Y3 terminal and

voltage across parasitic resistance (IxRx) is conveyed to the X terminal. Similar to the DDCC,

The current input at the X terminal is conveyed to the Z+ terminal with the same polarity and to

the Z- terminal with inverse polarity. Here, terminals Y1, Y2 and Y3 exhibit infinite input

impedance. Thus, no current flows in terminals Y1, Y2 and Y3. The terminal X exhibits zero

input impedance. The terminals Z+ and Z- have infinite output impedance.

34 THESIS

The symbol of VC-DDCC is shown in Fig. 2.32.

'I'1

Vo Y1 Iz+ 'Y2 Z+ - Vz+

Y2 Y2 DDCC Iz-

Iy3 Z- Vz- T Y3 Y3

x

Rx Ix

Figure 2.32 Symbol of VC-DDCC

Simulation results

The VC-DDCC was simulated using the 0.18µm CMOS parameters listed in Table 2.3

and device dimensions as listed in Table 2.4. The supply voltage used was ±2.5V. The Rx variation with

the bias voltage VBB was studied. The result is shown in Fig. 2.33, which suggests a moderate variation

if Rx with V. All other results are same as conventional DDCC as discussed and shown in previous

action 2.2. Zoo

1so

160

r~ 120

110

ao

6o

ao

20

0

1 I J 1.2 1.3 l.4 1.5 1.6 1.7 1_$

-VBII (V)

Figure 2.33 Rx variation with bias voltage VBB

35

2.4 Dual X Current Conveyor-II (DXCC-II)

The DXCC-II is a combination of regular CC-II and ICC-II. Similar to other current-

mode active devices, the DXCC-II has advantages such as higher usable gain, more reduced

voltage excursion at its sensitive nodes, greater linearity, less power dissipation, wider

bandwidth, better accuracy and larger dynamic range over its voltage-mode counterpart [l6].

➢ CMO,S implementation of DXCC-II

The DXCC-II is a five-port building block which is defined by the following

matrix equation:

VX+ 0 0 1 0 0 b+

VX- 0 0 -1 0 0 iX-

Ir = 0 0 0 0 0 Vv

IZ+ 1 0 0 0 0Vz+

Iz- 0 1 0 0 0 Vz -

where,

Vy = Voltage at Y terminal

Vx, = Voltage at X+ terminal

Vx_ = Voltage at X- terminal

Iy = Current at Y terminal

Iz+ = Current at Z+ terminal

IZ_ = Current at Z_ terminal

Ix+ = Current at X+ terminal

Ix. = Current at X- terminal

The symbol of DXCC-II is shown in Fig. 2.34. Fig. 2.34 shows that the DXCC-II has

several terminals as follows:

• One high input impedances voltage input terminals: Y

• Two low impedance current input terminal: X+, X.

• Two high impedance current output terminals: Z+, Z_

(2.6)

36

V88

I~ \IyO Y D:CC-II

IZ+ z+ 4" Vz+

I2— z— — z-

Figure 2.34 Symbol of DXCC-II

The CMOS implementation of DXCC-II is shown in Fig. 2.35. VDD

VSS

Figure 2.35 CMOS implementation of DXCC-11 [161

The differential pairs M1—M2 and Mi—Mg, together with transistors M11 and M13 construct active

feedback loops which provide low input impedance at terminals X+ and X-, respectively. Since

the differential pairs are biased with the drain currents of the PMOS transistors M17 and M18

(controlled with the bias voltage VBB), one can increase the bias currents (by decreasing VBB) to

improve the linearity of the DXCC-II. However, this results in more power consumption. The

37

transistor M3 together with M7, M8 and M13 are involved in a voltage inverting mechanism which

inverts the voltage of terminal Y to terminal X-. Further, the transistors M12 and M14 are

employed to transfer the X+ and X- terminal currents to Z+ and Z- terminals, respectively.

➢ Non-ideal analysis

Taking the non-idealities of the DXCC-II into account, the relationship of the

terminal voltages and currents of the DXCC-II can be rewritten as

Vx + r 0 0 Pki 0 0 ix+

Vx - 0 0 —,6k2 0 0 ix -

JY 1z +

1=1 0 0 0 0 0

aka 0 0 0 0

Vr

Vz+

I (2.7)

Iz- 0 akz 0 0 0 yZ -

where, /3k1(S) and 13k2(s) represent the frequency transfers of the internal voltage followers and

akf(s), ak2(S) represent the frequency transfers of the internal current followers of the kth-DXCC-

II, respectively. If DXCC-II is working at frequencies much less than the corner frequencies of

/ikf(s), (3k2(s), akl(s) and ak2(s), namely, then /3k1(s) = /3ki = i -c _, j where, sk„j (19k,11 <<1) denotes the

voltage tracking error from the Y terminal to the X+ terminal of the kth—DXCC-II; f3,-2(s) _

fl =1-s,z where, Ejcv2 (Isk2I <<1) denotes the voltage tracking error from the Y terminal to the X-

terminal of the kth—DXCC-II; ak,(s) = akt =1-ck, where, sA,•1 (1c ut <<I) denotes the current

tracking error from the X+ terminal to the Z+ terminal and a*2(s) = ak2 =I-ski2 where, 5k2 (IEA2l

«l) denotes the current tracking error from the X- terminal to the Z- terminal of the kth-

DXCC-II.

A Parasitic effects

The parasitic model of DXCC-1I is shown in Fig. 2.36. It is shown that the real

DXCC-1I has parasitic resistors and capacitors at port Z in form of Ri/JCz, at port Y in form of

Ryf/Cy and at port X parasitic are in form of series combination of resistance Rx and capacitor

Cx. Ideally, the DXCC-II is used at frequencies much lower than the corner frequencies of a,

(i=1, 2) and fl (i=1, 2). For typical applications built around DXCC-Il, the external resistors (R)

are much smaller than the parasitic resistors at the Y and Z terminals of DXCC-II, i.e. R<<R or

Rz and the external resistors are much greater than the parasitic resistors at the X terminals of

DXCC-II, i.e. Rx<<R.

38

Iz+ z+ Vz+

Y ____~ DXCC-II

fir = Cy ] R _____

X+ x- Rz-

Rx+ Ix+ Ix- Rx-

cx+ Cx_ Figure 2.36 Parasitic model of DXCC-TI

> Simulation results

The performance of the presented DXCC-II is verified using the SPICE

simulation program. The MOS transistors are simulated using 0.18}im TSMC process parameters

and are given in Table 2.5. The dimensions of the transistors used in the simulation are given in

Table 2.6. The supply voltages and biasing voltage are given by VDD = -Vs5 = 2.5V and VBB = -

I.6V, respectively and Cc = 0.06pF.

Table 2.5: 0.18pm TSMC model parameters used for simulation

NMOS:

+ LEVEL=7 VERSION = 3.1 TNOM = 27 TOX = 4.1E-9 XJ = 1E-7 NCH = 2.3549E17 VTHO = 0.3719233 +K1 = 0.5847845 K2 = 1.987508E-3 K3 = IE-3 K3B = 3.846051 WO = 1.00001E-7 NLX = 1.66359E-7 +DVTOW = 0 DVTI W = 0 DVT2W = 0 DVTO = 1.616073 DVTI = 0.4422105 DVT2 = 0.0205098 +U0=276.4769418 UA='-1.287181E-9 UB=2.249816E-18 UC 5.695845E-1I VSAT=1.050018E5 A0=1.8727159 +AGS = 0.4223855 B0= -8.460618E-9 B1= -IE-7 KETA= -6.583564E-3 Al = 0 A2 = 0.8925017 RDSW = 105 +PRWG =0.5 PRWB =-0.2 WR = 1 WINT = 0 LINT = 1.509138E-8 XL= 0 XW = -1E-S DWG = -3.993667E-9 +DWB = 1.211844E-8 VOFF = -0.0926198 NFACTOR = 2.4037852 CIT =0 CDSC = 2.4E-4 CDSCD =0 +CDSCB = 0 ETAO = 2.64529E-3 ETAB = -1.113687E-5 DSUB = 0.0107822 PCLM = 0.7114924 +PDIBLCI = 0.1861265 PDIBLC2 = 2.341517E-3 PDIBLCB = -0.1 DROUT = 0.708139 PSCBEI = SE10 +PSCBE2= 9.186022E-10 PVAG =5.1 28699E-3 DELTA = 0.01 RSH = 6.5 MOBMOD = I PRT = 0 +UTE=-1.5 KTl =-0.11 KTIL=0 KT2=0.022UA1=4.31E-9UBI =-7.61E-18 UC1=-5.6E-11 AT=3.3E4 +WL-0WLN=I WW= 0 WWN = I WWL= 0 LL 0 LLN = I LW=0LWN=I LWL =0 CAPMOD =2 +XPART = 0.5 CGDO= 7.9E-10 CGSO = 7.9E-10 CGBO = I E-12 CJ = 9.604799E-4 PB = 0.8 MJ= 0.3814692 +CJSW =2.48995E-10 PBSW= 0-8157576 MJSW = 0.1055989 CJSWG = 3.3E-10 PBSWG = 0.8157576 +MJSWG =0.1055989 CF= 0 PVTHO = -4.358982E-4 PRDSW= -5 P1(2= 2.550846E-4 WKETA = 1.466293E-3 +LKETA = -7.702306E-3 PUO = 23.8250665 PUA = 1.058432E-10 PUB= 0 PVSAT =1.294978E3 +PETAO= I.003158E-4 PKETA =-3.857329E-3

39

+ LEVEL=7 VERSION =3.1 TNOM = 27 TOX = 4.1E-9 XJ = 1E-7 NCH = 4.1589E17 VTHO = -0.3955237 +K1= 0.5694604 K2 = 0.0291529 K3 = 0.0997496 K3B = 13.9442535 WO = 1.003165E-6 NLX = 9.979192E-8 +DVTOW =0 DVT1 W = 0 DVT2W = 0 DVTO = 0.5457988 DVT] = 0.2640392 DVT2 = 0.1 U0=118.0169799 +UA=1.591918E-9 UB=1.129514E-21 UC=-1E-10 VSAT=1.545232E5 A0=1.6956519 AGS = 0.3816925 +B0=4.590751E-7 B1=1.607941E-6 KETA=0.0142165 A1=0.4254052 A2= 0.3391698 RDSW = 168.2822665 +PRWG =0.5 PRWB=-0.5 WR=1 WINT=0 LINT=3.011839E-8 XL= 0 XW=-1E-8 DWG =4.05222E-8 +DWB = 4.813652E-9 VOFF = -0.099839 NFACTOR = 1.8347784 CIT =0 CDSC = 2.4E-4 CDSCD =0 +CDSCB=O 11TA0=0.2017761~TAB=-0.I409866 DSUB=1.0474138 PCLM=1.4195047 PDIBLCI=2.422412E-4 +PDIBLC2=0.022477 PDIBLCB=-lE-3 DRDUT=1.228009E-3 PSCBEI=1.245755E10 PSCBE2= 3.598031E-9 +PVAG = 15.0414628 DELTA = 0.01 RS H = 7.5 MOBMOD = I PRT= 0 UTE = -1.5 KTI = -0.11 KT1 L = 0 +KT2=0.022 UA1=4.31E-9 t1B1=-7.61E-18 UCI=-5.6E-11 AT= 3.3E4 WL= 0 WLN=1 WW=0 WWN=1 +W WL= 0 LL = 0 LLN = I LW = 0 LWN =1 LWL =0 CAPMOD = 2 XPART = 0.5 CGDO= 6.34E-10 +CGSO = 6.34E-10 CGBO = IE-I2 CJ =1.177729E-3 PB = 0.8467926 MJ= 0.4063096 CJSW =2.417696E-IO +PBSW= 0.851762 MJSW = 0.3387253 CJSWG = 4.22E-10 PBSWG = 0.851762 MJSWG =0.3387253 CF= 0 +PVTHO=1.406461 E-3 PRDS W=11.5261879 PK2=1.718699E-3 WKETA=O.0353107 LKETA= -1.27761 1E-3 +PUO=-1.4642384 PUA=-6.79895E-11 PUB=1E-21 PVSAT=50 PETA0=1.003152E-4 PKETA=-3.103298E-3

Table 2.6: Dimensions of MOS transistors used for simulation

Transistors W(um) I L(µm)

M1, M2, M4, M5, MI5-20 1.44/ 0.18

M3, M6-1Q 2.88/ 0.18

M11-14 11.51/0J8

4 DC analysis


separately. Fig. 2.37 to Fig. 2.40 shows the DC characteristic of DXCC-1I. Fig. 2.37 shows that

when DC voltage of 20mV is applied at input terminal Y then DC voltage of 20mV is available

at terminal Xt and DC voltage of -2OmV is available at terminal X-. In this way, the relationship

of voltages of equation (2.6) is verified.

Fig. 2.38 shows the variation in voltages at X+ terminal (Vx+) and X- terminal (Vx-)

against the input voltage at Y terminal (Vy). Fig. 2.38 proves that equation (2.6) is correct. It is

obtained by varying Vy from -100mV to +100mV and is shown in Fig. 2.38. Fig. 2.38 shows

linearity range of voltages at X+ terminal (Vx+) and X- terminal (Vx-) against the input voltage

(VY)•

40

-200mV -10 OmV

D V(2) o V(3)

2 0OznV

Ov.

-5OmV OV 5OinV lOOmV

4OmV-

0v.

IV - - - .-...

- ------ -

X- . - - I-.- - - - - - - -

IOUs 15us 20us

SWIT

Figure 2.37 Verification of input voltages (Vx++Vy and VX+=-Vy)

-4 Cmv Os Sus D V(1) o V(2) v V(3)

4

URN

Figure 2.38 X-- and X- terminal voltages (Vx, and Vx-) against input voltage Vy

Fig. 2.39 and Fig. 2.40 show the variations in output current at terminal Z. (Iz+) and output

current at terminal Z- (Iz-) with respect to the current at X terminal (lx), respectively . These

responses of output currents show good linearity. Fig. 2.39 and Fig. 2.40 also verify the current

relationships of equation (2.6).

41

r•

q,

2.

.—:-._..-L••---•-••4...-4—... ......-I.......__a---••-~... [.. ~.!— b._......l... --.. »»

-50uA

OA

50uA 100uA

I (Rl)

Figure 2.39 Output current at Z+ terminal (1z,+) against input current at X+ terminal (IX +)

I 1 I I I I I Y I I

1 1 I I I I I I 1 1 I

---- 1----J---_ - 1----- ----1--_ -J---- J---- _ ----L---- i__--J------ _---L--__ ---_ J-_-• 1 1 1 1 1 1 1 1 1 Y 1 1

1

1 1 1 1

-- " 1 ! ----~----

I -r.... I 1 ----r---.....~

1 -----

1 .. "r'---

1 1 ----~-----

I 1 ----r----r---- ------

1

/

1 J I • 1 1 1 _ -- 1 - 1 1 1 1 1 1 I 1 I 1 1 Y 1

1 1 1 1 1 1 1 I 1 1 1 1

_ --_1-_•.J---- --_ -----L____J--_..J----------L'___J__-_J___- 1 1 I I I 1 I 1 1

-_-_~- 1

__-1---- 1 -----

1 1 ----7---. _-_1-

I _____--

. __r-

1 1 ___ 7 _--_'---__

1 1

___- -----___ -1---_

1 1 1 1 1 1 J 1 1

._-_1-- _ -J---__1 ----_ ---- --_J__-- 1

J----- --__L__-- 1---_J____ --------_- --_-J-----

1 1 t

1 1 1 I 1 4 I I 1 1 1 1 I 1 1

1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 I 1 1 1 1 1 1 1 1

1

1

I I I

1 1 1

-4OuA OA 40uA 80uA

;(I) Figure 2.40 Output current at Z- terminal (Iz-) against input current at X- terminal (Ix-)

',e AC analysis AC analysis is also done by applying AC input signal at the input terminal of

DXCC-II. Frequency responses are shown in from Fig. 2.41 to Fig. 2.43. Fig. 2.41 verifies the

voltage relationships of equation (2.6) in frequency domain. Fig. 2.42 and Fig. 2.43 verify the

current relationships of equation (2.6) in frequency domain. These responses also show the range

100uA-

OA

L

-100uA -100uA

❑ z (VZp)

BQuA-

50u.

QA.

-50uA-

-8Ou. -BOuA

❑ I (VZn)

42

11

1. OmP

0 . 5mA

OA-

_

1.0KHz 10KHz 0 I(R1) I(VZp)

lx+

---- - ------- 1. 0MHz 100MHz 10GHz

of frequency suitable for operation. Fig. 2.41 to Fig. 2.43 clearly indicates that voltage and

current relationships are accurate up to 50MHz.

V

+

VY

........... . . . . .........

. . ...........

10KHz LOMHz 100MHz 10GHz o V(2) v V(3)

Frequency


1.0V-

0.5V-

0V 1.0KHz

0 V(1)

Frequency

Figure 2.42 Currents (Iz+ and Jx+) in frequency domain 0

43

1. OmP•

0 . 5mA

_

____ 1-

............ T ...

_____ ................

1. oxaz 10KHz 1.OMflz 100MHz 10GHz o X(R2) o I(VZn)

Frequency

Figure 2.43 Currents (Iz- and I) in frequency domain

Fig. 2.44 and Fig. 2.45 show the voltage gain in dB. These responses of voltage gain also show

that the bandwidth of DXCC-II is around 100MHz.

......... ... __................. ....--

------------- . ......

01 1.0KHz 10KHz 1. 0MHz 100MHz 10GHz

u DB(V(2)/V(1)) Frequency

E

Figure 2.44 Voltage gain (Vx+/ Vy) in dB

G a i a

-2 n

d B

-4

44

Ii]

G a 1 n

1 -25 n

d 13

-50-I— I 1.0KHz 10KHz

o DB(V(3)/V(1)) 1.0MHz 100MHz 1.0GHz

L.

Frequency

Figure 2.45 Voltage gain (Vx-I Vy) in dB


respectively. These responses show the good bandwidth range of DXCC-11.

10-

G

:1+ n

0• n

d B 5

1.0KHz 10KHz 1.0MHz 100KHz 10GHz 0 DB(I(VZp)/I(R1))

Frequency

Figure 2.46 Current gain (Iz+ / Ix+) in dB

45

PSPICE simulation is also carried out for sinusoidal input. These results also give

a good agreement between expected and simulated results. These results also verify the basic

equations for DXCC-11 in time domain and are shown in Fig. 2.48 to Fig. 2.50. The total

harmonic distortion (TFID) is found to be less than 1%. 200mV - -

-200mV - Os Sus oV(1) V(2) vV(3)

Ov. ;ifrz:Ts ,IITTS 7I* iI1 LI

................ ....

~--4 . ..... -_4

i C

.... . ............ . ... -- -

..........

- ------

lOus l5us 20us

. ... .......... .. Ai. - -- - -- ---- ------------ - - ------

. ........ .

. ..........

1.0MHz 100MHz 10GHz

L

Frequency

Figure 2.47 Current gain (Iz- I Ix- ) in dB

+ Transient analysis

-2.( 1.0KMz 10KHz

C DB(I(VZn)/I ( R2))

Time 4

Figure 2.48 Input/output voltages at Y, X 1- and X- terminals

46

-2 OOuk Os n I (Rl)

2 0 QuA-

OA-

5us lOus v 1(VZp)

Time

15us 20us

2OOuZ

DA

Figure 2.49 Input/output currents at X+ and Z+ terminals

II .. ii I;IiI - - --

Figure 2.50 Input/output currents at X- and Z- terminals

-200uA Os o '(R2)

5us lOus l5us 20us G I(VZfl)

Time

47

2.5 Proposed Dual X Current Conveyor-II (DXCC-II) with buffered output*

The DXCC-I1 with buffered output is a combination of regular DXCC-II and a buffer. It

has one extra low impedance terminal, which is needed for voltage-mode applications.

2.5.1 CMOS implementation of DXCC-II with buffered output

The DXCC-II with buffered output is also a five-port building block which is

defined by the following matrix equation:

VX* 0 0 1 0 a iX+

VX - 0 0 —1 0 0 II IX-

I VW 0 0 0 1 0

i = 0 0 0 0 0 YY I (2.8) IIz+i 1 0 0 0 0

II Vz+ I

Lz-] p 1 0 a s Yz

where,

Vv = Voltage at Y terminal

Vx+ = Voltage at X+ terminal

V x_ = Voltage at X- terminal

Vw = Voltage at W terminal

Iy = Current at Y terminal

Iz+ = Current at Z+ terminal

IZ_ = Current at Z. terminal

Ix± = Current at X1- terminal

Ix- = Current at X- terminal

The symbol of DXCC-II with buffered output is shown in Fig. 2.51. The DXCC-II with

buffered output has several terminals as follows:

• One high input impedances voltage input terminals: Y

• Two low impedance current input terminal: X+, X-

• Two high impedance current output terminals: Z+, Z-

• One low impedance voltage output terminal: W

The content is based on Author published paper Pt.

48

Zy Vy Y IZ+

Ix+ Z+ VZ+

'x+ I- X+DXC'C -II IZ-

Ix~ Z- '

V

Figure 2.51 Symbol of DXCC-II with buffered output

The CMOS implementation of DXCC-II with buffered output is shown in Fig. 2.52. VDD

W.

VSS

Figure 2.52 CMOS implementation of DXCC-II with buffered output

The differential pairs M, M2 and M7—M8, together with transistors M„ and M13 construct active

feedback loops which provide low input impedance at terminals X+ and X-, respectively. Since

the differential pairs are biased with the drain currents of the PMOS transistors M17 and M18

(controlled with the bias voltage VBB), one can increase the bias currents (by decreasing VaB) to

improve the linearity of the DXCC-II. However, this results in more power consumption. The

transistor, M3 together with M7, M8 and M13, are involved in a voltage inverting mechanism

which inverts the voltage of terminal Y to terminal X-. Further, the transistors M12 and M14 are

employed to transfer the X+ and X- terminal currents to Z+ and Z- terminals, respectively.

k.

Transistors M21 to M28 with a bias current Ia combinely form a buffer, which provides

one extra low impedance terminal W. The voltage at Z+ terminal is equal to the voltage at

terminal W.

2.5.2 Non-idealities

Taking the non-idealities of the DXCC-II into account, the relationship of the

terminal voltages and currents of the newly developed DXCC-1I can be rewritten as

0 0 'ski 0 0 Tex+ Vx- 0 0

Ix- Vw 0 0 0 yk 0 Ir 1 — 0 0 0 0 0 VY (2.9)

Iz+ aki 0 0 0 0 vz+

Iz - a ak1 0 o o yZ-

where, J3*j(s), /3k2(s) and yk(s) represent the frequency transfers of the internal voltage followers

and aki(s), ak2(s) represent the frequency transfers of the internal current followers of the kth-

DXCC-II, respectively. If the DXCC-II is working at frequencies much less than the corner

frequencies of flkf(s), #0(S), yk(s), ak,(s) and ak2(s), namely, then flk,(s) _ /3k1= I -c -j where, cl

(Ic ,iI «I) denotes the voltage tracking error from the Y terminal to the X+ terminal of the kth-

DXCC-II; /3,u(s) = flk2=1-sk,,2 where, EA-2 (IEki21 <<I) denotes the voltage tracking error from the Y

terminal to the X- terminal of the kth—DXCC-II; yk(s) = yk=l-&kwhere, sk„ (IEt <<I) denotes the

voltage tracking error from the Z terminal to the W terminal of the kth—DXCC-II; a ,(s) = ak!

=1-cka1 where, ckri (] I «I) denotes the current tracking error from the X+ terminal to the Z+

terminal; and 1(s) = ak2 =I-skr2 where, sk,2 (lEki2I <<1) denotes the current tracking error from the

X- terminal to the Z- terminal of the kth—DXCC-II.


The performance of the proposed DXCC-II with buffered output is verified using

the SPICE simulation program. The simulations are based on 0.1811m TSMC CMOS parameters.

The supply voltages used are f2.5V, VBB = -1.55V, Cc = 0.06pF and In = 25µA. The newly

developed DXCC-II with buffered output exhibits low output impedance at W which was

measured and found as 1851).

so

• DC analysis


separately. Fig. 2.53 to Fig. 2.58 show the DC characteristic of DXCC-II with buffered output.

Fig. 2.53 shows that when DC voltage of 50mV is applied at input terminal Y then DC voltage of

50mV is available at terminal X+ and DC voltage of -50mV is available at terminal X-. lOOrnV--- - - ____

-lOOmV• OS a V(1)

ov.

V Y

V -'----

4-- .- - 4i.is Bus l2us 16us 20us

o V(2) v V(3)

q

Time

Figure 2.53 Verification of input voltages (Vx++Vy and V+-Vy)

Fig. 2.54 shows that the voltage at W terminal (Vw) is same as the voltage at Z+ terminal (Vz+).

Therefore, Fig. 2.53 and Fig. 2.54 verify the relationship of voltages of equation (2.8).

-p:— - - - - ----

5us lOus 15us 20us

Time

Figure 2.54 Verification of output voltages (VwVz+)

10 Cmv

5 Cmv

0v. Os n V(4) o V(6)

51

—lOOmV- 11 M

—10 0irU! o V(6)

lOOmV•

Dv.

II:IIIIIIIIIII

—5OmV Dv 50mV lOOmS!

4.

Fig. 2.55 shows the variation in voltages at X, terminal (V +) and X- terminal (Vx-) against the

input voltage at Y terminal (Vy). Fig, 2.56 shows the variation in voltage at W terminal (VW)

against the voltage at 14. terminal (Vz-1-). Fig. 2.55 and Fig. 2.56 prove that equation (2.8) is

correct. It is obtained by varying Vy and Vz+ from -I OOmV to +lOOmV and is shown in Fig. 2.55

and Fig. 2.56, respectively. Fig. 2.55 and Fig. 2.56 show good linearity range.

II III III I13 .J'I 211

I I 2I! I I IIT II II

—50MV 0

SOmV lOOmV

VIN

Figure 2.55 X+ and X- terminal voltages (Vx+ and Vx-) against VY

10 OmV

Dv.

—lOOmV —lOOmV

ci V(2) o V(3)

W—

V(4)

2 Figure 2.56 Voltage at W terminal (Vw) against voltage at Z+ terminal (Vz+)

52

1....L-

IIiIH Li E:

-5OuA

OA

50uA 100uA

10 Ou

ON

-10 OuA -10 OUP,

0 I (VZp)

Fig. 2.57 and Fig. 2.58 show the variations in output current at terminal Z+ (lz+) and output current at terminal Z- (Iz-) with respect to the input current at X+ terminal (lx+) and input current

at X- terminal (Ix-) respectively. These responses of output currents show the linearity of the

proposed active element. Fig. 2.57 and Fig. 2.58 also verify the current relationships of equation

(2.8).

I (R1)

Figure 2.57 Output current at Z, terminal (Iz-,) against input current at X+ terminal (lx+)

0uA ..

17- .-8OuA -80uA -4OuA OA 40uA BUuA

a I (VZn) I(R2)

Figure 2.58 Output current at Z. terminal (Iz..) against input current at X- terminal (Ix-)

53

+ AC analysis

AC analysis is also done by applying AC input signal at the input terminal of

DXCC-11. Frequency responses are shown in Fig. 2.59 to Fig. 2.62. Fig. 2.59 and Fig. 2.60 verify

the voltage relationship of equation (2.8) in frequency domain. Fig. 2.61 and Fig. 2.62 verify the

current relationship of equation (2.8) in frequency domain. These responses also show the range

of frequency suitable for operation. Fig. 2.59 to Fig. 2.62 clearly indicates that voltages and

currents relationship is accurate up to 50M1-Iz. 1.ov

0. 5V

- 011 1.0KHz 10KHz 100cHz 1.0MHz 10MHz 100MHz 1.0GHz 10GHz

o V(1) * V(2) v V(3) Frequency

Figure 2.59 Frequency response showing input voltages (Vy, and Vx-)

1.0

0.5V

Ov 1.0KHz 10KHz 1.0MHz 100MHZ 10GHz

o V(4) o V(6) Frequency

Figure 2.60 Voltages (Vz+ and Vw) in frequency domain

54

1. OmA

0. 5inA

qO

1.0KHz 10KHz 1.01Hz 100MHz 10GHz D I(RI) G I(VZp)

Frequency

Figure 2.61 Currents (Iz- and Ix,) in frequency domain

3

'p

1.0KHz 10KHz 1.OMHz 100MHz 10GHz ci I(R2) o I(VZn)

Frequency

Figure 2.62 Currents (Iz- and ix-) in frequency domain

Fig. 2.63, Fig. 2.64 and Fig. 2.65 show the voltage gain in dB. These responses of voltage gain

also show that the bandwidth of DXCC-II is 100MHz.

55

i-f

1UUNHz J.. UGHZ

G a i n

i -2.' n

d B

-50 2.0KHz 10KHz

o DB(v(3) /v(1) ) 1.DMHz

Frequency

w

G a i n

-20

d B

-401 1

1.OKHz 10KHz ❑ DB(V(2)/V(1))

1.0MHz 100MHz 1UGHz

Frequency

Figure 2.63 Voltage gain (Vx+/ Vy) in dB

Figure 2.64 Voltage gain (Vx- / Vy) in dB

N

0

G A I N

-0.5 I N

-1.01 1.0KHz 10KHz

o DB(V(6)/V(4)) 1.0MHz

Frequency

100MHz 1.0GHz

Figure 2.65 Voltage gain (Vw I Vz+) in dB


respectively. These responses show the good bandwidth range of DXCC-II.

10

G a i n

0• n

d B -5

—i 1. oKRz 10KHz 1.0 i1z 100MHz 10GHz

o DB(I(VZp)/I(R1)) Frequency

I Figure 2.66 Current gain (Iz+/ Ix+) in dB

57

-200mV Os 4us a V(1) V(2) v V(3)

20 OmV•

0v N-1 ,7

Bus l2us l6us 20us

1.0•

G a

1.0KHz 10KHz 1.0MHz 100MHz 10GHz 0 DB(IVZn)/I(R2))

Frequency

Figure 2.67 Current gain (Iz-/ Ix-) in dB

Transient analysis

PSPICE simulation is also carried out for sinusoidal input. These results also give

a good agreement between expected and simulated results. These results also verify the basic

equation for DXCC-II in time domain and are shown in Fig. 2.68 to Fig. 2.71. The total

harmonic distortion (THD) is found to be less than 1%.

T ime

Figure 2.68 Input/output voltages at Y, X and X- terminals

58

7I± 1IVTIIII11 ....

5us 15us 20us o V(6)

20 OmV

Ov.

—200ntV 05 o V(4)

-200uA- - - 0$ ci I(R1)

2 OOuA

OA

II I.iI J2

Sus IOUs V I (VZp)

Time

l5us 20us

Tirm

Figure 2.69 Input/output voltages at L- and W terminals

Figure 2.70 Input/output currents at X and Z+ terminals

59

! - 3

~ # t

_ S

t i

~ - ? E i

5us IOus Z5us 20us o I(VZn)

Time

200uA-

-200uA Os ❑ I (R2)

Figure 2.71 Input/output currents at X and Z- terminals

2.6 Proposed digitally controlled active elcmentt

Interesting improvements to the circuit proposals presented in the next chapters are

possible through some design modifications. A conventional DXCC-II is ideally characterized by

unity voltage as well as current transfer gains (please refer to equation (2.8)). Recently some

innovative enhancements to DXCC-lI were proposed [17]. One of these enhancements has

already been employed in this chapter in the form of DXCC-II with buffered output. Another

design modification presented in [17] was the gain variable DXCC-II, where the voltage transfer

gain was made variable in the AD-844 based realizations. Parallel to this enhancement will be

another gain variable DXCC-II with variable current transfer gain (referred to ap and a„). As the

performance parameters of most of the applications depend on current transfer gains. Therefore

if the active building block is replaced by a current gain variable DXCC-II, then further

flexibility of controlling the performance parameters can be achieved. Such enhancements will

enable possible digital control over circuit parameters by way of employing appropriate

techniques [18, 19]. Significant circuit improvement and automation can therefore be achieved

by designing current conveyors with non unity and variable transfer gains.

t The content is based on the author communicated paper P,1.

60

2.6.1 CMOS implementation

The CMOS implementation of Digitally Controlled DXCC-II (DC-DXCCII) with

buffered output is introduced in Fig. 2.72.

us:

Figure 2.72 DC-DXCCII with buffered output

Here, the four bit control word acts on transistors MpQ_3 and Mn4_3 with aspect ratios same as

M I 6-M 19 and Ml 2-M 15 respectively. This enables control over ap. Fine control can be obtained

by designing the output stage transistors for weighted aspect ratios.


The performance of the proposed digitally controlled active element is verified

using the SPICE simulation program. In the proposed active element, the four bit control word

(a3a2alao) acts on transistors Mp0_3 and Mn0_3 and enables control over current transfer gain (ap).

This control over current transfer gain (ap) enables digital control over circuit parameters. The

control over ap is tabulated and shown in Table 2.7.

Fable 2.7: Current transfer gain (av) control in DXCC-II of Fig. 2.72

Control Word

(Theoretical)

ap

(Simulated) a3 a2 aI -ao

0 0 0 1 1 0.99

0 0 1 1 2 1.96

0 1 1 1 3 2.94

1 1 1 1 4 3.92

61

2.7 Concluding remarks

In this chapter, an overview of DVCC, DDCC, VC-DDCC and DXCC-II along with their

CMOS implementation is presented. Furthermore, DXCC-II with buffered output and DC-

DXCCII with buffered output are proposed. The CMOS implementations of both active elements

are also given.

The important characteristics with non-ideal equations, parasitic study and simulation

results of all active elements are given. Device enhancements are further discussed as future

solutions along with some results on digital control over current transfer gain of the active

element.

62

CHAPTER 3

PROPOSED FIRST ORDER ALL-PASS SECTIONS

All-pass filters are used to correct the phase shifts caused by analog filtering operations

without changing the amplitude of the applied signal. In the literature, many first order all-

pass filters were proposed using different types of current conveyors such as [20-54]. Most of

the papers are on first order voltage-mode (VM) all-pass filter [20-47 and 49-54]. Although

the recently proposed DVCC based VM all-pass filters in [43-44] employ grounded

capacitors and resistors, which are advantageous in the reduction of parasitic impedance

effects as well as in easy integration in VLSI systems, they still suffer from the need of

passive component matching. In one work, a resistor less VM all-pass filter employing two

DVCCs and a single grounded capacitor has also been reported [15]. Although the proposed

circuit in [44] does not require a matching condition and provides low output impedance, it

still suffers from a lack of high input impedance. The most recent circuits of first order

voltage-mode all-pass filter [47] use a single active element as FDCC-II and two grounded

passive components. The circuits also enjoy the feature of high input impedance and low

output impedance. But the FDCC-II based work [47] employs as many as 35 transistors along

with a floating current source, which is cumbersome to implement. The DDCC based all-pass

filters in [29, 31] offer good options. However, all of these filters do not possess high input

impedance and/or low output impedance. The work [29] presented an all-pass filter using

differential difference current conveyor (DDCC). Similar to [29], recently presented an all-

pass filter using DDCC with minimum number of passive elements [31].

In this chapter, different circuits of first order voltage-mode all-pass filter are given.

In section 3.1', a new circuit of first order all-pass filter, using only two DDCCs, one resistor

and one grounded capacitor is proposed. The proposed filter does not need any matching

condition to realize the ail-pass filter transfer function and enjoys both high input and low

output impedance features. The non-ideal analysis of the proposed filter is also given. In

addition, the parasitic impedance effects of the active elements on the proposed filter are

investigated. Next, section 3.2' and 3.3* presents eight new first order voltage-mode all-pass

filters. All the circuits employ single DXCC-II with buffered output. The first two filters in

The content is based on the author published papers P8. P1 . 63

aeetion 3.2 and 3.3 have two passive components while the other two filters in the same

sections have three passive components, out of which two are grounded. All of the eight

proposed filters have high input impedance and low output impedance. It may be noted that

high input impedance is an important requirement for voltage-mode circuits, especially as

several such circuits/blocks can be cascaded without loading problem. Two components

based all-pass filters benefit from no matching condition requirement, whereas the three

components based filters do need matching conditions, in form of matched resistors or

capacitors. The circuit with matched capacitors may be tuned for their pole-frequency by the

third component, which is resistive, while the circuit with matched resistors needs to be tuned

through the third element in capacitive form. Furthermore, in section 3.41, two new first order

current-mode all-pass filters employing a single DXCC-II are presented. The proposed

circuits employ only one resistor and one capacitor and they have no element matching

restriction. Both circuits have low input and high output impedance. All the proposed circuits

of this chapter are verified with PSPICE simulation tool.

3.1 Voltage-mode circuit using DDCCt


DDCC based circuit configuration for realizing first order all-pass filter is

shown in Fig. 3.1. The circuit contains two DDCCs as active element and one resistor and

one grounded capacitor as passive elements. It may be noted that the proposed circuit uses

two DDCCs, each implemented with only ten MOSFETs (due to unused Z stages in Fig.

2.18). Thus the new proposed circuit with only twenty transistors is very simple. The new

circuit also exhibits high input impedance and low output impedance.

The circuit is characterized by the following voltage transfer function and phase function:

1 Vout (3.1) ~n s+ VRC

/gyp =1$0-2 tan coRC (3.2)

Equation (3.1) shows the standard voltage transfer function for a first order all-pass filter with

unity gain and pole frequency, coo = 1/RC. Frequency dependent phase function (t) is given

in equation (3.2). The salient features of the proposed circuit are high input impedance, low

output impedance and use of grounded capacitor.

t The content is based on the author published paper P7.

t The content is based on the author published paper P.

64

Yl DDCC(l)XI v"'t

Y2 Y3

YE I R DDCC(2) X

Y3 y2 T C

.a. Figure 3.1 Proposed cascadable first order all-pass filter

3.1.2 Non-ideal effects

The voltage-mode all-pass filter of Fig. 3.1 is reanalyzed using equation (2.4)

(non-ideal equation of DDCC), thus transfer function becomes as:

s_ fi12 21+f23) fill

____ LVout = /6uRC (3.3)

Vi IRC

Zip =180—tan coRC fi''-(fi21+#23) 1 (3.4) Ij612(1021 + fl23)— f 11

Here, P11, X312 are the voltage transfer gains from Y1, Y2 terminals respectively to the X terminal of DDCC1 and (32L, P23 are the voltage transfer gains from Yi, Y3 terminals respectively to the X terminal of DDCC2. Equation (3.3) shows that the pole-frequency is

unaltered by DDCC non-idealities for the transfer function of the respective circuit, but the

filter gain is slightly modified due to the DDCC non-idealities.

3.1.3 Effects ofparasitics

The proposed circuit of Fig. 3.1 is reanalyzed by taking the parasitic effects of

DDCC into account. As the X terminal of the DDCC2 is connected to a resistor, the parasitic resistance at the X terminal of the DDCC2 (Rx2) can be absorbed as a part of the main

resistance. The value of Rx is much smaller then the external resistor (R) so pole-w0 of the proposed circuit of first order voltage-mode all-pass filter will be less affected. The effects of

the capacitors at port Y of the DDCC1 are also negligible because these capacitors are quite

65

small (and process dependent) as compared to the external capacitors. However, the effective

value of the resistor and capacitor after parasitic inclusion is given below:

R' = R+R and C' = C+Cy12 (3.5)

where, Rxz is the parasitic resistance at X terminal of the DDCC2 and Cv12 is the

parasitic capacitor of Y2 terminal of DDCC 1.

From equation (3.5) it is clear that the parasitic resistor of X terminal of the DDCC2 appears

in series with the external resistor (R) and parasitic capacitor of Y2 terminal of DDCCI

appears in shunt with external capacitor (C). So the transfer function of the proposed first

order all-pass filter circuit including parasitic effects is given as:

RY12 — R'

'out Rr12R'C'

Tf~n RY12 + R' (3.6) s+

Rr12R'C'

where R' = R+R , C' = C+Cy12 and Ry12 is the parasitic resistor of Y2 terminal of DDCC 1.

Equation (3.6) suggests that pole and zero frequency would be different. However, for typical

design (R' << RY12), the modified pole and zero frequencies are to be in close proximity so as

to justify all-pass operation. Therefore, it is to be concluded that the circuit is not adversely

affected by the parasitic capacitances and X terminal resistance.


The voltage-mode all-pass filter of Fig. 3.1 was simulated using the CMOS

implementation of DDCC. The circuit of voltage-mode all-pass filter was designed with

C=10pf, R=10KQ. The designed pole-frequency is 1.59MHz. The simulation results show a

pole frequency of 1.57MHz that closely matches the designed frequency. The discrepancy in

the pole frequency is due to the non idealities as discussed in the previous sub-sections. The

gain plot of the circuit of Fig. 3.1 is shown in Fig. 3.2, while phase plot is shown in Fig. 3.3.

Next, Fig. 3.4 shows that at the pole frequency of 1.59MHz input/output waveforms are 900

phase shifted as expected. The Fourier spectrum of the output is shown in Fig. 3.5. The total

harmonic distortion (THD) of the proposed circuit is within 2%.

66

5.0-

G A

Y N

0.

N

d B

I 1 1 i . I I 1 , I 1 I --------r---------r--------- ---- ----r------_--,---------- ------- -r -------- 1 1 1 1 1 I I . r

1 I I I

1 p 1 1 1

r r -------------------L.—•—•—•--

I

-•-••--- !---------J----------

i

1 r -------- ---------- ! 1 1 1 ! 1 1

L 5 f 5 1 1 f 1

-- --------L-- -------- -----L -------J— ------ -------- - ------- ------- 1 1 1 I 1

--------f _._~---_—r------`_- ---------I•---•--•—Y --------- -------- r—.---.---

1 I I I ----L---------L --------- --------- ---------'---------- ---------'----------

r 1 , , ,

1 I 1 r 1 1

1 1

I

~ 1

1.0KHz 1.011h z 1001H z

Frequency

Figure 3.2 Gain plot of the proposed circuit

::::::* :E::!T:: :::::::::L::::::::: ::::::::::::::::::::::::: i I 1 1 1

1 . 1

I . J

r 1 1 i 1

r 1 1 1

1 1 1 1 1

1 I 1 1

---------'---------!--------- ---------+--------- --------- ---- ---L--------- 1 1 1 1 1

1 1

I / 1 1 1 1 1 1

I

1.0MHz 1.01Hz 100IlHz

Frequency

Figure 3.3 Phase plot of the proposed circuit I I 1 1 I I I I I I . I I 1 I I I I r r • • I . . . . • 1

Y I . r Vv` • . I • . 1 •

— l---T — T--1--- T -- — T — 1--- --T— 1---r —1--- ---r—•l'-- ---, —' 1 1 1 1 i 1 I 1 1 1 1 1 1 1 1 r

I 1 I I

J 1 1 .

1 .

1 1 1 I .

I .

I 1 1 . • i

1 •

1 1 1 I i 1 1 1 1 1 1 1 1 I 1 I • • 1 I 1 1 ,

1 1

I 1 I 1

I 1 1

I .

• • 1 1 •

1 1

1 1 i 1 1 ,

1 1 I 1 1 1 i I 1 1 1 i 1 i

1 1 1 1 1 1 I ! J 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 a 1 1

1 1 I I I I I 1 • • 1 . I I 1 1

2.Ous

180d•

P H A S E

I 90d-N

D E G

-5.0 1.0HZ

V DB(V(4)/V(2) )

as 1.0Hz

o P(V(4))

1.ov-

0

-1.av Os 0.5us 1.Ous 1.5us 0V(3) 4 V(2)

Time Figure 3.4 Input/output waveforms at pole frequency

67

1 1 I 1 I I I 1 1 1 I 1 I I I 1 1 I 1 I I 1 I I • I 1 I I 1 I 1 1 1 1 •

1 1 I 1 1 1 1 1 1 1 1 'II I 1 1 1 1 1 1 1 1 I

I I I 1 I r 1 I 1 I 1

I I I I I I I 1 1 1

r I I I I 1 I I 1 1 . I r 1 1 1 1 I 1 I 1 I I I 1 1 I 1 I I 1 1 • 1 1 I 1 1 1 1 1 1 1 1

I 1 I I I I I I 1 1 r 1 . I 1 1 1 1

I I I I 1 I I I 1 I 1 1 1 1 I I a 1 1 1 e 1 1

1 I I 1 I I I I 1 1 1 • 1 I 1 I I I I I 1

I 1 1 1 I I I r 1 I I I I 1 1 I

I I I I

I I

1 1

1

I 1 I I

1 1 1 I . 1 1 1 I I 1

1 1 1 1 1 1 1 1 1 1 1 I I 1 1 1 I I 1 1

413Hz $IHiz 12HHz 1611Hz

Frequency

Figure 3.5 Fourier spectrum of the output at 1.59MHz

3.2 Voltage-mode circuits using DXCC-IE

3.2.1 Topology-I

The proposed voltage-mode first order all-pass filter topology is shown in Fig.

3.6. The proposed topology is characterized by the general transfer function as given below:

V0 _ (1f Z,)+(21Z4 )—(2/Z2 ) V,. (11Z3)+ (2IZ 4 )+(21Z 2 ) (3.7)

14

60 amV-

400mV.

20omV.

OY 0Hz

o V(4)

U

Figure 3.6 Proposed topology of all-pass filter

Specialization of the impedances in Fig. 3.6 yields four different circuits of first order all-pass

filter as described below.

§ The content is based on the author published papers P,.

68

3.2.1.1 Filter 1

Selection of the impedances in Fig. 3.6 yields a circuit of first order

voltage-mode all-pass filter by retaining impedances Z2 and Z4 while open circuiting

impedances Z, and Z3. The selection of impedances is as Z2 is taken as resistive and Z4 as

capacitive reactance (Z4=11sC4). The new circuit of Filter 1 is shown in Fig. 3.7.

vo R 2

Figure 3.7 Proposed circuit of Filter 1

The transfer function of the proposed circuit of Fig. 3.7 is given as below,

Tta _ s — (11 C 1 R 2)

V; s + (11 C f R 2) (3.8)

The expression for pole-coo is given in equation (3.9).

1 a) = (3.9)

CIR2

Equation (3.8) shows the standard voltage transfer function for a first order all-pass filter with

unity gain. 3.2.1.2 Filter 2


voltage-mode all-pass filter by retaining impedances Zz and Z4 while open circuiting

impedances Z1 and Z3. The selection of impedances is as Z4 is taken as resistive and Z2 as

capacitive reactance (Z2=1/sC2). The new circuit of Filter 2 is shown in Fig. 3.8.

v4 02


The transfer function of the proposed circuit of Fig. 3.8 is given as below.

69

Ti

yC3

R2

Va__s-(1rC2RI) (3.10)

Y s + (1I CzRI)

The expression for pole-wo is given in equation (3.11).

CO = 1 (3.11) C2RI

Equation (3.10) shows the standard voltage transfer function for a first order all-pass filter

with unity gain.

3.2.1.3 Filter 3


voltage-mode all-pass filter by retaining impedances Z1, Z2 and Z3 while open circuiting

impedance Z4. The selection of impedances is as Z2 is taken as resistive and Zl and Z3 as

capacitive reactance (Zi=1/sC1 and Z3=11sC3, respectively). The new circuit of Filter 3 is

shown in Fig. 3.9.



V _ C s — (21 CR2) V C3 s+(2IC3R2)

(3.12)

The expression for pole-o 0 is given in equation (3.13).

= 2

~~ C3R2 (3.13)


with unity gain for matched capacitors (C1=C3).

3.2.1.4 Filter 4


Voltage-mode all-pass filter by retaining impedances Z1, Z2 and Z3 while open circuiting

mpedance Z4. The selection of impedances is as Z1 and Z3 is taken as resistive and Z2 as

apacitive reactance (Z2=11sC2). The new circuit of Filter 4 is shown in Fig. 3,10.

70

Vi

ft3



J s -- (112C2R1) Y —rs+(1/2C)

(3.14)

The expression for pole-%, is given in equation (3.15).

CO = (

~ 2C2R3 3.15

)


with unity gain for matched resistors (R1=R3).

The first two circuits (Filter 1 and Filter 2) use two components each, both in floating

form, whereas the last two circuits (Filter 3 and Filter 4) use three components each. The

former two circuits benefit from single resistor control. The third circuit also benefits from

single resistor control but is non-canonical, although it uses both capacitors in grounded form.

The last circuit (Filter 4) is canonical by employing single capacitor, but requires matched

grounded resistors. All four filters are further tabulated and shown in Table 3.1. It is worth

pointing that other useful bilinear functions (low-pass, high-pass, integrator and differentiator)

are also derivable from the general topology of Fig. 3.6. Therefore, the proposed general

topology does provide a broader application area which goes beyond the listing given in

Table 3.1. For instance retaining Z2 and Z3, while open-circuiting Z, and Z4 results in low-

pass and high-pass sections by taking Z2 as a resistor, Z3 as a capacitor and by taking Z2 as a

capacitor, Z3 as a resistor respectively. Similarly, retaining Z3 and Z4, while open-circuiting

the other two impedances also yield similar results. More such circuits can also further be

derived.

71

Table 3.1: Proposed all-pass filters

Circuit Impedance Specializations Filter Circuit Transfer Function

Filter 1 Z1=open circuit

Z2=R2, vi y z+ Y° s— (11 C r R 2 _ Z3=open circuit, DXCCII V, s + (11 CIR2

Z4=1/sC, X+ 1 w x- z- I —

Vo R

Filter 2 Z1= open circuit

Z2=11sC2, V. s - (1 / C2Ri)

Z3=open circuit, V s + (1 / C2R1) DxCCIY

Z4=R1 x+ - I Rl w x- r~o =

RIC2

Vo C2

Filter 3 Z1=1/sC1, vi Y 2-1- Y° _C s—(2l CIR.) Z2=R2, V C3 s+(21C3R2) DXCCII Z3=1/sC3, 2

Z4=open circuit

CI=C3 ~1

w x

[_ 1C C~ _

° CsR2

Filter 4 Z1=R1, Qi Y 2+

Z2=1IsC2, Vo s —(1/2C2R DXCCII

Z3 R3, Y s + (1/ 2C2R

Z4=open circuit x+

w x _ z-

1 co

Rl R3 2CzR3 R1—R3 Vo

C2

3.2.2 Non-ideal effects

Using the non-ideal equation of DXCC-II with buffered output (equation 2.9),

the proposed circuits are reanalyzed so as to yield the following voltage transfer functions for

Filters 1 to 4 respectively:

72

(an+ 1)Qn Vo_ Y18 p

(a P + 1 ),3pC iR z

[S_

Vi

L (ap+ 1)CiR2

~j s- ,3p(ap+1) 1

VO 8 n C 2 R 1 (a n+ 1)

VI (3.17)

(a n + I )# n S — ~r

Vo c] a P fJ p C i R 2

Vi ya f p a n+ 1 (3.18) ,s +

C3R2

a pfl p VO

S ~n(a n + 1)C 2R 1

Vi Y~ n 1 (3.19) S +

(an + 1)C 2R 3

The pole-w0 sensitivity for the circuits of all-pass filter to the non idealities as well as to the

external components is analyzed and is tabulated in Table 3.2.

Table 3.2: Sensitivity figures

Sensitivities Filter 1 Filter 2 Filter 3 Filter 4

SC -1 -1 -1 -1

t.Ojo ~ 7 ap

aP (ap + l)

p (ap + l)

0 0

+rV0 an

-an (an + I)

an an -an (an + I) (an 4 1) (an + I)

Scoo 0 0 0 0

Scoo 0 0 0 0

he sensitivity figures for the proposed circuits are all less than or equal to unity in

agnitude which implies good sensitivity performance.


The next study on the proposed circuits is carried out for the effects of

xasitic involved with the used current conveyor. It assumes special significance for

73

evaluating the real performance of any analog circuit. In the proposed topology, the

involvement of RX is important, besides port Y and port Z parasitic. A re-analysis of the four

circuits listed in Table 3.1 yields the following transfer functions with the assumption that

both X+ and X- terminals exhibit an equal resistance (Rx).

Filter 1 (+) and Filter-2 (-), dropping the suffixes from passive elements yields the following

transfer function:

1 _ S u CR

Vi 1 s+ C(R + 2Rx )

(3.20)

Equation (3.20) suggests that the two filters (1 and 2) would exhibit a slightly lower pole-

frequency as compared to the ideal value given in Table 3.1.

The transfer function of Filter 3 becomes:

s— 2 Vn

[cL] CI (-R2 - Rj Vi C3 s + 2 (3.21)

C3(R2+R,,

Equation (3.21) suggests similar observation as made with regard to the previous filters, but

with the reduced parasitic effects and hence lesser errors in pole-frequency. However, in this

case the parasitic capacitances appear along with C3 and C1, hence getting absorbed by these

external capacitors. The filter gain depends on the capacitor ratio in this case.

The transfer function of Filter 4 is:

s- 1

- -L V, R3 j s + 2 (3.22) 2C2R3

The pole frequency of Filter 4 is independent of Rx, as evident from equation (3.22), though

the zero frequency depends on Rx. Moreover, the filter gain depends on resistor ratio in this

case. It may be noted that the port Z parasitic resistances (high) appears in shunt with R3

(chosen small in design), thus not affecting the filter performance.


The new proposed circuits are verified through PSPICE simulations and to i

implement the newly developed DXCC-II with buffered output as active element the CMOS

structure (Fig. 2.50) has been used. All the proposed circuits of all-pass filters have been

designed at the pole-frequency of 25MHz. For the circuit of Filter I and Filter 2, resistance

74

F 1 1 1 I F

11 1 1 y al 1 I I 1 ____ 1____---- T....~-.ter ----- 1-------- --------r-------1-------- --------r-

! I 1 I 1 1 I 1 1

1 1 1 1 1 1 1

1 1 I 1 1 I 1 1 1 1 1 1 I 1 1

1 1 J 1 1 ! 1 1 1 I 1 1 1 1 1

1 1 Y 1 1 1

1 l F F 1 1 1 1 1 I I I

1 1 1 1

1 1 1 1 1 1 I 1 1 1 1 I 1 1

1 1 1 1 .r-----~•--- --

-•r.. n- ----•---------- ------ -~-.- -. --.r--µ--

1 1 1 1 1 1 1 ! F 1 ! ! 1 1

.r-----1-------- 1--aa. af~ ► a ar.-r.J-..-r. r- rr-rr-rrL-.r...rJr.rrrrr~J--......L

------ 1 - 1 1 I 7 1 1 1 I I I 1 I 1 1 i 1 I A

5Ons 1DOns

D .

-2 00niV Os n ;1(11 o V(5)

used is of 5KS~ and capacitor used is of value 1.27pF. The frequency response of Filter 1 is

shown in Fig. 3.11, which shows that the pole frequency is 24.93MHz with a percentage error

of 0.28%. The usefulness of new circuits is to be especially emphasized keeping in view the

design frequency which is quite high. The input/output waveforms are shown in Fig. 3.12.

The time-domain output at the pole frequency was found to show THD of as small as

0.79%, which is a very low value keeping in view the operating frequency. Next, the signal

amplitude was varied from lmV to 500mV and the ThD curve plotted. It is seen from Fig. 3.12 that the TFID is within 1% for nearly two decade variation in input signal amplitude. Fig. 3.12 shows a very good dynamic range of the new circuit topology.

20 c A 0 I

_20

- 4C 0 DB(V(5)/V(1) )

1504 P H 100d A

50d E SEL~~

Od 1.0Hz 100Hz 10F~iz

0 P(V(5)) Frequency

1.4HHz 10 01Hz

Figure 3.11 Frequency response of Filter 1

Time

Figure 3.12 Input/output waveforms at 25MHz

75

7

6

0 100 2O0 300 400 sco 600

lnputVoltage (mV)

Figure 3.13 THD variations at output with signal amplitude at 25MHz

3.2.E Experimental realization using AD-844

The new proposals in the field of circuit theory and design have often been

verified through standard tools like SPICE, but there has always been a quest for actually

building those proposals using off-the-shelf chips. The motive behind this has often been to

show the workability of the proposed circuits, as can be seen from one recent work [55]. The

topology proposed here can also be easily built using the Analog Devices chip AD-844. AD-

844 has been a useful chip both for linear as well as non-linear applications 156-58]. The

possible realization of DXCC-II is given in Fig. 3.14. The same can be used to realize the

single DXCC-II based circuit topology of Fig. 3.6. For presentation of results Filter 1 from

Table 3.1 was chosen with the implementation of DXCC-II as given in Fig. 3.14. The use of

four AD-844s for realizing a DXCC-II itself not an economical idea, but often becomes

necessary for better support to the available knowledge. After verifying the Filter 1 (Table 3.1)

both by its CMOS implementation and AD844 realization, bread board testing was also

carried out. The supply voltages used were ±1OV. The circuit was tested with Ct = 0,5nF, R2

2.2KO. The designed pole frequency is 144.72KHz. The experimental waveforms with

1.6V peak-to-peak value are given in Fig. 3.15 (a), which shows a 900 phase shift at the

designed pole frequency. The X—Y plot is also shown in Fig. 3.15 (b), which further supports

the circuit's performance as 900 phase shifter at pole frequency.

76

Y

z+'

13T

Figure 3.14 Possible experimental realization of DXCC-II using AD-844s

3 WI DU L TRACE aSCJLtOS[OP£ Lu

(a)

(b)

Figure 3.15 (a) Experimentally obtained input/output waveforms (1.6 V peak-to-peak,

144.72 kHz) (b) Experimentally obtained X—Y plot showing 900 phase shift

77

3.3 Voltage-mode circuits using port interchange in DXCC-Xl**

The new additional topology for voltage-mode first order all-pass filter is obtained by

interchanging the positions of X+ and X- in Topology-I (Fig. 3.6) of previous section.

3.3.1 Topology-ll

The new additional topology for first order voltage-mode all-pass filter is

shown in Fig. 3.16. Z4

Z2

Figure 3.16 Topology extension by interchanging X .ports

The given topology is characterized by the general transfer function as below:

Vd — Z2Z3Z4 + 2Z1Z2Z3 — 2Z1Z3Z4 (3.23)

V, ^ Z]Z2Z4 +2Z,Z2Z3 +2Z1Z3Z4

Specialization of the impedances in Fig. 3.16 yields four new circuits of first order all-pass

filter as described below.

3.3.1.1 Filter 1


voltage-mode all-pass filter. In the circuit of Filter 1, Z2 and Z4 are retained with Z2 as a

resistor and Z4 as a capacitor, while open-circuiting Z1 and Z3. No matching condition is

required. The new circuit of Filter I is shown in Fig. 3.17.

ri Y Z+

DXCCII

- w X+-

1

Vo R1

Figure 3.17 Filter 1

" The content is based on the author published papers P5.

78


Vo s—(11C1R2) (3.24)

Vi r s + {1I C1R2)

The expression for pole-tea is given in equation (3.25).

_ 1

~° CiR (3.25)


with unity gain.

3.3.1.2 Filter 2


voltage-mode all-pass filter. In the circuit of Filter 2, Z2 and Z4 are retained with Z2 as a

capacitor and Z4 as a resistor, while open-circuiting Zi and Z3. No matching condition is

required. The new circuit of Filter 2 is shown in Fig. 3.18.


'he transfer function of the proposed circuit of Fig. 3.18 is given as below.

Vo _ s-(11C2RI) V s + (1 l C2RI)

(3.26)

Che expression for pole-o 0 is given in equation (3.27).

m o = 1 (3.27) RIC2

;quation (3.27) shows the standard voltage transfer function for a first order all-pass filter

rith unity gain.

3.3.1.3 Filter 3


-oltage-mode all-pass filter. In the circuit of Filter 3, Z1, Z2 and Z3 are retained with Z1, Z3 as

capacitor and Z2 as a resistor, while open-circuiting Z4. The new circuit of Filter 3 is shown

n Fig. 3.19.

79

Vio—IY

DXCCII

X— 2- w X+

_Lc LJ 3

To r R2



Y _ Ci s—(21 CiR2) (3.28)

V C3 s+(21 C31 Z)

The expression for pole-o 0 is given in equation (3.29).

2 C3Rz

(3.29)


with unity gain for matched capacitors (C1=C3).

3.3.1.4 Filter 4


voltage-mode all-pass filter. In the circuit of Filter 4, ZI , Z2 and Z3 are retained with Z1, Z3 as

a resistor and Z2 as a capacitor, while open-circuiting Z4. The new circuit of Filter 4 is shown

in Fig. 3.20.

Vi



V. s-(1r2C2Ri) V —s+(1!2C2R3)

(3.30)

br The expression for pole-(oo is given in equation (3.31).

o = 1 (3.31) 2C2R3

so


with unity gain for matched resistors (R,=R3).

The circuits of Filter 1 and Filter 2 use two passive components. In the last two

circuits of Filter 3 and Filter 4 three components are used in each. The circuits of Filter 1 and

Filter 2 enjoy the advantage of single resistor control. The circuit of Filter 3 also enjoys the

feature of single resistor control but is non-canonical. It also employs both capacitors in

grounded form. The circuit of Filter 4 is canonical by employing single capacitor, but

requires matched grounded resistors. All four filters are further tabulated and shown in Table

3.3. It is also to be noted that other useful first order analog functions (for instance lossy and

loss less integrators, high pass filter etc) are also realizable from the modified general

topology of Fig. 3.16.


Using the non-ideal equation of DXCC-11 with buffered output (equation 2.9),

the proposed circuits are reanalyzed. The voltage transfer functions for Filters 1 to 4 are as

follows respectively:

5— (an + 1)/n

Vo_ _ (ap + I ) C i R 2 Vi y~ p a n + 1 3.32)

[ S+ (aP + 1 >C iR z

,l3p(a, + 1 ) Vo _ s 6.0 2R1(an+ 1

n Vi Y s +

(a + 1 ( 3.33)

(an+1 C2RI

(a n + 1 )p n

Vo _ C I aPf3FC iR 2 Vi r _

Ya p fp ~- 3 a n+ 1 (3.34 )

s + C 3R 2

a p/J p ___ rVo fln(a n + 1 ~C 2R I Vi Y'i n — 1 (3.35)

s + (an + 1)C 2R 3

81

Table 3.3: Proposed all-pass filters

Circuit Impedance Specializations Filter Circuit Transfer Function

Filter 1 Z1=open circuit

Z2=R2, Vi Y Z+ V. —

$ — (1 / CiR __ Z3=open circuit, DXGCII F1 s + (1l CiR

Z4=1/sCi x_ Z_ Cl ~" 1

CiR 2 ° R a

Filter 2 Z1= open circuit

Z2=1 /sC2, V. s - (1 / C2RI) _

Z3=open circuit, Vi Y Z+

V s + (1/ C2Ri) DX cczx

Z4=R1 x_ 1

Z_ w X+ 1 R1C2

vo Cs

Filter 3 Z1= 11sC1, Vi Y Z+

Z2=R2, DXCCIz Y C~ s—(2/ CiRi Z3=1ISC3, X- ~- V

_ C3 s+(2I C3R2

Z4=open circuit CI=C3 Va [_ } c 2

0)0 = C~R2 a

Filter 4 Z1=R1 , 1i Y Z+

Z2=1lsC2, Yo s — (112C2R1) ~xccz~

Z3=R3, >_ Z _ V s+(I/2C2R3)

Z4=open circuit w X+

w = 1

R1=R3 Ri

Vo

2C 2R3

C2

.r The pole-coo sensitivity for the circuits of all pass filters to the non-idealities as well as to the

external components is analyzed and is tabulated in Table 3.4,

82

Table 3.4: Sensitivity figures

Sensitivities Filter 1 Filter 2 Filter 3 Filter 4

S ~C -1 -1 -1 -1

~o 'S&P _

(ap + 1) a r

(p+1) 0 0

SaA an an

(an + 1) an

(an + 1) all

(an + 1) (an + 1)

S0 Al

0 0 0 0

Sao Al

0 0 0 0

The sensitivity figures for the proposed circuits are all equal to or less than unity in

magnitude which implies good sensitivity performance.


A re-analysis of the four circuits listed in Table 3.3 yields the following

transfer functions with the assumption that both X+ and X- terminals exhibit an equal

resistance (Rx).

Filter 1 (+) and Filter 2 (-), dropping the suffixes from passive elements yields:

1

V. s_

CR V~

5+ 1 (3.36) C(R+2Rx )

Equation (3.36) suggests that the two filters (1 and 2) would exhibit a slightly lower pole-

frequency as compared to the ideal value given in Table 3.3.

Filter 3 transfer function becomes:

s- 2

V. _ C1 C1(R2 —1)

V, C3 s + 2 (3.37) C'3(R2+R )

Equation (3.37) suggests similar observation as made with regard to the previous filters, but

with the reduced parasitic effects and hence lesser errors in pole-frequency. However, in this

case the parasitic capacitances appear along with C3 and C1 , hence getting absorbed by these

external capacitors. The filter gain depends on the capacitor ratio in this case.

Filter 4 transfer function is:

83

I s~

V, R, + Rx 1 2C2 (R1 + R1) Y` R3 s + 2 (3.38)

2C2R3

The pole frequency of Filter 4 is independent of Rx, as evident from equation (3.38), though

the zero frequency depends on R. Moreover, the filter gain depends on resistor ratio in this

case. It may be noted that the port Z parasitic resistances appears in shunt with R3, thus not

affecting the filter performance.


The new proposed circuits are verified through PSPICE simulations. All the

proposed circuits of all-pass filters have been designed at the pole-frequency of 25MHz. For

the circuit of Filter 1 and Filter 2 (Table 3.3), resistance used is of 5K! and capacitor used is

of value 1.27pF. The frequency response of Filter 1 is shown in Fig. 3.21, which shows that

the pole frequency is 24.46NJTIz with a percentage error of 0.16%. The input-output

waveforms are shown in Fig. 3.22. Frequency spectrum of the input/output waveform is

shown in Fig. 3.23. The time-domain output at the pole frequency was found to show THD of

as small as 0.62%.

40

Cr 20

I 0

N -20

-40 13 DB (V 5) /V (1) )

P Oct

H A

-200d E

SEL>> -400d

1.0Hz 100Hz 10KHz o P(V(5))

Frequency

1.0KHz 100I3Hz

Figure 3.21 Frequency response of Filter I

84

—200mV Os ❑ v(1) o v(5)

200mV-

OY .

Vi Vo€

50ns loons Time

Figure 3.22 Input/output waveforms at 25MHz 80mV

4 OM%

200MHz 400MHz

Frequency

Figure 3.23 Fourier spectrums of input/output waveforms at 25MHz

3.4 Current-mode all-pass sections using DXCC-IItt


The proposed current-mode all-pass filters are shown in Fig. 3.24. Both the

circuits employ a single DXCC-II, and the minimal number of passive components (one

resistor and one capacitor). Note that the capacitor used is in grounded form, which makes

the circuits suitable for integrated circuit implementation. Routine analysis of the circuits of

Fig. 3.24 yields the following current transfer function

tt The content is based on the author published papers P7.

ov 0Hz

❑ V(1) o V(5)

i -

85

I

'° — CR (3.39) ~IN 5 +

CR

The frequency dependent phase response (0) of the filters is given by

0(w) = —2 tan-1 (rvCR) (3.40)

It is to be noted from equation (3.39) that no passive element matching constraints are required for the proposed circuits. The proposed filters exhibit low input and high output impedance, which make them suitable for cascading without requiring additional current buffer circuit.

R C

Z1+ X-

z2+ DXCCII 1OUT

1XN ZI- X+

Y ~2-

(a)

R C

Z 1- X+

Z2- DXCCII 1OUT

'IN Z1+ II

r Z )̀+

(b)

Figure 3.24 (a) Current-mode all-pass filter-I (CMAPF-I) (b) Current-mode all-pass filter-II (CMAPF-II)

3.4.2 Non-ideal analysis The proposed circuits are reanalyzed with non-ideal DXCC-II, the modified

current transfer functions are found as

86

s+ az-a3-a4

CMAPF-I: In ur _ —az CRa2 (3.41) IN

CR

S+a4 —a1 —Ce2

CMAPF-11: T = —aq CR; (3.42)

IN Is +— - CR

From equations (3.41) and (3.42), it is to be observed that the non-idealities do affect the

filter gain, as it now depends on a2 and a4 for the current-mode all-pass filter-I and current-

mode all-pass filter-II, respectively but the pole frequency is unaltered by DXCC-1I non-

idealities. The pole-frequency (coo) and gain (H) sensitivity for the all-pass filter circuits to

the non-idealities as well as external components are analyzed and are tabulated in Table 3.5.

Table 3.5: Sensitivity figures for the proposed circuits of Fig. 3.24

Circuit S ,a.,!jz al ct,,w3A ' C `Sa 2

`sa S `a a3,f,Q3.R.0

CMAPF-I 0 -1 1 0 0

CMAPF-1l 0 -1 0 1 0

From Table 3.5, it is to be observed as the sensitivities of active and passive components with

respect to pole frequency (a 0) and gain (H) are within unity in magnitude thus ensuring a

good sensitivity performance.

3.4.3 Effects of DXCC-II parasitics

A re-analysis of the two circuits given in Fig. 3.24 yields the following

transfer function

1 s-

CMAPF-I:: I ~,. ; — (C + c1+) ( R + Rx-) (3.43) 'IN s +

(C+Czi+) (R+Rx_)

1 s-

CMAPF-II: r°ur =— (C +CZ1_) (R + Rx+) (3.44) I,N s + I

(C+CZ,_) (R+Rx+)

From equations (3.43) and (3.44), it is clearly observed that the parasitic

resistances/capacitances merge with the external values. As the X terminal is connected

directly to a resistor so the parasitic resistance at the X terminal of the DXCC-II (Rx) can be

87

10KHz 100KHz 1.OMHz 10MHz o DB(I(vout)) © a P(I(vout))

Frequency

1 2 Od-

100

04 -loos

-100

-200

:.:ix:xxiixx .IEIEEE.: 111:1

-200d• 1.0KHz

absorbed as a part of the main resistance (R) where as the parasitic capacitances (Czj_ or Czl+)

appear in shunt with the external capacitor (C). Such a merger does cause slight deviation in

circuit's parameters. It is also seen that the pole-frequency would slightly be deviated because

of these parasitic.


The proposed circuits are verified using the PSPICE simulation program. The

current-mode all-pass filter-I is designed with C = 100pF and R = 1K.Q for a theoretical pole

frequency of 1.59MHz. The phase and gain responses for the current-mode all-pass filter-I

are shown in Fig. 3.25, which show a constant unity gain and frequency dependent phase. A

phase shift of -90" is obtained at the pole frequency and the pole frequency is found to be as

1.51 MHz, which is close to the designed value. Next figure (Fig. 3.26) shows the time

domain input/output waveforms when a sinusoidal input signal of frequency 1.59MHz is

applied at the input terminal of the circuit. The output current is -90' phase shifted with

respect to the input, which verifies circuit as a phase shifter. The fourier spectrums of

input/output waveforms are shown in Fig. 3.27. The variation of the THD at the output by

varying the amplitude of the sinusoidal input current at 1.59MHz is shown in Fig. 3.28. It can

be seen that the THD value of the filter rapidly increase for the input current beyond 200gA

(peak to peak). In addition, the Lissajous pattern for the circuit as -900 phase shifter is shown

in Fig. 3.29. The simulations confirm the feasibility of the proposed circuits and results quite

agree with the theory.

Figure 3.25 Simulated gain and phase response of current-mode all-pass filter-I

88

-2.OmA- Os 0.5us

I(iin) . I(vout)

2 - OrnA-

OA

but

I.Ous 1.5us 2.0us

Figure 3.27 Fourier spectrums at 1.59MHz 3.5

3

25

2

1.5

1

03

in

Time

Figure 3.26 Input/output waveforms 1.OmA

0 . SmA iitii 0Hz 4MHz 8MHz 12MHz 16MHz

I(iin) I(vout) Frequency

1 5 10 50 100 500 1000 fin(pA)

Figure 3.28 THD variations with the sinusoidal input signal at 1.59MHz

89

1.DmA-

OA-

1 1 r I 1 1 1

1 1 f I

r 1

1 1

---_L_--J---_J-_-•L_-- I 1 1 1 ! 1 1 1

:ht:::::::i 1

Y 1 1 1 1 f 1 1 1 1 1 1 1 1

1 1 1

Y 1 1 1

1 f 1

1 1 1 1 { 1 1 1 1 1 1 1

1 I 1 I 1 1 1 1 1 1 I i I I . . I

1 1 1 1 1 1

1 I 1 1 :::

1 1 1 1 1 1 I 1 1 1 1

__

1 1 I 1 1 1 J -1,OA

-1. OrA + I(vout)

GA 1.OmA

I(iin) Figure 3.29 Lissajous pattern showing -900 phase shift at pole frequency

3.5 Conclusion This chapter presents nine first order voltage-mode all-pass filters and two first order

current-mode all-pass filters. A new first order voltage-mode all-pass filter, employing two

DDCCs as active components, one resistor and one grounded capacitor as passive

components is presented. The given circuit enjoys the features of high input impedance and

low output impedance, which is desirable feature for voltage-mode circuits. Eight other new

voltage-mode all-pass filter circuits based on topology-I and topology-II have been also

presented. All the circuits are based on a DXCC-II with buffered output, hence do not require

additional voltage followers while cascading [58]. New proposed Filter 1 and Filter 2 in both

topologies employ only two passive components, which can be appropriately chosen for

realizing two types of all-pass responses. Filter 3 and Filter 4 have three passive components

each, out of which two are grounded. Filter 3 can be tuned through a single resistor (like

Filter 1 and 2) and Filter 4 requires matched resistors for tuning. The circuits are found to

show good frequency performance, which makes them superior to existing works.

In addition to the circuits of voltage-mode all-pass filters, two novel first-order

current-mode all-pass filters, employing minimal number of active and passive components

i.e. single DXCC-II, one resistor and one capacitor are also presented. The proposed circuits

enjoy low input and high output impedance feature, which is a desirable feature for the

current-mode circuits. Beside this, the circuits employ grounded capacitor which is suited for

IC implementation in CMOS technology. No passive component matching constraints are

90

required for the proposed filters. The comparison of all the proposed circuits of this chapter is

given in Table 3.6.

Table 3.6: Comparison of proposed first-order all-pass sections

Features Fig. 3.1 Fig. 3.6 (Topology-I) Fig. 3.16 (Topology-II) Fig. 3.24

Filter Filter 3-4 Filter Filter 3-4 Filter 3 Filter 4 Filter 3 Filter 4 1-2 1-2

Mode of Voltage Voltage Voltage Voltage Voltage Voltage Voltage Current Operation Number of Two One One One One One One ' One

active elements

Number of One One One Two One One Two One resistors

Number of One One Two One One Two One One capacitors

Input High High High High High High High Low impedance

Output Low Low Low Low Low Low Low High impedance Designed 1.59MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 1.59MHz

pole- frequency Type of DDCC DXCCII DXCCII DXCCII DXCCII DXCCII DXCCII DXCCII active

element

Furthermore, non-ideal analysis and parasitic considerations for all the circuits are

also given. Simulations results are given to verify the theory. The new developed circuits are

expected to further enhance the existing knowledge on the subject.

91

CHAPTER 4

PROPOSED SECOND ORDER FILTER CIRCUITS

It is well known that current conveyor and its different variations have received significant

attention because of their high performance attributes such as extended bandwidths and

high values of slew rates [1]. Second order active filters using different kinds of active

elements are of great interest, since several cells of that kind can be connected in cascade

to implement higher order filters. It is important to realize these active filters using a

minimum number of active and passive elements, since simplicity, cost reduction, power

consumption and versatility are all important for the integrated circuit designers. In

addition to these features, numerous circuits presented in the literature realizing second

order transfer functions exhibit different properties concerning the operation mode,

sensitivity, integrability, etc. Therefore, numerous circuits reported in the literature tend to

employ a minimum number of active and/or passive components [1, 60-74]. Current-mode

analog signal filtering has also received a lot of attention in the recent past. Thus, several

multifunction or universal hi-quadratic filters using current conveyors have been reported

in the literature [13, 75-106]. It may be noted that analog filters continue to appear in open

literature as a potential analog block for larger subsystems [21, 27, 28, 46, 47, 49, 107,

108].

This chapter presents second order filter circuits. Second order all-pass filters with

the features of high input and low output impedance are presented in first two sections. In

section 4.1#, floating simulators have been employed to overcome the drawbacks of

passive inductors [109]. It may be noted that floating inductor simulators using current

conveyors have been researched well in literature [12, 110-112]. Transformation technique

has further been employed in section 4.2* to realize simpler alternative with lesser circuit

complexity. Section 43* presents a new second order current-mode biquad filter circuit

employing grounded components. The circuit uses a minimum number of components

The content is based on the author published papers Ps. P4.

92

required to achieve a second-order transfer function. Three types of transfer functions are

available at once, without any circuit modification. Moreover, the circuits using grounded

components are beneficial from fabrication point of view. Single active element based two

new second order band-pass filters with the feature of high input and low output

impedance are further proposed in section 4.41. Both the circuits employ single DXCC-i1

with buffered output, two capacitors and three resistors. The proposed circuits benefit from

low active and passive sensitivities. The proposed circuits are designed for low-quality

factor property. Both the proposed circuits enjoy the feature of high input impedance and

low output impedance. Thus the low-Q filters presented in this section are useful for

cascading. Extensive simulations are performed to validate the proposed theory, which not

only justify the proposed theory but also provide advancement to the existing knowledge.

4.1 All-pass filters based on simulated inductort

Fig. 4.1 shows the topology of all-pass filter. Selection of the impedances in Fig. 4.1

yields a circuit of second order voltage-mode all-pass filter by retaining all impedances Z1,

Z2, Z3 and Z4. The selection of impedances is as ZI and Z3 capacitive reactance (Zi=1/sC1,

Z3=1fsC3, respectively), Z2 as resistive and Z4 is taken as inductive reactance (Z4 = sL4). It

is a well known fact that real inductors are not used in integrated analog systems due to

their bulky size. Here, simulated floating inductor [109] is used in place of the inductor.

The DXCC-Il based circuit of ref [109] realizes a resistor-less floating inductor. Z4

Figure 4.1 Topology of all-pass filter

t The content is based on the author communicated paper P10 .

: The content is based on the author published paper P.

93

4.1.1 Circuit-I

4.1.1.1 Circuit analysis

The new proposed second order voltage-mode all-pass filter using

simulated inductance (L4=LS;m) is shown in Fig. 4.2. The transfer function of the proposed

circuit of Fig. 4.2 is given as below.

V0 (s) _ s2LCtiR2 —2sL +2R2 (4.1)

V (S) s2Lsi,C3R2 +2sL5trr, + 2R2

The expressions for pole-u)0 and Q are given in equation (4.2) and (4.3) respectively.

cla = 2 (4.2) C3 Lsim

FC3Rz (4.3)

From equations (4.2) and (43), it is found that the Q can be tuned independent of coo by

adjusting the value of R2. Sensitivity figures for pole-u)0 and Q are given as follows:

So° =SO'° _-1,SW° =0 (4.4) C3 L.,ins 2 Rz

1,

= Q Q = I (4.5) S S = — S — 2 C3 Lsirlr 2

From the equations (4.4) and (4.5), the sensitivity figures for the proposed circuit are found

to be less than or equal to unity in magnitude which implies good sensitivity performance.

L

C3

Figure 4.2 Proposed second order all-pass filter using simulated inductor

It is now to be emphasized that inductance simulator value is as Ls jm = (C/gmlgm2), where,

gm, & gm2 are transconductance of transistors used in simulated inductor, which can be

94

controlled by the gate voltages of those transistors [109]. Here, g,; (i=1, 2) is the

transconductance of the ith MOS transistor and is given as:

gmi = 2 ppCox (VGi - VTI ) where, i 1,2 (4.6) t

By substituting the value of LS;,,, in equation (4.1), the transfer function becomes

V0 (s) _ s2CC1R2 -2sC+2R2g, 1 gm2 (4.7)

Vs (s) - S2CC3R2 +2sC+2R2gm1gm2

The expressions for pole-m and Q are also modified and given in equation (4.8) and (4.9)

respectively.

=F~3

ga (4.8)

Q = !~D C3gmlgm l2 (4 9) G z 2C

7

Sensitivity figures for pole-o0 and Q are now given as follows:

SOry'° = -S = -S = I ,S0]~'° ; 0 (4.10) 8ml1 gyn2 C3 C 2 2

SQ =l, 8Q = Sg t gm~ =_8Q=_ (4.1)

All the sensitivity figures given in equations (4.10) and (4.11) are still less than or equal to

unity in magnitude, which suggests good sensitivity performance.

4.1.1.2 Non-ideal analysis

Using the non-ideal equation of DXCC-II with buffered output (equation

(2.9)), the proposed circuit of second order voltage-mode all-pass filter using simulated

inductor as shown in Fig. 4.2 is reanalyzed so as to yield the following voltage transfer

function:

V0 (s) s2apQpLs~mC1R2 -sLsrra/3n (1+ an )+R2lp(I+ap ) (4.12) V; (s) S2L5,,,,C3R2 +sLs,m(I+an )+R2 (l+ap )

The expressions for pole-cap and Q are given as follows:

JC3L,

I+ap rip =

(4.13)

R2 C3(l+ap )

Q l + an ~ (4.14)

95

Active and passive sensitivity figures for pole-o9 and Q are given in equations (4.15) and

(4.16).

Sty° =S ev° —_-1,s'°' =0,Sa° = p ,S ° =0 (4.15) 2 Rz P 2(l+ap )

a S =1,SQ --S~lr

— 2' Sa — 2(1+aF )'Sa I+an (4.16)

The sensitivity figures are all less than or equal to unity in magnitude which implies good

sensitivity performance. Sensitivity of filter parameters to current transfer gains will also

remain less than unity for the ideal value of current transfer gains which is equal to unity.

4.1.1.3 Parasitic considerations

A study is next carried out on the effects of various parasitic of the DXCC-II

used in the proposed circuit. The proposed circuit is re-analyzed by taking into account the

parasitic effects. A re-analysis of the proposed circuit of voltage-mode second order all-

pass filter using simulated inductor as shown in Fig. 4.2 yields: P

V° (s) s2 LS1nzC1 R2 — 2sLs,.n, +2R2 , , (4.13)

V, (s) s2L5,»rC3 R Z + 2sL,ln, +2R2

where, R2' = R2+RX.. and C1' = C i+ Cx+ and C3' (C3+Cz++Cz-)

Equation (4.17) shows that the parasitic resistances/capacitances merge with the external

value. Such a merger does cause slight deviation in circuit's parameters. It can be further

observed from equation (4.17) that the order of transfer function of second order all-pass

filter is not changed. The modified expressions for pole-ce, and Q with parasitic effects are

also given in equation (4.18) and (4.19).

coo =

F~3~km

(4.18)

FC3

Q = R2 (4.19)

Next, it is seen from equation (4.18) that the pole-frequency would slightly be deviated (in

deficit) because of these parasitic. The expression showing the effects of parasitic on po1e-

Q is also given in equation (4.19). The pole-Q would also deviate slightly because of the

parasitic.

96

4.1.2 Circuit-II


Another second order voltage-mode all-pass filter using simulated

inductance (L4°Ls;m) is shown in Fig. 4.3. The circuit is obtained by interchanging the positions of the X+ and X- terminals in Fig. 4.2 and is shown in Fig. 4.3. The transfer

function of the proposed circuit of Fig. 4.3 is given as below.

V(s) ~_s2L,-;,,,C,R2 —2sLs1m + 2R2 (4.20)

V1 (s) s 2Ls1,,,C;R2 + 2sL51R, + 2R2•

The expressions for pole-a 0 and Q are given in equation (4.21) and (4.22) respectively.

coo = 2'

(4.21) C3 ~sim

FC3 ,.,Q=RZ (4.22)

From equations (4.21) and (4.22), it is found that the Q can be tuned independent of ca. by

adjusting the value of R2.

Sensitivity figures for pole-%, and Q are given as follows:

=Sw° =—I,S~° =0 (4.23)

SQ =1,SQ = —S~;n, = 2 (4.24)

From the equations (4.23) and (4.24), the sensitivity figures for the proposed circuit are

found to be less than or equal to unity in magnitude which implies good sensitivity

performance.

L. r — --~

Cs

Figure 4.3 Second-order all-pass filter using simulated inductor obtained by interchanging

X ports in Fig. 4.2

M

By substituting the value of Ls;m in equation (4.20), the transfer function becomes

V. (s) - _ s2 CC,R2 - 2sC + 2R2gr1,1gr,,2 (4.25) f (s) s2CC3R2 + 2sC +

The expressions for pole-%, and Q are also modified and given in equation (4.26) and

(4.27) respectively.

__ 2gn)XM2 (4.26) U C3C

Q = R2 r3g;:~9-~:2 (4.27)

Sensitivity figures for pole-t)o and Q are given as follows:

SO)a ° = -S0'° = -S0'° = 1 S~f~'° = 0 (4.28) burl 9 g02 C3

SQ -1, S/~r = S-0 =1

1 (4.29) gnr 1, g,2 c 2

All the sensitivity figures given in equations (4.28) and (4.29) are still less than or equal to

unity in magnitude, which suggests good sensitivity performance.



(2.9)), the proposed circuit of second order voltage-mode all-pass filter using simulated

inductor as shown in Fig. 4.3 is reanalyzed so as to yield the following voltage transfer

function:

V0 (s) s 2 a p/3 pLC1 R2 -sL,;,,,/3,.,(I+a ye )+R 2 f3p(1+a p ) = -Y

(4.30)

V1 (s) s2 Ls1n,C3 R2 +sL(1+an )+R2(1+a p ) The expressions for pole-rao and Q are given as follows:

I+a r ° = p (4.31)

C Airu

R C 3(l+a p l+a L.

(4.32) Y! srm

Active and passive sensitivity figures for pole-o 0 and Q are given in equation (4.33) and (4.34).

a (4.33) C, _knr 2 Rz P 2(l+a p ) n

a 5' =I,SC3

tin, 2'S 2(1+aP )'Sa 1+ a,

(4.34)

98

The sensitivity figures are all less than unity which implies good sensitivity performance.

Sensitivity of filter parameters to current transfer gains will remain less than unity for the

ideal value of current transfer gains which is equal to unity.

4.1.2.3 Parasitic study

Next, the effects of various parasitic of the DXCC-II used in the proposed

circuit are studied. The proposed circuit is re-analyzed by taking into account the parasitic

effects. A re-analysis of the proposed circuit of second order voltage-mode all-pass filter

using simulated inductor as shown in Fig. 4.3 yields: r ,

S2LsimCi RZ 2SLsirn + 2R2 r r r

sz Lsi1C3 R, + sim + 2R2 (4.35)

where, R2' = Rz+Rx- and CI' = C1+CX_ and C3' = (C3+Cz++CZ_)

From equation (4.35), it has been observed that the parasitic resistances/capacitances

merge with the external value. Such a merger does cause slight deviation in circuit's

parameters. It can be further observed from equation (4.35) that the order of transfer

function of second order all-pass filter is not changed. The modified expressions for pole-

o and Q with parasitic effects are also given in equation (4.36) and (4.37).

wa = 2 (4.36) C3 hi,,,

ORC2 3 (4.37) CsinJ

Next, it is seen from equation (4.36) that the pole-frequency would slightly be deviated (in

deficit) because of these parasitic. The expression showing the effects of parasitic on pole-

Q is also given in equation (4.37). The pole-Q would also deviate slightly because of the

parasitic.


The new proposed circuits are verified through PSPICE simulations. The proposed

second order voltage-mode circuits of all-pass filter using simulated inductor have been

designed at the pole-frequency of 15.92MHz. For the circuit of second order voltage-mode

all-pass filter (Fig. 4.2) resistance used is R2 = 20KQ, capacitors used are of values Ci =

C3 ^ 1 pF and for the resistor less floating simulated inductor, the dimensions of the NMOS

transistors are WIL=2gm10.5.m. The bias voltages are selected to be 4.78V so that to

obtain a resistance of 20kK2 across each one of the MOS transistor. The capacitance C is

99

G A I N

U DB(V(5)/V(1))

1.0KHz 1.0MHz 1.0GHz

SEI -36

1.OHz c P(V(5))

P H -10 A

5 -20 E

Frequency Figure 4.4 Gain (dB) and phase (deg) response of second order voltage-mode all-pass

filter 400mV

-400mV 100ns

v V(1)

a v -

Vo Vi

V(5) Time

Figure 4.5 Input/output waveforms at 15.92MHz

150ns 200ns

set to 2pF so that to realize a floating inductance of 0.2mH. The gain and phase response

of the circuit of Fig. 4.2 is shown in Fig. 4.4, which shows that the pole frequency as

15.85MHz with a percentage error of 0.44%. The usefulness of new circuits is to be

especially emphasized keeping in view the design frequency which is quite high. The

input/output waveforms for second order voltage-mode all-pass filter are shown in Fig.

4.5. The fourier spectrum of output is shown in Fig. 4.6. The THD is found to be 1.5%.

The plot of THD variation at output with input voltage is also given and is shown in Fig.

4.7.

100

3ar—.,

20

10

12

10

2

0

0Hz 200MHz 400MHz o V(5)

Frequency

Figure 4.6 Fourier spectrum of output waveform at 15.92MHz

0 200 400 600 Soo 1000 1200 Input voltage (mV)

Figure 4.7 THD variations at output with signal amplitude at 15.92MHz

4.2 All-pass filters using frequency transformation§

Another possible circuit design is to use frequency transformation method [1131. In

frequency transformation, all the impedances are scaled by the frequency-dependent factor

The content is based on the author published papers P5.

I01

1/s. Such an impedance-level scaling operation is quite appropriate, because this operation

does not affect the transfer function. The motivation behind this scaling operation is that

scaling inductive impedance sL by 1/s leaves the circuit with the resistor of the same

value, R = L, and the inductor is eliminated. However, so as not to change the transfer

function in the scaling operation, all components must be scaled by the same factor.

Therefore, the three passive elements, namely

ZR = R, ZL = sL, Zc =1f(sC)

After transformation (ifs) yields the new components

Z'R = R/s, Z'L = L, Z'e = 1/(s2C)

Such scaling actually results in a transformation of the elements: a resistor (R) becomes a

capacitor of value `1/R', an inductor (L) becomes a resistor of value `L', and a capacitor

(C) becomes a frequency-dependent negative resistance (FDNR) and is denoted by `D' and

symbolized as four parallel lines.

4.2.1 Circuit-I


The resulting circuit after frequency transformation is shown in Fig. 4.8.

Here, the active realization of FDNR using DXCC-II may be used [114]. The active

realization of FDNR has the advantage of using a single active element and tunability by

means of control voltage. The impedance function [114] is given for the ideal case

[z]= 1 = 2, for C 1= C2 C. s2 Deq s2C-R

r The transfer function of the proposed circuits of Fig. 4.8 is given as below.

Ya (s) = s2C; R1Ra —4sC,R4 +4 (4.3 8)

V,- (s) s2C3 R3R4 +4sC2R4 +4

The expressions for pole-o 0 and Q are given in equation (4.39) and (4.40) respectively.

rya = 2 (4.39) C3 R3 R~

= C3 R3 (4.40) 2C2 Rd

Sensitivity figures for pole-n0 and Q are given as follows:

S'° =—I,S ,, =S~,, =-1 S0)° =0 (4.41) C3 R3 Ra 2' Cz

102

SQ =—SQ =1,sQ =—SQ = (4.42)

From the equation (4.41) and (4.42), the sensitivity figures for the proposed circuit are all

less than or equal to unity in magnitude which implies good sensitivity performance.

M J

D3

Figure 4.8 Proposed second-order all-pass filter using frequency transformation



(2.9)), the proposed circuit of second order voltage-mode all-pass filter using frequency

transformation as shown in Fig. 4.8 is reanalyzed so as to yield the following voltage

transfer function:

Va(,$ ) se a p,8pC?R,R4 —2sfanC2 R4 (1 +an )+2i3P (I+a p ) y (4.43)

V,. (S) s2 C3 R3R4 +2sC2R4 (1+an )+2(1+ap)

The expressions for pole-co and Q are given as follows:

l F2(1 + ap ) C% = --

R3 R4 (4.44)

C3

C3 R3 (l+a ) 3 P 44

C2 (1+ an ) 2R4 (4,45)

Active and passive sensitivity figures for pole-w0 and Q are given in equation (4.46) and

(4.47).

a 1 =Q,~'a° = p ,So° =4 (4.46)

C3 R3 Ra 2 C~ P 2(1+ap ) n

SQ = —SQ = —1, SQ = _Q — 1 2 ' SQ = ap SQ =_ an (4.47)

C.., C3 R4 2 aP 2(1+a p )' an l+an

103


sensitivity performance.

4.2.2 Circuit-II


Another circuit of second order voltage-mode all-pass filter using

frequency transformation is obtained by interchanging the positions of the X+ and X-

terminals of Fig. 4.8 and is shown in Fig. 4.9. Here also, the active realization of FDNR

using DXCC-II is used [114]. The transfer function of the proposed circuit of Fig. 4.9 is

given as below.

V0 (s) _ s2C; R1 RQ —4sC7R4 +4 V(s) s2C3R3R4 +4SC2R4 +4

(4.48)

The expressions for pole-coo and Q are given in equation (4.49) and (4.50) respectively.

(I ° _ - 2 (4.49) Ca R3 R4

Q C = 3FR 3 (4.50)

z

Sensitivity figures for pole-o 0 and Q are given as follows:

_-1 S 6'° = SC'° _ —1 ' S° = 0 (4.51) C3 R4 2 Ca

SQ = —SQ = _1,S = —SR =- (4.52) a a 3 4 2

From the equation (4.51) and (4.52), the sensitivity figures for the proposed circuit are all

less than or equal to unity in magnitude which implies good sensitivity performance.

D3

Figure 4.9 Second-order all-pass filter using frequency transformation obtained by

interchanging X ports in Fig. 4.8

IC4



(2.9)), the proposed circuit of second order voltage-mode all-pass filter using frequency

transformation as shown in Fig. 4.9 is reanalyzed so as to yield the following voltage

transfer function:

V. ( s ) s2aP ,[iPC; R,R4 —2s/3nC2 R4 (1+an )+213p (1+ap ) (4.53)

V(s) s2C3 R3R4 +2sC2R4 (1+an )+2(1+aP)

The expressions for pole-a)0 and Q are given as follows:

O 1 2(l+ap)

(4.54) n - C3 R3R4

C3 FRXap)(4.55)

CZ (l + an)

Active and passive sensitivity figures for pole-c 0 and Q are given in equation (4.56) and

(4.57).

Sa =_1,S'Q =S =0.S~° — '

a p S pa =p (4.56) Ca R4 2 ' Cz aP 2(1 + a p ) an

(4.57) C' C3 Ra 2 aP 2(1 + ap) ' an l + an


sensitivity performance.


The proposed second order voltage-mode circuit of all-pass filter using

frequency transformation has been designed at the pole-frequency of 25.18MHz. For the

circuit of second order voltage-mode all-pass filter (Fig. 4.8) resistance used is R4 = 4KfZ,

capacitor used is of value C2 = lOOpF and for the resistor-Iess FDNR, the dimensions of

the NMOS transistors are EVIL=21iml0.5µm. The bias voltages are selected to be 1.2V so

that to obtain a resistance of I.6kf across each one of the MOS transistor. The

capacitances CD I = CD12 = SOpF is set to realize FDNR D1 and the capacitances CD31 =

CD32 = 5OpF is set to realize FDNR D3. The gain and phase response of the circuit of Fig.

4.8 is shown in Fig. 4.10, which shows that the pole frequency as 25MHz with a

percentage error of 0.71 %. The input/output waveforms for second order voltage-mode all-

105

pass filter are shown in Fig. 4.11. The fourier spectrum of output is shown in Fig. 4.12.

The THD is found to be 1.1% which is also good.

G A I N

1

1 o DR(V(5) /V(1) )

_OHz 10DHz 10KHz 1.31Hz 100MHZ

P 0 d

H -100 d A S --200 d E

SEL>

1 o P(V(5))

Frequency

Figure 4.10 Gain (dB) and phase (deg) response of second order voltage-mode all-pass

filter

vo vi

_ ............... .i.-_-. ....v..._.................-__-__ice _._...... ................. .~___-_. ..._._g...u.-_..~...........«__.... ~_-a-_.. ...-....... ' I '

f f

150ns

200ns

Time

Figure 4.11 Input/output waveforms at 25MHz

0v-

-lOmV 100ns

❑ V(1) o V(5)

106

4.

OHz 40MHz 80MHz 120MHz 160MHz o V(5)

Frequency

Figure 4.12 Fourier spectrum of output waveform at 25MHz

4.3 Current-mode biquad filter *

A new current-mode bi-quadratic filter with one input terminal and three output

terminals is proposed. The given circuit uses one differential voltage current conveyor

(DVCC), two grounded resistors and two grounded capacitors. The given circuit can

realize the standard filter functions: low-pass, band-pass and high-pass, simultaneously

without changing the passive elements. The use of only grounded components is

particularly attractive for IC implementation [115].

Im

C~ x DVCC

R1 1 Y'1 Z1

R2 C2 IMP 'ZBP

Figure 4.13 Proposed current-mode biquad filter


107

4.3.1 Circuit analysis

The proposed circuit of Fig. 4.13 is analyzed using equation (2.1). The transfer

functions can be expressed as

ILP _ YCI C2RR2 I„ =

s+ 1 - 1 + + 1 (4.58)

[CZR2 CA Cil?ij ClC2AR2

IBP ~Clh

2 1 - 1 + 1 + 1 (4.59) 5+

CzRz C2R CA CiC2JM??.

s~+ I - 1 IHP 162R2 C7R s2

for Ri=R2=R) (4.60) 1 1 1 I 1 s2 +

~ S +

CaR +

C~ C~ CA CIC~ C1C2R'

From equation (4.58 — 4.60) it can be seen that a low-pass response is obtained from ILP, a

band-pass response is obtained from IBP and high-pass response is obtained from IHP under

the condition Ri R2=R.

In low-pass and band-pass responses, the pole frequency co and the quality factor Q

are given by

r.D 1

o = (4.61) C,C2R,Rz

_ C,C2R,R2 CLRI - CIR2 + C2R2

(4.62)

It may be further noted that for high-pass response, the resistors are matched as R1=R2=R

so the pole frequency coo and the quality factor Q become

rv~ RFC11C2 (4.63)

C2(4.64)

The high-pass gain, low-pass gain and band-pass gain are given by

108

HHP -1; HLP=1; FIB? = R2C2

R2C2+RiCi—R2Ci (4.65)

From equation (4.65), it has been observed that the high-pass gain, low-pass gain is unity

and the band pass gain with equal resistor design also becomes unity. Sensitivity figures of

the filter parameters of equation (4.63) and (4.64) for the proposed circuit is analyzed.

Pole-coo sensitivity is found to be 0.5 in magnitude for all elements.

ScDo =s'0 =Sa)° =S ° _-1 (4.66) A Cj C2 2

Pole-Q sensitivity for resistive and capacitive elements is respectively found as:

SQ _ C2R2 — CIR2 — CIRI

SRS 2[C2R2 + CSRi -- C (4.67) 4.67)

SQ — CIR2 + CiRI — C2R2 (4.68)

2[C2R2+CIRI—CIR2]

Q _ CiR2+C2R2--CiRI SQ 2[C2R2+ CiRi — C1R2]

(4.69)

Q — CSR[ — C2R2 — C1R2

SCz 2[C2R2+CIR1—CIR2I (4.70)

For equal capacitor and resistor design, the sensitivity of pale-Q to resistive and capacitive

elements becomes less than unity in magnitude.


The current mode biquad filter of Fig. 4.13 is analyzed using equation (2.2)

(non ideal equation of DVCC), thus transfer functions become as:

ILF CIC R2 I rr s2 + 1. ` aifli + a2/32 + a2/32 (4.71)

Cam C2R CA CC2R,Rz

sa,/3z IBP CRi _

- I ai f ~ az/3z as flx (4.72)

IM ys +s _ + + C CZRi CiI CC2RhR2

109

s2 +1 aifii

-- 111 Lc2R2c2RJ -

2 1 at/li a2/3z a2/12 (4.73) s +s - + +

C2R2 CART CiRt CC2RiR2

where, ii i and X32 are the voltage transfer gains of DVCC from the Y1 and Y2 terminals to

the X terminal, respectively, al is the current transfer gain of DVCC from X to Z1+

terminal, a2 is the current transfer gain of DVCC from the X to Z2+ terminal. The

equations (4.71 - 4.73) show the transfer function of second order low-pass filter, band-

pass filter and high-pass filter with non-idealities of DVCC respectively.

The pole frequency co, and quality factor Q with non idealities are obtained by:

(I) = a 2,82 (4.74)

ClC2RiR2

a2f 2CIC2RlR2 Q =

(4.75) CiRi - aL/ILCIR2 + az/32C2R2

where, 131 and 02 are the voltage transfer gains of DVCC from the Yi and Y2 terminals to

the X terminal, respectively, at is the current transfer gain of DVCC from X to Z1+

terminal, a2 is the current transfer gain of DVCC from the X to Z2+ terminal.

The active and passive pole-o 0 sensitivity is found to be 0.5 in magnitude for all elements.

S°=S~°=-S~°=--Sa'°=-S~° --5 °-1 (4.76) a' ~2 R, R2 Ct C2 2

Pole-Q sensitivity for active and passive elements is found as:

1 = a2)32C2R.2.- a1 f iCiR2 - C1RI SR Ri 2 a2f 2C2R2+CiRI -a►/31C1R2

4.77 (4.77)

Q 1 = aiPIC1R2 - a2 fl2C2R2 + CiRi S

2 a2/32C2R2 + CiRi - al/3iC1Rz (4.78)

S2 = 1 a2 fl2C2R2 + ail iCiR2 - C1RZ (4.79)

Cti 2 a2 f 2C2R2+CiRi - ar/3iCiR2

SQ = 1 CiRI - a2 fl2C2R2 - ai fllCiR2 Cz 2 a2f2C2R2+ CiRi -al/l1CIR2

(4.80)

lie

_ Q _ aI/3ICiR2

Sa' ~18i a2 fl2C2R2+ CiRI — aillCiR2 (4.81)

sa _ SQ _ J. CtRl—a2/32C2R2—alfIClR2 (4.82) a2 A 2 a2f32C2R2+C1R1—a1/l1CTRa

where, I' and X32 are the voltage transfer gains of DVCC from the Y1 and Y2 terminals to

the X terminal, respectively, a] is the current transfer gain of DVCC from X to Z1 +

terminal, a2. is the current transfer gain of DVCC from the X to Z2 terminal, For equal

capacitor and resistor design, the sensitivity of pole-Q to active and passive elements

becomes within unity in magnitude.


The proposed circuit of Fig. 4.13 is reanalyzed by taking the parasitic effects

into account. As the X terminal of the DVCC is connected to a resistor, the parasitic

resistance at the X terminal of the DVCC (Rx) can be absorbed as a part of the main

resistance. As the value of Rx is much smaller then the external resistor (RI), so pole-w0 of

the proposed circuit of second order current-mode biquad filter will not be affected. The

effects of the capacitors at port Y and Z of the DVCC are also negligible because these

capacitors are quite small (and process dependent) as compared to the external capacitors.

However the effective values of the capacitors after parasitics' inclusion is given below

C1(effective) = C1+Cz2++CY2, C2 (effective) = C2 +Cy1+CZ1+ (4.83)

From equation (4.83), it is clear that the parasitic capacitances appear in shunt with

external capacitors thus ensuring a possibility of pre-distorting the designed values.

Therefore it is to be concluded that the circuits are not adversely affected by the parasitic

capacitances and X-terminal resistances.


The proposed circuit of second order current-mode biquad filter (Fig. 4.13)

circuit was designed with Q = 1, f4 = 7.96MHz: C, = C2 = lOpF, R1 = R2 = 2Kf. . The

simulated frequency is same as designed one. The simulation results of second order

current-mode biquad are shown in from Fig. 4.14 to Fig. 4.18. Fig. 4.14 shows the

simulated gain plots of all three responses (high-pass response, low-pass response and

band-pass response). Fig. 4.15 shows the simulated transient output for low-pass with

111

50

G A I N

I N

d -50 B

-100- 100Hz 10KHz 1.0MHz 100MHz 1.0GHz

o DB(I(C1)/I(IIN)) o !JB(I(C2)/I(IIN)) v DB(I(R2)/I(IIN)) Frequency

ILP IBP

IHP

-200uA - 200ns

D I(R2)

200uA

OA-

.

300ns 400ns 500ns 600ns

amplitude of 200.iA peak to peak at input of 7.96MHz. Fig. 4.16 shows the simulated

transient output for band-pass with amplitude of 200p.A peak to peak at input of 7.96MHz.

Fig. 4.17 shows the simulated transient output for high-pass with amplitude of 22O.tA

peak to peak at input of 7.96MHz. The output waveform for high-pass function at 10Hz

frequency is also shown in Fig. 4.18. As it can be seen, there is a close agreement between

the theory and the simulation. The THD of the proposed circuit at all outputs is within 2%.

Figure 4.14 Gain plot in dB showing all three responses

Time

Figure 4.15 Low-pass output for sinusoidal input of 7.96MHz

112

Time

Figure 4.18 High-pass output at [0Hz

-2OOuP---- 200ns 300ns 400ns 500ns

I(C2) Time

Figure 4.16 Band-pass output for sinusoidal input of 7.96MHz

2 OOuA-

CA

600ns

-200uA 200ns 300ns 400ns 500ns

v 1(d) Time

Figure 4.17 High-pass output for sinusoidal input of 7.96MHz

200uA-

ON

IT

600ns

-2O0uA Os U 1(d)

200uA-

Ok

z71I12II1

1.Ons 2.Ons 3.Ons

113

.4 Voltage-mode band pass filtersti

4.4.1 Proposed circuits

The proposed circuit of second order voltage-mode band-pass filter is shown

in Fig. 4.19 (a). It is composed of one DXCC-II with buffered output, two capacitors, and

three resistors. Another circuit is obtained by interchanging the positions of the X+ and X-

terminals and is shown in Fig. 4.19 (b). The transfer function of the proposed circuits of

Fig, 4.19 (a) and (b) is given as below. V) = k sC4(R2R,+2R1 R2 —2R1R,)+RR —2R, (4.84) V(s) s2 R1 R,R4C3C, +sR,(R1C3 +2R2C,+2R4C,)+2R1

where, k = +1 for the circuit of Fig. 4.19 (a) and k = -I for the circuit of Fig. 4.19 (b).

For the matching condition as R2 = 2R1, the above transfer function becomes Tp{s) =k 2sR1C4 (4.85)

- J(s) S2R1 R4C3C4 +s(RAC3 +2R1C4 +R4C4)+1

where, k = +1 for the circuit of Fig. 4.19 (a) and k = -1 for the circuit of Fig. 4.19 (b),

The expressions for pole-a 0 and pole-Q are given in equations (4.86) and (4.87)

respectively.

wo 1 (4.86) I'l ~4 C3 C4

_ RIR4C3C4

Q (4.87)

R,C3 +2R1 C4 +R4C4

Sensitivity figures for pole-ü 0 are given as follows: V.

(O0 = Ste° = —1 (4.88) Ri R4 C3

C4 2

From the equation (4.88), it is clear that the pole-wo sensitivity is found to be less than

unity in magnitude which implies good sensitivity performance.

Sensitivity figures for pole-Q are given as follows:

S p _ 1 R4C4 — R, C3 — 2R,C4 A 2 R4C4 + R1C3 + 2R,C4

(4.89)

tt The content is based on the author conununicated paper P10.

114

Sg — 1 R,C3 +2R1C4 —R4Cd (4.90

R4 2 R C3 +2R1C4 + R4C4 l

S Q - 1 2R,C4 +R4C4 -R1C3

c3 2 2R LC4 +R4C4 +R,C3 (4.91)

S Q _ 1 R IC3 —2R1C4 --R4C4

(4.92) C4 2 RC3 + 2R1C4 + R4C4

For equal resistor and capacitor design, the sensitivity of pole-Q to resistive and capacitive

elements becomes less than or equal to unity in magnitude.

R4 C4

0 '-3

'U Ry

(a)

R4 C4

Ei 3

V tj T

K6

(b)

Figure 4.19 (a) Proposed voltage-mode band-pass filter (b) Another circuit obtained by

interchanging X ports

115


The proposed circuits of second order voltage-mode band-pass filter as shown

in Fig. 4.19 (a) and (b) are reanalyzed using non-ideal equation of DXCC-II (equation

(2.9)) so as to yield the following voltage transfer function:

V0(s) - k

sC4

[apj6pRR4 +,6pR,R2(a p2 + l)-15 R1R4(an+l)]+ap,8pR2 `,QnRi(an t1) -

s 2 R1 R2R4C3C4 +sR,(R2C3 +R,C4(ap +1)+R4C4(an +1))+R,(an +l)

(4.93)

where, k = +I for the circuit of Fig. 4.19 (a) and k = -1 for the circuit of Fig. 4.19 (b).

For the matching condition as R2= 2R1, equation (4.93) becomes

V°(s)- sC4 [2a p f pR4 +218 R,(a p +1)--J3nR4(a,+1)]+R, [2a p pp -/3n(an +1)]

V,. (s) 2s 2R1 R4C3C4 +s(2R1C3 +2R1 C4(ap +l)+R4C4(an+l))+(a ye +1)

(4.94)

where, k = +1 for the circuit of Fig. 4.19 (a) and k = -1 for the circuit of Fig. 4.19 (b).

The expressions for pole-w0 and Q are given as follows:

Ci) F+

4C3C4

2(an +1)R1R4C3C4

2R1 C3 +2R1 C4(ap +1)+R4C4(an +1)

Active and passive sensitivity figures for pole-coo are given in equation (4.97).

s -s"°=sj°=sr~°=-sa°=1,s~'° =o Ra 3 Ca 2 n 2 aF

Active and passive sensitivity figures for pole-Q are given as follows.

SQ - 1 R4C4 (an +1)-2R1C3 -2R1C4 (ap +1)

A 2 R4C4 (an +1)+2R,C3 +2R,C4 (ap +1)

sQ = 1 2R,C3 +2RC4 (ap +l)-R4C4 (an +l)

R4 2 2R1C3 +2R1C4 (ap +l)+R4C4 (an +l)

(4.95)

(4.96)

(4.97)

(4.98)

(4.99)

SQ 1 2R1C4 (ap +l)+R4C4 (an +1)-2R„C3

C3 2 2R1C4 (ap +1)+R4C4 (an +1)+2R,C3 (4.100)

116

Q = 1 2R,C3 -2R1C4 (ap+i)—R4C4(an+1) (4.101)

C4 2 2R,C3 +2R1 C4 (crp +1)+R4C4 (an +1)

SQ - 1 2a,R1C3+2anR,C4(ap+1)-anR4C,(a,+1) (4.102) a" 2 2RC3 (a,+1)+2R1C,(an+l)(ap+1)+RC,(an+1)2

SQ -- 2apR,C4 (4.103)

'P

2 3 +2RC4 (ap +1)+R4C4 (an +1~

From equations (4.98) to (4.103), it can be further observed that the sensitivity figures for

pole-o 0 and pole-Q are all within unity in magnitude for equal resistor and capacitor

design which implies good sensitivity performance.

4.4.3 Parasitic considerations

A study is next carried out on the effects of various parasitic of the DXCC-II used

in the proposed circuits. It assumes special significance for evaluating the real performance

of any analog circuit. The various parasitic of DXCC-lII are port Z parasitic in the form of

RZI/Cz, port Y parasitic in the form of Ry//Cv and port X parasitic. The proposed circuits

are re-analyzed by taking into account the above parasitic effects. A re-analysis of the

proposed circuits of second order voltage-mode band-pass filters as shown in Fig.

8.1yields:

V(S) —k sC4R'C'(RzR4 +2R;R-2RRR4)+R'C'(RI -2R1) V,(s) s`R'RR4 C3 C4 RZ+ R _CZ+ C _ +sR1'[RC3 RZ+ RZ _CZ+Z C - +RC4 R'C'(2+R4 ) +2R4 C4 R'C']+R'C'(2+R r I Z Z

(4.104)

where, R' i = R1+Rx+, R'2 = R2+Rx-, R' = RZ++RZ_ and C' = Cz+CZ + C2.C3+ CZ+C3

From equation (4.104), it is to be observed that most of the parasitic capacitances get

absorbed with the external grounded capacitor, as are in shunt with it. Also the parasitic

resistances get absorbed with the external resistors, as it is in series with it. Such a merger

will cause a slight deviation in circuit parameters.


The proposed circuit of second order voltage-mode band-pass filter (Fig. 4.19

a) is designed with pole frequency of 15.92MHz: Ci = C2 = IOpF, R1= RA = IKQ and R2 =

2KS2. The simulated pole frequency is same as designed one. The gain response of the

117

circuit of Fig. 4.19 (a) is shown in Fig. 4.20, which shows that the pole frequency is

15.89MHz with a percentage error of 0.18%. This gain response shows that it is suitable

for narrow band applications. The usefulness of new circuits is to be especially

emphasized keeping in view the design frequency which is quite high. The input/output

waveforms for second order voltage-mode band-pass filter are shown in Fig. 4.21. The

Fourier spectrum of output is shown in Fig. 4.22. The THD is found to be 1.5%.

The Monte Carlo analysis of the second order voltage-mode band-pass filter (Fig.

4.19 a) is next performed taking 5% Gaussian deviation in the each passive component

(C1, C2, R I, R2, and R4). The analysis is done for 5 runs. The gain response with Monte

Carlo analysis is shown in Fig. 4.23 and time domain result for Monte Carlo analysis is

shown in Fig. 4.24. As depicted from Monte-Carlo analysis results, the proposed filters

have good sensitivity performances.

Next, the proposed circuit of second order voltage-mode band-pass filter (Fig. 4.19 a)

is further designed for wide band: Cl = C2 = l OpF, R1 = 10K1, R2 = 20Kf and R4 = 1KS1

The gain response of the circuit of Fig. 4.19 (a) is shown in Fig. 8.25.

50

25

10KHz 1.0MHz 100MHz 10GHz o V(4)

Frequency

Figure 4.20 Gain (dB) response at 15.92MHz

118

SEI -50

❑ V(1) 0

10

Qs 50ns 100ns 150ns 200ns ❑ V(4)

Time Figure 4.21 Input/output waveforms at 15.92MHz

0Hz loom 200rHz a V(4)

Frequency Figure 4.22 Output waveform at 15.92MHz

50

25

10KHz 1.0MHz 100MHz 10GHz o v ❑ oV(4)

Frequency

Figure 4.23 Monte Carlo analysis of Fig. 4.19 (a) showing Gain (dB) response

119

-100mV ❑ 0Va0V(1)

50_.

SEI -50

100m

OV

Vin

Os 50ns loans 150ns 200ns ❑ oV aV(4)

Time

Figure 4.24 Monte Carlo analysis of Fig. 4.19 (a) showing input/output waveforms

for 5 nuns

Z.0,

0.5V

1.OKEiz 1.0MHz 100MHz 1.0GHz D V(4)

Frequency

Figure 4.25 Gain (dB) response showing wide band


Several second order filters are proposed in this chapter. Four circuits of second order

voltage-mode all-pass filters with high input and low output impedance in each case are

proposed in the beginning of this chapter. First two circuits of all-pass filters are based on

simulated inductor and last two circuits of all-pass filters are based on frequency

transformation technique. All the four proposed circuits of all-pass filter use the active

element namely DXCC-U with buffered output. Furthermore, a new second order current-

mode biquad filter is presented. It is very simple and contains a minimum number of

120

components required to achieve a second order transfer function. Three types of transfer

functions are available at once, without any circuit modification. The new circuit is suited

for high frequency operation. In the last of this chapter, two new second order voltage-

mode band-pass filters are proposed. Both the circuits are also simple and contain a

minimum number of active components. Although the proposed band-pass filters have a

low-Q property, they can be used for impedance matching purposes or to suppress the

sidebands of a multi pass-band filter. The proposed low-Q filters are also useful for

cascading. The comparison of all the proposed circuits of this chapter is given in Table 4.1.

Table 4.1: Comparison of proposed second-order filters

Features Fig. 4.2 Fig. 4.3 Fig. 4.8 Fig. 4.9 Fig. 4.13 Fig. 4.19

Mode of Voltage Voltage Voltage Voltage Current Voltage Operation Number of One One One One One One

active elements

Number of One One One One Two Three resistors

Number of Two Two One One Two Two capacitors

Input High High High High High High impedance

Output Low Low Low Low High Low impedance Designed 14MHz 14MHz 25.18MHz 25.18MHz 9.7MHz 15.89MHz frequency

Other One One Two Two No No elements (if Simulated Simulated FDNR FDNR

an) Inductor Inductor Type of Ali-pass All-pass All-pass All-pass Band-pass, Band-pass

responses High-pass and low-

ass Type of DXCC-II DXCC-II DXCC-H DXCC-II DVCC DXCC-II active

element

Non-ideal analysis and parasitic considerations for all the second order filters are

also discussed. All the proposed circuits of second order filters enjoy good active and

passive sensitivities. Simulations results are given to confirm the presented theory.

121

CHAPTER 5

PROPOSED OSCILLATOR CIRCUITS

A sinusoidal oscillator with multiphase or quadrature outputs is a basic building block, which has

a wide range of applications especially in telecommunications, power electronics and signal

processing and measurement systems. Among several types of the oscillators, a quadrature

oscillator is an important block which has two sinusoids with 900 phase difference. The

quadrature oscillators have various communication applications for example, in

telecommunication as quadrature mixers, as single-sideband modulators, in direct-conversion

receivers and as vector generators or selective voltmeters for measurement purposes [116-120].

Therefore, many current conveyors based quadrature oscillators are reported in the literature [13,

14, 17, 40, 56, 121-148]. These circuits provide voltage output(s), current output(s), both voltage

as well as current output(s), with a certain phase shift giving rise to quadrature and multiphase

oscillators [13, 14, 17, 40, 56, 118-151]. It may be noted that the circuits with both voltage and

current outputs have also been termed as mixed-mode oscillators [130-1351. Besides the

realization of multi-phase oscillators, third order quadrature oscillators found special attention

owing to their low-distortion output generation capability [56, 134, 136, 143, 144, 150, 151]. As

a result numerous high performance oscillator circuits continue to find most recent space in the

literature [145-149].

In this chapter, several oscillator circuits are presented. A multi-phase oscillator using

DDCCs is presented in section 5.1*. The circuit provides three quadrature voltage outputs

simultaneously. The proposed circuit enjoys low active and passive sensitivities. In section 5.2`,

a new voltage-mode quadrature oscillator based on DDCCs is presented. The proposed circuit

employs two DDCCs, two grounded capacitors, and two resistors. The use of grounded

capacitors makes the proposed circuit suitable for integrated circuit implementation. In section

5.3*, four new voltage-mode quadrature oscillators using DDCCs as active element are realized

by using a simple technique. Each circuit enjoys the attractive features such as use of grounded

The content is based on the author published papers P8, P2, P3.

122

passive components, outputs of equal magnitude and low active and passive sensitivities. Each

circuit employs all grounded passive components and provides two quadrature voltage outputs.

In section 5.4, another quadrature oscillator based on DXCC-II is presented. The proposed

circuit employs two DXCC-IIs as active elements, two resistors and two capacitors. The circuit

of quadrature oscillator provides two quadrature voltage outputs at low impedance terminals. A

sinusoidal oscillator circuit is presented in section 5.51. The proposed circuit uses DXCC-II as an

active element. The proposed oscillator gives two voltage outputs. Section 5.6t presents a new

second order mixed-mode quadrature oscillator based on DVCCs. The proposed circuit employs

two DVCCs, two grounded capacitors and two grounded resistors. The proposed circuit enjoys

low active and passive sensitivities. The use of grounded capacitors makes the proposed circuit

suitable for integrated circuit implementation. Section 5.71 presents a new third-order quadrature

'J oscillator based on DVCCs. The proposed circuit requires three DVCCs, three grounded

capacitors and three resistors, of which two are grounded. The circuit generates four quadrature

current outputs at high impedance nodes and two quadrature voltage outputs. The circuit

usability at high frequencies with low THD is confirmed.

The non-ideal analysis of all the proposed circuits is also given. The theoretical results

are verified by PSPICE simulation.

5.1 Voltage-mode multi-phase oscillator using DDCCt


A sinusoidal oscillator producing a number of quadrature signals is derived using

the basic technique given in [40]. The block diagram is shown in Fig. 5.1. It consists of two

cascaded first order voltage-mode all-pass filter and a unity gain inverter; with the output of

inverter feedback to the input of the first stage. It may be noted that inverter (gain = -1) is

realized using DDCC itself with input and output at Y2 and X terminal of DDCC respectively

and Y i and Y3 terminals are grounded. The circuit of multiphase oscillator is given in Fig. 5.2.

t The content is based on the author published papers P1 , P5, P6, P9.

The content is based on the author published papers Pg.

123

s+: s--a s- -1 .-+

v i V, V3

Figure 5.1 Proposed circuit topology of multiphase oscillator

vi YI VI

Y2 DDCC (1) X Y2 DDCC (3) X v3

-1

Y3 Y3

Vz Y1 Rl Y l R2

DDCC (2) X DDCC (4) X

Y3 Y3

Y2 Y2

C2

Figure 5.2 Proposed Circuit of multiphase oscillator

The system loop gain (VoUT / VN) is given by

Vorr 1tRtCi+ JsR2C2+l )RIC1—sR2Cz-1 )

Ju N

If loop gain is set to unity at s = jco, the circuit shown in Fig. 5.2 can be set to provide a multi-

phase sinusoidal oscillation with frequency of oscillation (FO) as:

1 o

— (5.2) 2,c CIC2R1R2

The sensitivity figures of FO with respect to passive components are low and given in equation

(5.3).

Sf0 ___ (5.3)

124

Equation (5.3) shows that all the sensitivity figures are less than unity in magnitude, which is a

good feature of the proposed circuit. The circuit provides three quadrature voltage outputs (Vi,

V2 and V3), whose phasor relationship is shown in Fig. 5.3.

V,

V3 Vi

Figure 5.3 Phasor diagram of multiphase oscillator


By considering non-idealities of DDCC (equation (2.4)), the system loop gain

(VOUT/ VIN is given by

VOUT sfil[RlC] -- fl12~21+/323) — fill sjn1R2C2— j812~21+,023)—#l] (5.4)

Vrry sR 1C1 + I sR2C2 + 1

If loop gain is set to unity at s = jco, the circuit shown in Fig. 5.2 can be set to provide a multi-

phase sinusoidal oscillation with frequency of oscillation as:

/11211h2/341(821+ fl23) fl12 fi32843 21+ fin)-/311fi32~41+/343)- fl12fl31~21+ fi23)+ /311/331 + /352

f — 2tr /3szC1CzR1R2+/3UE31C1CxRlRz

(5.5)

where, 13] 1, J312 are the voltage transfer gains from Y1, Y2 terminal respectively to the X terminal

of DDCC 1, 1321, ¢23 are the voltage transfer gains from Yl, Y3 terminal respectively to the X

terminal of DDCC2, 1331, P32 are the voltage transfer gains from Y1, Y2 terminal respectively to

the X terminal of DDCC3, 041, 043 are the voltage transfer gains from Y1, Y3 terminal

respectively to the X terminal of DDCC4 and P52 is the voltage transfer gain from Y2 terminal to

the X terminal of DDCC5.


The circuit was designed with C1=C2=10pF and R1=R2=IOKSZ, the theoretical

frequency of oscillation was around f0=1 .58MHz, whereas the simulated frequency of

oscillations was fq 1.583MHz. The quadrature outputs are shown in Fig. 5.4. Fourier spectrum

of all three quadrature outputs is shown in Fig. 5.5.

125

V11 I L

1

V

q ~

2 1

~ , V3

... J.-- .....r I 1 1

J.-~..1 - __ .... J.---_l_.- .J.---- 1 L•---- --_~__ ̂--L-... J---- -L---- 1 1 I 1 I 1 1 1 1 1

I 1 1 A 1 1 1

1 1 I t 1

1 I 1 I I 1 1

1 1 1 I 1 1 f 1

1 1 I 1 1 1 1 1 I I 1 1 1 I 1 1 1

1 i 1 1 1 1

1 1 1 1 f I 1 1 1 I I 1 1 1

1 I

1 1

! 1 1

4 !

1 1 1

1 1 f 1 1 1 1 I 1 1 1

1 1 I 1 1 1 1 1 1 I 1

I 1 f 1 1 I 1

i: :iiz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 I 1 1 4 1 1 I 1 1 1 1 1 1 1 1 1 I 1 1

1.5us 2.5uc a Vt3) a V(2)

Time

Figure 5.4 Voltage outputs of multiphase oscillator

500mV

OVI— 0Hz 50118 z 100}IHz

v V(6) aV(3) 0V(2) Frequency

Figure 5.5 Fourier spectrums of the outputs

Oy•

-1.0v

1.aus o V(6)

126

r

5.2 Voltage-mode quadrature oscillator using DDCC§


The proposed circuit of voltage-mode quadrature oscillator is shown in Fig. 5.6.

The proposed oscillator is derived using the basic scheme which consists of a first order all-pass

filter section and an integrator. It is composed of two DDCCs, two grounded capacitors and two

resistors.

V1

Y1 Z+

Y 1 R1 DDCC (2) ;2 DDCC (1) X Y2 -~-

Y3 Y3 X Y2 ~~'1

..

Figure 5.6 Proposed circuit of voltage-mode quadrature oscillator

The characteristic equation of the circuit can be expressed as

2 + s(CzR2—CiR~) + 1 =0 (5.6) s C1C2R1R2 CLC2RSR2

The frequency of oscillation (FO) and condition of oscillation (CO) can be obtained as:

FO: fo = 1 (5.7) 2r C1C2RiR2

CO: C2R2 <_ CiRi (5.8)

The two quadrature voltage outputs (Vi and V2) of the proposed circuit, depicted in Fig. 5.7, are

related as

V2= jwC2R2Vi (5.9)


(5.10).

§ The content is based on the author published papers P2.

127

f I

o _ 2 (5.10)

Equation (5.10) shows that all the sensitivity figures are Iess than unity in magnitude, which

shows good sensitivity performance of the proposed circuit.

V2

v1

Figure 5.7 Phasor Diagram depicting quadrature voltage outputs


The voltage-mode quadrature oscillator of Fig. 5.6 is reanalyzed using non-ideal

equation of DDCC (equation (2.4)), thus characteristic equation becomes as:

s2 + S(C2R2 - f.,821C1R1) + a[ 22 11+/319)- )32h} - 0 (S.11) CIC2RIR2 C1C2RIR2

The modified frequency of oscillation and condition of oscillation are given as:

0 a _ 22(,811 + Q1s) — /321 5.12

— 2'r CIC2RIR2 ( }

C2R2 <_ q,,D2iCiRI (5.13)

Here, p11, 1L3 are the voltage transfer gains from YI, Y 3 terminals respectively to the X terminal

of DDCC1 and 321, 1322 are the voltage transfer gains from Y1, Y2 terminals respectively to the X

terminal of DDCC2. a is the current transfer gain from the X terminal to Z+ terminal of DDCC2.

The sensitivities of active and passive components are within unity in magnitude. Thus, the new

circuit of voltage mode quadrature oscillator enjoys attractive active and passive sensitivity

performance.

128

5.2.3 Effects of parasitics

The proposed circuit of Fig. 5.6 is reanalyzed by taking into account the parasitic

effects. As the X terminal of the DDCC1 and DDCC2 is connected to a resistor, the parasitic

resistance at the X terminal of the DDCC (Rx) can be absorbed as a part of the main resistance.

As the value of RX1 and Rx is much smaller then the external resistor (R), so frequency of

oscillation of the proposed circuit of voltage-mode quadrature oscillator will be less affected. The

effects of the capacitors at port Y and Z of the DDCC are also negligible because these

capacitors are quite small as compared to the external capacitors. However, the effective values

of the capacitors after parasitics' inclusion is given below

C1(effective) = C1+Cy22, C2 (effective) = C2+Cz2+CY12+Cyi 1+ Cv31 (5.14)

From equation (5.14), it is clear that the parasitic capacitances appear in shunt with external

capacitors. Therefore, it is to be concluded that the circuit is less affected by the parasitic

capacitances and X-terminal resistances.


To verify the theoretical prediction of the proposed circuit, Fig. 5.6 was designed

with C1 = C2 = lOpF, R1 = R2 = 10KfI, for the oscillation frequency of fQ = 1.59MHz. The

simulation results show oscillation frequency of 1.57MHz that closely matches the designed

frequency. The discrepancy in the frequency of oscillation is due to the non idealities (equation

(5.12)) as discussed in the previous section. The waveform of simulated two quadrature voltage

outputs is shown in Fig. 5.8. Fig. 5.9 shows the simulated frequency spectrums of V1 and V2.

The X-Y pattern of two outputs V1 and V2 in Fig. 5.10 shows and verifies the quadrature

relationship. The phase difference between these two voltage outputs is 90.03°, which is

calculated with the help of Fourier transform data. Furthermore, The FO is found to vary from

1.59MHz to 15.92MHz for R (if R1 = R2 = R), variation from 10Kt) to 1KKI respectively. The

result of frequency control is given in Fig. 5.11. The THD of the proposed circuit at all outputs is

within 0.92%, which is low.

129

-1.Ov-. Os v v(4)

1.0V•

OY

1 1 Y 1 1 1 I

___r - _'r___r___r_ - _ _ -r___r.._r __T___ ' ''-- I-- -_r _T__ - ---'----'----''---'•--- 1 1 1 1 ~ I 1 1 1 I I 1 1 r 1 1 Y

1 1 1 1 1 1 I 1

1 1 I 1 1 1 1 1 1 1 1

1 1

1 1 I 1 1 1 1 1 1 1

1 1 1 1 I I I I 1 1

7 1 1 1 I 1 I 1 1

1 1 I 1 1 1 ! 1 1 1 1 1 1 1

1 I .

1 r 1 I 1 1 1 1 1 1

1 I 1 1 I 1 1 ! 1 1 1 I 1

1 1 1 1

4 1

I 1

4 1 i I I 1 1 1

1 1 1

1 1 I 1 1 1 I 1 1 1 1 1 Y

r I 1 1 f 1 I 1 1 I

---~---' I ---1--- 1 1 -'---- 1 1 1 ---' -- '--J---J------- 1 1 '--' 1 1 1 '-- J̀-------- 1 -- ,--- 1 -1•_- 1 `--- 1 '----1 1 1 1 1 1 1 I 1 1 I 1 1 1

0.5us 1.Dus 1.5u2 2.Ous a V(1) TIRE

Figure 5.8 Quadrature output waveforms

801

401

lillV r 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 I I 1 ! 1 1 1 1 1 1 1 1

r I I I I 1 1 ___

1 ----r---- r-~•~r _.-- ----r -.-_r ___ T ___ ___T ____r --__I._-__

• 1 I 1 I I I I 1 I I 1 1 1 1 1 1 I I 1 1 1 1 1

1 1 1 I P I 1 ~ . • . 4 r 1 4

1 1 I / 1 1 1 I 1 r 1 1 I 1

1 1

~ 1 1

_ ••---1 -___ 1 1 1

____fir•----------- 1 1 1

1 1 -~~ --------- -__----------------------- I I

1 Y

1 1

r r 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 I

1 1 I I 1 1 1 1 I

IM i r 1 I i 1 ! 7 1 1 t J I 1 1 I 1 I I 1

1 1 1 1 1 1 Y 1 1 1 1 1 J J 1 r f 1

r.__T._-- --- --- r ---- ____T___T ___ T ____ 1 1 1 1 1 1 1 1 1 r 1 1 I I 1 1 1 1 I 1 1 1 1

1 1 1 1 1 1 1 1 Y 1 ! I 1 1 1 1 1 1 I 1

; ; i ; 1

i ~ ; i I 1 P 1 I 1 1 r 1 1 1 1 I

-- -••--'----- ---•5---- --- !---- -------- I----J--------- 1-•- -I---- !-•- ---- - 1

1 1 1 1 1 1 1

! I 1 I 1

1 1 1

1 1 I 1 1 1 1 I 1 1

0Hz 4HHz 8}lHz 12BHz 16IIHz

9 V(4) o V(1) Frequency

Figure 5.9 Frequency spectrum of outputs V1 and V2

130

---J---- 4----L---J---- ----L---J----J--- -~---- 1 1 1 /

I

I 1

1 1 I

1 1

I I 1 /

1 ■ J J / /

1 1 1 1 1 1 f

1 1 1 I 1 1 1 1

1 1 1 1 ■

! I J ! ! I J ! 1

1

1 1 1 1 1

1

1 1

1

1

1

I 1 1

I f 1

1

1

1

I 1

1 1 1 1 1 1

1 ■ 1 f 1 . I

I I 1 1 I I

1 1 I

C I 1 I I 1 1 ! I ! 1 1 ! 1 ■ f I 1 1 1 I 1 ■

J 1 1 1 ■

1 1 1 1 1 1 1

ov 1.ov

V(1)

Figure 5.10 X-Y pattern of outputs V1 and V2

is

16

14

12

10

r 8

6

4

ON

0

0 2 4 6 II 10 12

R(Ki)

Figure 5.11 Frequency of oscillation variation with R(if R j = R2 = R)

D y

-1.o

-1. IJY

V(2)

131

5.3 Grounded components based voltage-mode quadrature oscillators using DDCC**

5.3.1 Circuits description

The proposed circuits of grounded components based voltage-mode quadrature

oscillators (VMQOs) using DDCC are shown in Fig. 5.12 (a)-(d). VMQOs are realized by using

a simple technique. The basic building blocks for this technique are a first order all-pass filter

section and an integrator. All the proposed circuits consist of two DDCCs, two grounded

capacitors, and three grounded resistors.

— vi Z+ y 1 z+ 0v02 Y2 UIICC(1) R1 Cr + Y2 DDCC(2) =C2

Ya _ L___y3 x x

Vol R2 R3

(a) VMQO-I

''1 Z+ Y1 Z+ Vol ~2 I)I)C.C(I) R1 C1 = y2DDCC(Z) =CS ~FJ w Y3

x

Vdl fR2 ga

(b) VMQO-II

0* The content is based on the author published papers P3.

132

vo2 IC2

(c) VMQO-III

Y 1 ti+

Y2 DDC((1) R1

Y3 x

R2

Y1 Z+ V02

_ Y2 DDCC(2) 1C2 1 x

of R3

(d) VMQO-IV

Figure 5.12 Proposed circuits of VMQOs

The characteristic equation of the circuits of Fig. 5.12 (a)-(d) is given as

sZ +s —R, — 1 + 2R—R2 =0 C,R,R2 CARS C1C2 R,R,R3

The frequency of oscillation and the condition of oscillation can be obtained as:

1 l F0: fo=- 2

21r CC2R1R2R3

Rz — Ri e 1 Co. CIR1Rz C2R3

(5.15)

(5.16)

(5.17)

133

The two quadrature voltage outputs (Vol and Vol) of the proposed circuits, depicted in Fig. 5.13,

are related as

Vol = jrnC2R3Vo2 (5.18)

Equation (5.18) shows that the proposed circuits are capable to realize two quadrature voltage

outputs.

Vol

Figure 5.13 Phasor Diagram depicting quadrature voltage outputs


The VMQOs of Fig. 5.12 (a)-(d) are reanalyzed using equation (2.4) (non-ideal

equation of DDCC), thus characteristic equation becomes as:

VMQO-I:

s2 E(Rl -«LQ<< ) ]+ a, [(a 812/~R,+a„3 1Q,~)- z ] _ (5.19) CPR, G,R, C1C,1 R,J

VMQO-1I:

+5 ( -aQ)_aQ P a.[(a1 /3, flR +aJ/H4B lRl)-/3 R,]u _ (5.20) L CAA RR C. I C1C,R1R2R,

VMQO-III:

s2~-sL~ -a (5.21) ~.AJJ c1 CICAAR

VMQO-IV:

2 +s [(1-aka,sR,)a,/l + a~[(a,~~AA+a,~f23R1)-Q»I] =o (5.22) GR1P, G J CC R R2R,

134

The modified frequency of oscillation and condition of oscillation are given as:

VMQO-I

F0. _ 1 a2 [(a /3 R +afi1/ z]) -f=1Rj (5.23) 0 2x C1"R1R3

CO: (R -a )G~ S /3c~ (5.24)

VMQO-il

FO: f =— a=~(aQ~s +a~Au~)-~b~ ] (5.25)

fo -21r C,C2] A

CO: (R, - aA ) C2R, ~ az1323C,R,R2 (5.26)

VMQO-lII

FO: 1 a, [(af~~A +a,f R1)-tR] (5.27) f0 =-

21r C.CZRR2IR

CO: (R, -a 3 )C, a,/3zCRR, (5.28)

VMQO-IV

FO: 1 aL(a z ,1 +a )~flR2] (5.29)

f0=- 2,r C,C,ARR,

CO: (R, -aj ,R,)CZ1 5 a2 /i,C,R,R, (5.30)

It is to be further observed from equations (5.23)-(5.30) that the tracking errors may slightly

change the frequency of oscillation and condition of oscillation.

5.3.3 Parasitic Study


effects. As the X terminal of the DDCC (1) and DDCC (2) are connected to a resistor, the

parasitic resistance at the X terminal of the DDCC (Rx) can be absorbed as a part of the main

resistance. As the value of Rx1 and Rx2 is much smaller than the external resistors, so frequency

of oscillation of the proposed circuits of VMQOs will not be affected. The effects of the

135

capacitors at port Y and Z of the DDCC are also negligible because these capacitors are quite

small (and process dependent) as compared to the external capacitors. However, the effective

values of the capacitors after parasitic's inclusion is given below

VMQO-I:

C1 (effective) = C1 + CY23 + Czi + Cy11, C2 (effective) = C2+ Cz2+ Cy12+ Cy21 (5.31)

VMQO-II:

C1 (effective) = C1 + CY21 + CZ1 + Cv11, C2 (effective) = C2 + Cz2 + CY23 + CY12 (5.32)

VMQO-III:

C1 (effective) = C1 + CY23 + C'zt + Cy 13 , C2 (effective) = C2+ CZ2 + CY12 + CY21 (5.33)

VMQO-IV:

C (effective) = C1 + CY21 + CZ1 + Cy 13, C2 (effective) = C2 + CZ2 + CY23 + CY12 (5.34)

From equations (5.31)-(5.34), it is clear that the parasitic capacitances appear in shunt with

external capacitors thus ensuring a possibility of pre-distorting the designed values. Therefore it

is to be concluded that the circuits are not adversely affected by the parasitic capacitances and X-

terminal resistances.


The proposed VMQO circuit configurations were verified using PSPNCE

simulation. The VMQO-I was designed with C1 = C2 = 5pF, RI = 1KS~, R2 = 1.5KS , Rs = 3Kf2,

for the oscillation frequency of fo = 10.61MHz. The simulation results show an oscillation

frequency of 10.25MHz that closely matches the designed frequency. The simulated waveforms

of two quadrature voltage outputs are shown in Fig. 5.14. Fig. 5.15 shows the simulated

frequency spectrums of V01 and V02. The X-Y pattern of two outputs Vo I and Vol is given in

Fig. 5. l6 which shows and verifies the quadrature relationship. Furthermore, The FO is found to

vary from I.IMHz to 10.61MHz for single resistance (R1) control with variation from IOKSZ to

1KS respectively. The result of theoretical and simulated frequency control is given in Fig. 5.17.

The THD of the proposed circuit at all outputs is within 0.8%, which is low.

136

-10 OmV ' 03

v V (2)

10 OiaV-

0v ii1i&t:'w sons 100ns 150ns 200ns V(5)

Time

Figure 5.14 Quadrature output waveforms

250ns 300ns

8 OmV

4 OmV

w-- ----. _•••U _—.----_-_ --I. Ekilill 20MHz 40MHz 60MHZ SOMHZ 1IJUMI-IZ 1IJ1LUZ

V(5) Frequency

Figure 5.15 Frequency spectrum of outputs Vo l and V02

ov 0Hz

v V(2)

137

-50mV-

-80mV -80mV

v V(2)

50mV-

BOmV-

ov.

-40mV OV 4OmV 80mV

V(5)

Figure 5.16 X-Y pattern of outputs Vol and Vol

12

10

8

6

0

4

2

0

0 5 10

0 Theortical Values

——Simulated Values

R1(Kn)

Figure 5.17 Frequency of oscillation variation with Rl

5.4 Voltage-mode quadrature oscillator using DXCC-ll


Another quadrature oscillator is realized using the first order all-pass filter (Filter I

of Table 4.1) along with an integrator as shown in Fig. 5.18. The realization of integrator using

DXCC-II does not need X- and Z- stages. Therefore, the circuit of Fig. 5.18 does not show X-

TT The content is based on the author published papers Pi.

138

and Z- stages in the DXCC-II (2). The circuit configuration is thus simplified as several

transistors (namely: M3, M6 — Miff, M13 — M[4, M15 — M20 in Fig. 2.52) can be eliminated from the

actual implementation of DXCC-II (2) used in realizing the integrator block.

C2

C1

Figure 5.18 Voltage-mode quadrature oscillator

The characteristic equation of the quadrature oscillator is given as:

2 Z 1 1 _Q

(5.35) s + s( CIR1 C2R2 CiC2R1R2

The frequency of oscillation (FO) and condition of oscillation (CO) are given as:

FO: f =1 (5.36) ° 2ff 1ECzIR2k

CO: RiC1 ? R2C2 (5.37)

The circuit of Fig. 5.18 provides quadrature voltage outputs in form of Vol and Vol. The two

outputs are related as Vol = sR2C2Vo2, thus exhibiting the quadrature relationship at the

frequency of oscillation. An interesting extension of the quadrature oscillator of Fig. 5.18 is

further possible if X- stage is retained in the DXCCII-2; Z- stage can still be suppressed. A third

output would then be available at the X- of DXCCII-2, which is inverted version of Vol. It may

further be noted that the fourth output is already accessible at the X- terminal of DXCCII-1,

which is an inverted version of Vol. The circuit can thus be called a four phase quadrature

oscillator.


The non ideal characteristic equation for quadrature oscillator of Fig. 5.18 is given as:

p Z an + apfipfin(c +l) =0(5.38)

(ap+l)CiRi C2R2 CIC2RIR2(ap+l)

139

-2 0 QrnV , Os D V(6)

200mV-

ay. •1AI1 tWiUWt--WI'I"3PaU

0.2us 0.4us 0. bus o. Bu.s 1. ous o V(7)

The non ideal frequency of oscillation and condition of oscillation respectively becomes

FO: = apfpfln an+1

5.34 ° 27c C~C2RIR2(ap + 1) { )

Lrn + 1 < /3P aP r5 .0 L ) (ap+1)CiR i C2R2

Here, PP is the voltage transfer gain from Y terminal to the X+ terminal of DXCC-II and 0„ is the

voltage transfer gain from Y terminal to the X- terminal of DXCC-II. aP is the current transfer

gain from the X+ terminal to Z+ terminal of DXCC-II and cs„ is the current transfer gain from the

X- terminal to Z- terminal of DXCC-II.

The sensitivity figures for frequency of oscillation are given as follows:

S = i/((,+ l), S '° =a/(a+1), o =0.5, S O =0.5 (5.41) I )

p ,n ►" P ~n The sensitivity figures for the proposed circuit are all less than unity in magnitude which implies

good sensitivity performance.


Next the quadrature oscillator circuit is designed with C1=C2=lOpF, R1=4.651U1

and R2=4.4KSi Designed frequency of oscillation (FO) is 4MHz, where as the observed FO is

3.99MHz, which is in error by 0.5% only. The time domain waveforms for quadrature voltage

outputs are shown in Fig. 5.19 that verifies the proposed circuit and its Fourier spectrum is

shown in Fig. 5.20. The THD is found to be 1.2%.

Time Figure 5.19 Quadrature voltage outputs at 4MHz

15 OinV

100m

50m\

i t -

1 1 2

)Hz 10NHz 20MHz 30MHz o V(6) o V(7)

Frequency

Figure 5.20 Fourier spectrums of oscillator outputs

5.5 Voltage-mode oscillator using DXCC-111 5.5.1 Proposed circuit

In this section, a voltage-mode oscillator producing two voltage outputs is given. The

circuit is shown in Fig. 5.21; it consists of a second order voltage-mode all-pass filter and a unity

gain inverter, with the output of the inverter fed back to the input of the first stage. It may be

noted that the inverter (gain = -1) is realized using DXCC-II itself with input and output at Y and

X-, respectively. The system loop gain (defined Vow / VIN, Fig. 5.21) is given by

V0 ( s) (_ 1) s2 LC1 R2 — 2sL + 2R2 (5.42)

Y IN (s) S 2 L sim CA + 2 SLsim + 2 2

If loop gain is set to unity at s = juo, the circuit shown in Fig. 5.21 can be set to provide two

sinusoidal voltage outputs with frequency of oscillation as:

Jo I 2 — 2)c L C sim 3

(5.43)

Sensitivity figures for oscillation frequency are given as follows:

Sf. =SL°m =-!,S) =0 (5.44)

Equations (5.44) shows that the sensitivity figures for the proposed circuit are found to be less

than unity in magnitude which implies good sensitivity performance.

The content is based on the author published papers Ps.

141

The circuit provides two voltage outputs (Vol and Vol) as depicted in Fig. 5.21.

OUT

Vol

V02

Figure 5.21 Proposed voltage-mode oscillator

It is a well known fact that real inductors are not used in integrated analog systems due to their

bulky size. Here, simulated floating inductor [109] is used in place of the inductor. The DXCC-II

based circuit [109] realizes a resistor less floating inductor, So it is now to be emphasized that

iriductance simulator value is as Lsim = (C/gmlgm2), where grill & gm2 are transconductance of

transistors used in simulated inductor, which can be controlled by the gate voltages of those

transistors [109]. Here, gm; (i=l, 2) is the transconductance of the ith MOS transistor and is given

as:

gnti = 2pC0x W (Vs, — JTr ), where, i = 1, 2 (5.45)

By substituting the value of Ls;m in equation (5.42), the system Ioop gain (defined Vour I Vim,

Fig. 5.21) becomes

Vour(s') _ (l) s2CCIR2 —2sC+2R2g.192 (5.46) V/N (s) S21. C3R2 +2sC + 2R~gmlgm2

If loop gain is set to unity at s = jw, the circuit shown in Fig. 5.21 can be set to provide two


I;, 2~F~3ne2

(5.47)

Sensitivity figures for frequency of oscillation are given as follows: S f~ __ _S O — —Sf° — — 5. ° —0 (5.48) 91,9.2 C3 C 2, z

142

All the sensitivity figures given in equations (5.48) are less than unity in magnitude, which

suggests good sensitivity performance.


By using the non-ideal equation of DXCC-II (equation (2.9)), the system loop gain

(defined VoUT / V1N , Fig. 5.21) is given by

V0 (s) _ ( _1) ,sla p 6pLsr,nC,R2 — sL;Qn(1+an)+R2/p(1+ap) (5.49)

VIN (S) s2L8.R C3R2 +SLsrm (1+ Cen) + R2 (1+ ap)

If loop gain is set to unity at s = jca, the circuit shown in Fig. 5.21 can be set to provide two

voltage outputs with frequency of oscillation as:

1 /1+ap

f°-2rc C~- 3 sum

(5.50)

Active and passive sensitivity figures for oscillation frequency are given in equations (5.49).

Sf° -Sf° --1 ,Sf° =O,Sf° = a~ Sf° =0 (5.51) C3 ~'sirn 2 a

2(l + a p )

The sensitivity figures are all less than unity in magnitude which implies good sensitivity

performance.


The oscillator circuit of Fig. 5.21 is designed with C,=C3=1 OpF, R2=20KSn and for the

resistor less floating simulated inductor, the dimensions of the NMOS transistors are

WIL=2.tm10.5 zm. The bias voltages are selected to be 0.78V so that to obtain a resistance of

20KEI across each one of the MOS transistor. The capacitance C is set to lOpF so that to realize a

floating inductance of 1 mH. Designed frequency of oscillation (FO) is 2.25 MHz, where as the

observed FO is 2.23 MHz, which is in error by 0.8% only. The time domain waveforms for

quadrature voltage outputs are shown in Fig. 5.22 that verifies the proposed circuit and its

Fourier spectrum is shown in Fig. 5.23. The THD is found to be 0.8%.

143

-l.oV Os o V(2)

1. 0V

oV.

Vol Vol

+ V(5) Time

Figure 5.22 Two voltage outputs at 2.23 MHz

O.5us 1. Ous

5 00mV

25OrnV

0V 0Hz

o V (2) 20MHz 40MHz 60MHZ BOHHZ

+ V(5) Frequency

Figure 5.23 Fourier spectrums of oscillator outputs

5.6 Mixed-mode quadrature oscillator using DVCC56


The proposed circuit of second order mixed-mode quadrature oscillator is shown in

Fig. 5.24. It is composed of two DVCCs, two grounded capacitors and two grounded resistors.

u The content is based on the author published papers P6.

144

Y2 Yi Y2 Z+ ]

DtiCC(1) DVCC(2) Z+ -J

V2NRI

Z+ V, Y I X Z— I2

C 1 R2 Ca

Figure 5.24 Proposed circuit of second order quadrature oscillator


S' + s (C1R1 -

C1R2) 1 + = 0 (5.52)

C1C2R,R2 C1C2R1 R2

The frequency of oscillation (FO) and condition of oscillation (CO) can be obtained as

FO: f — 1

(5.53) ° 2 rjC1C2R,R,

CO: R, <_ R z (5.54)

The various voltage and current outputs depicted in Fig. 5.25 are related as

V2 = —( jrwC1R, )V (5.55)

13 = ( J oC2Rl )l 11, = —12 (5.56)


(5.57).

fo 1 (5.57)

C,IC2 ,R,,R2 y — 2

Equation (5.57) shows that all the sensitivity figures are less than unity in magnitude, which is a

good feature of the proposed circuit.

r

145

I3

12 Ii

(a)

v,

V2

(b)

Figure 5.25 (a) Phasor diagram depicting quadrature current outputs (b) Phasor diagram

depicting quadrature voltage outputs


The second order mixed-mode quadrature oscillator of Fig. 5.24 is reanalyzed

using equation (2.2) (non-ideal equation of DVCC), so as to get modified characteristic equation

as:

S2 +s (C,R, +a]#12C2R2(1-a2f22) -alfl11C1 R2) + a1N12 =0 (5.58)

C1 C2 R1 R2 C1C,R1 R2

The modified frequency of oscillation and condition of oscillation are

1 Faiz2n 2R,R, (5.59)

CO:C,R1 ~ a,,6,,C,R 2 —a1fl,2 C2 R,(1—a2,622 ) (5.60)

Here, 011, X312 are the voltage transfer gains from Y1, Y2 terminals respectively to the X terminal

of DVCCI and (022 is the voltage transfer gain from Y2 terminal to the X terminal of DVCC2. i1

is the current transfer gain from the X terminal to Z+ terminal of DVCC C and a2 is the current

146

transfer gain from the X terminal to Z- terminal of DVCC2. The active and passive sensitivities

are shown in equation (5.61).

1 ay , fi12 ~~CC ,C2,Rt,R2 2

, sa2, P22 , fizz = 0 (5.61)


circuit of mixed-mode quadrature oscillator enjoys attractive active and passive sensitivity

performance.



effects. As the X terminal of the DVCCI , DVCC2 and DVCC 3 is connected to a resistor, the

parasitic resistance at the X terminal of the DVCC (Rx) can be absorbed as a part of the main

resistance. As the value of Rx1, Rx2 and Rx3 is much smaller then the external resistor (R), so

frequency of oscillation of the proposed circuit of mixed-mode quadrature oscillator will not be

affected. The effects of the capacitors at port Y and Z of the DVCC are also negligible because

these capacitors are quite small (and process dependent) as compared to the external capacitors.

However, the proposed circuit of quadrature oscillator is re-analyzed taking into account the

above parasitic effects. A re-analysis of the proposed circuit of quadrature oscillator yields:

As' +Bs+C = 0 (5.62)

where, A = CiRX2R~(ZZR r2 — Z2R' — Z1 RX,) B= C2R1(2Z,R~., — Z,R, -- Rl'R ., -- 2Z,R.r2 ) C = R1'(Z2 — RI') Where, R'1—R1+Rx1, Z1—(C1+CY12+CZl++CZ2+)11(RY12IIRZi+11Rz2+) and

Z2=R2 II (Cyr +CY22+Czi.++Cz2+) Il (RY II RY22 II Rzlf II Rz2+)

From equation (5.62), it is clear that the parasitic resistances and capacitances appear in shunt

with external capacitors, which are connected at Z terminals. Therefore, it is to be concluded that

the circuits are not adversely affected by the parasitic resistances and capacitances. Moreover,

from equation (5.62), it can be further observed that the parasitic resistances/capacitances merge

with the external value. Such a merger does cause slight deviation in circuit's parameters.

147

!12 13 € -Ii

W _ t

f j

- ~---i -.~.- ~~._~.~. .......M........~~_..- ._.... .._.....ham ... -a-~ ... _ ...... __ _ ... _

300ns 400ns 500ns 600ns 700ns I(C2► o I(vz3)

100uA-

aA

-10OUA 200ns

0 1{C1)


The proposed second order quadrature oscillator was next simulated using

PSPICE. The circuit was designed using equal capacitors of value C1= C2 = lOpF, Rt = 3.66M,

R2 = 4KSZ. The theoretical FO using this design was 4.15MHz. The simulated FO was found to

be 4.12MHz, which is very close to the theoretical value and only 0.72% in error. The results for

the three current outputs and two voltage outputs are shown in Fig. 5.26 and Fig. 5.27

respectively. The Fourier spectrum of the outputs of Fig. 5.26 and Fig. 5.28 are shown in Fig.

5.27 and Fig. 5.29, respectively. Each output enjoys a total harmonic distortion (TIC) of within

1%. To further support the circuit's practical utility, R (for RI = R2 = R) was varied so as to vary

the FO. The FO tuning through R is shown in Fig. 5.30. The FO is found to vary from 1.59MHz

to 15.92MHz for variation of R from lOKL1 to IKS2 respectively. Both theoretical and simulated

FO is found to closely match.

Time

Figure 5.26 Quadrature current output waveforms

148

4 OuA

GA-1

0Hz a 1(d)

i--Il 'lull. 10MHz 20MHz 30MHz 40MHz

I(C2) v I(vz3) Frequency

-40OiriV--- Os a

400mV

0v. dAb Vtfr!*& V(1) o V(2)

200ns 400ns 600ns

Figure 5.27 Frequency spectrums of current outputs

Time

Figure 5.28 Quadrature voltage output waveforms

149

9 8 7

N5 25 = 4 0

2 1 C

300mV

2 OOinV

10 OmV

-1--------=..----- h_—=

OFIz 10MHz 20MHz 30MHz 40MHz a V(1) o V(2)

Frequency

Figure 5.29 Frequency spectrums of outputs V1 and V2

--Theoretic&

—--Simulated

2 3 4 5 6 7 8 9 10 R in 1(0

Figure 5.30 Frequency of oscillation variation with R

5.7 Third order mixed-mode quadrature oscillator using DVCC""'


The proposed circuit of third order quadrature oscillator is shown in Fig. 5.31. It

is composed of three DVCCs, three grounded capacitors, and three resistors.


150

-1z+ Yl

X DVCC(3) Z— I3

R3 1 Y2 z+ I—+14

Y2 YI

DVCC(1) Z-- R3

Z+ x Z+ ~ 1 X DVCC (2) Z-f I1 C3

R1 T a YI Y2 Z— I2

Figure 5.31 Proposed circuit of third order mixed-mode quadrature oscillator


Z(C,R2+C,R,—CR,) 1 1 s +s +s + =0 (5.63)

C1 C2 R1R2 C,CZ R,RZ C1 C2C3R1 R2 R3

Replacing s = jco and equating real and imaginary terms, the above equation yields the frequency

of oscillation (FO) and condition of oscillation (CO) as

1 FO: fo = (5.64)

2;r C, C,R, R,

CO:C1C,R1 Rz = C3 R3 (C2 R2 +C1R1 —C1 R2 ) (5.65)

Assuming equal value resistors (R1=R2=R) and capacitors (C,=C2=C), the expressions of

equations (5.64) and (5.65) simplify to

FO: f = 1 (5.66) 2)rRC

CO: CR = C3 R3 (5.67)

The various voltage and current outputs depicted in Fig. 5.32 are related as

1 _ _(jo C2R1)V1 (5.68)

I, _ (jcoC3R3 )I3 ,I2 = (jcoC3R3 )I4 ,I1 = —12113 = —14 (5.69)

151

It is evident from equations (5.68) and (5.69) that all six outputs are obtained in quadrature form.

Two quadrature voltages in the form of V, and V2 with a phase shift of 900 are obtained. It is

quite worth noting that the voltage outputs unlike the available current outputs do not appear at

appropriate (low) impedance level. The four current outputs are available at desired high

impedance level and also exhibit a quadrature relationship. Four quadrature current outputs in the

form of I1, I2, I3 and Ia with a progressive phase shift of 90° are obtained. The various outputs

generated have equal amplitudes.

II

14 I3

I2

(a)

vi

V2

(b)

Figure 5.32 (a) Phasor diagram depicting quadrature current outputs (b) Phasor diagram

depicting quadrature voltage outputs

r

152


(5.70).

fo s — -- (5.70) CV'C25R1>~

1

2

Equation (5.70) shows that all the sensitivity figures are Iess than unity in magnitude.

5.7 2 Non-ideal analysis

The third order quadrature oscillator of Fig. 5.31 is reanalyzed using equation

(2.2) (non-ideal equation of DVCC) so as to obtain the characteristic equation as:

3 2 (a1/12C2 R 2 +CI RI -a11311C1l2)

+ _l~lz a1a2a3fl12 fi31 s +s

CC RR +s CCRR CCCRRR —0 (5.71)

l 2 l 2 1 2 l 2 1 2 3 1 2 3

The modified frequency of oscillation and condition of oscillation are

FO: f0 = 1 1 JQl'"

(5.72) lac C1C2RR2

CO:a,a3N31CI C2R1 R2 = C3R3`a1!'12C2R2 +CI R1 -al!'12C1R2) (5.73)

Here, P11, vi42 are the voltage transfer gains from Y1, Y2 terminal respectively to the X terminal of

DVCCI and f331 is the voltage transfer gain from Yl terminal respectively to the X terminal of

DVCC3. al is the current transfer gain from the X terminal to Z+ terminal of DVCC1, a2 is the

current transfer gain from the X terminal to Z- terminal of DVCC2 and cy is the current transfer

gain from the X terminal to Z+ terminal of DVCC3. The active and passive sensitivities are given

in equation (534).

sf" — —s f 1 ° ]~ p

a1 , #12 - C,,C2,Rl,R2 2 (5.74)


circuit of third order quadrature oscillator enjoys attractive active and passive sensitivity

performance. It can be further observed from equation (5.72) and (5.73), the non-idealities

slightly change the frequency of oscillation and condition of oscillation.



effects. As the X terminal of the DVCC1 , DVCC2 and DVCC3 is connected to a resistor, the

153

parasitic resistance at the X terminal of the DVCC (RX) can be absorbed as a part of the main

resistance. As the value of Rx1, Rx1 and Rx3 is much smaller then the external resistor (R), so

frequency of oscillation of the proposed circuit of third order quadrature oscillator will be

slightly affected. The effects of the capacitors at port Y and Z of the DVCC are also negligible

because these capacitors are quite small (and process dependent) as compared to the external

capacitors. However, the proposed circuit of quadrature oscillator is re-analyzed taking into

account the above parasitic effects. A re-analysis of the proposed circuit of quadrature oscillator

yields:

s3a+s2b+sc+d =0 (5.75)

where, a_R'Rr,R,,,Rj'2R2'R3'(C i+C')(C2+C'r) (C3+Cfr1)

b=R1'R2'R3'[R'R"R1'(C 1+C')(C2+C,r)+R„R.,.R1'(C2+C„)(C3+C")+R'R"R1'(C1+C')(C3+C"►)+R'

Rr"R rrr(C2+C,r) (C3} C,rr)I+R'R,."R3'rR,"R 1'2(C 1+C')(C3+C"►)+R2'(C i+C 7(C3+C,.,)

c=R l,R2'R3' [R'R '̀(C,+C')+R"RI'(C2+C")+R"R,'(C3+C ")+R,R„(C, +C')+R'R"(C2+C ")+R'R,r,(C3

+Crrr)+RrrRrrr(C3+C`)]+R"RI'R3'[R'Rl '(C1 +C')+R" FRS 1(C3+Crrr)+RlRr1r(C3+Crrr)]

d=R1'[R"R1 'R3'+R1'R2'R31+R,RrrR3 r+RrR2rR3r+RrRrRur+RruRR?R3r]

where, R' = Rz1~+Rv12+RZ3+, R" = Rz1++Ry11, R" R+ R 31 and R1' = R1+Rxl, R2' = R2+RXZ,

R3' = R3+Rx3, and C' = Cz1++CY l2+CZ3+, C” = CZI++CYI1, Cirr = Z2- '-'Y31 C.

From equation (5.75), it is clear that the parasitic resistances and capacitances appear in shunt

with external capacitors, which are connected at Z terminals. Therefore, it is to be concluded that

the circuits are not adversely affected by the parasitic resistances and capacitances. Moreover,

from equation (5.75), it can be further observed that the parasitic resistances/capacitances merge

with the external value. Such a merger does cause slight deviation in circuit's parameters.


The proposed third order quadrature oscillator was next simulated using PSPICE.

The circuit was designed using equal capacitors of value Ci = C2 = C3 = 5pF, R1 = R2 = R3 =

4kCl,. The theoretical FO using this design was 7.96MHz. The simulated FO was found to be 7.94

154

-400 400ns

u I(C3)

40OuA•

0A- ii.i1. 450ns 500ns 550ns 600ns

o I(vzl) n I(vz4) o I(vz3) Time

MHz, which is very close to the theoretical value and only 0.25% in error. The results for the

four current outputs and two voltage outputs are shown in Fig. 5.33 and Fig. 5.35 respectively.

The Fourier spectrum of the outputs of Fig. 5.33 and Fig. 5.35 are shown in Fig. 5.34 and Fig.

5.36 respectively. The THD at various outputs is listed in Table 5.1.

Table 5.1: % THD for current and voltage outputs

Outputs Il I2 I3 I4 VI V2

% THD 1.82 1.16 0.53 0.58 1.34 0.84

To further support the circuit's practical utility, R (for R l = R2 = R) was varied so as to vary the

FO. The FO tuning through R is shown in Fig. 5.37. The FO is found to vary from 3.18MHz to

10.62MHz for variation of R from 10Kf to 3K.Q respectively. Both theoretical and simulated

FO is found to closely match.

Figure 5.33 Quadrature current output waveforms

155

10 UuA-

- --- ---- -

0Hz 50MHz 100MHz 150MHz o I (C3) o I (vzl) v I(vz4) a I(vz3)

Frequency

Figure 5.34 Frequency spectrums of current outputs

Ilk 40

~~M -- I I I

500ns 600rxs 700ns 800ns + V (2)

Time

Figure 5.35 Quadrature voltage output waveforms

2. OV-

cv-

-2.OV-1 400ns

0 V (1)

156

800mV•

4 00mV•

OV 0Hz

o V(1) o V(2)

1 -

50MHz 7.00MHz 150MHz

Frequency

Figure 5.36 Frequency spectrums of voltage outputs

12

10

N 8

—4—Zheoretica!

f5irnulated

2

3 4 5 6 7 8 9 10

RinKfl

Figure 5.37 Frequency of oscillation variation with R (for R, = R2 =R)

5.7.5 Circuit enhancement

Next, a new application of the proposed third order quadrature oscillators in clock

generation is given. A four phase clock (V.1k, Valk, Vcllk and Vd~Ik) along with two sine

waveforms (V lst and V21) is generated by using the proposed circuit of oscillator (Fig. 5.31).

The block diagram representation is shown in Fig. 5.38. For generation of four phase clocks, four

voltage outputs are taken instead of four current outputs (as shown in Fig. 5.31) at the Z

terminals of DVCC2 and DVCC3. The four-phase clock voltage outputs are at a progressive

phase shift of 900. Note that the Z terminals exhibit a high output resistance, sufficient to saturate

157

the DVCCs. The output levels depend on the supply voltage (Voo and Vss). No additional

resistors are being used, thus the new scheme is compatible with monolithic implementation. The

results of four phase clock are shown in Fig. 5.39 and very well justify this new application.

VDD

v1 OVa fl: Circuit as

bclk Sine/Clock v2 Generator vcc

4tk

Vss

Figure 538 Proposed circuit as Sine/Clock generator 4.0'

0\

-4.0~ o V(13)

4.OV OV

-4.OV ❑ V(10)

4.OV-~-

-4.OV' _ v V(11)

4.OV

SEL>> -4.OV

Os 0.5us 1.Ous ❑ V(9)

Time

Figure 5.39 Four phase clock wave shapes

5.8 Conclusion

Several oscillators are presented in this chapter. Most of the proposed circuits are simple

and contain a minimum number of components required to achieve quadrature oscillations or

multi phase oscillations. First, six new circuits of oscillators using DDCCs are presented. All the

circuits enjoy the feature of high input impedance and low output impedance. Next, two novel

circuits of oscillators using DXCC-I1 are presented. Both the circuits consist of two DXCC-IIs as

active elements. Furthermore, a new mixed-mode second order quadrature oscillator circuit

158

based on two DVCCs as active element, two grounded capacitors and two grounded resistors is

given. The circuit employs all grounded components, idea[ for IC implementation. The circuit

provides two quadrature voltages and three current outputs. The circuit also enjoys the feature of

low THD. Non-ideal analysis and parasitic study is also given. Furthermore, a new third order

mixed-mode quadrature oscillator circuit based on three DVCCs as active element, three

grounded capacitors and three resistors is also presented. The circuit provides both quadrature

voltage and current outputs. The enhancement of proposed circuit as sine/clock generator is

further given. The comparison of all the proposed circuits of this chapter is given in Table 5.2.

Table 5.2: Comparison of proposed oscillators

Features Fig. 5.2 Fig. 5.6 Fig. 5.12 Fig. 5.18 Fig. 5.21 Fig. 5.24 Fig. 5.31

Mode of Voltage Voltage Voltage Voltage Voltage Mixed Mixed Operation Number of Four Two Two Two Two Two Three

active elements Number of Two Two Three Two Two Two Two

resistors Number of Two Two Two Two Two Two Three capacitors Quadrature Three Two Two Two Two Two Two

voltage outputs Quadrature None None None None None Three Four

current out uts Designed 1.58MHz 1.59MHz 10.61 MHz 4MHz 2.25MHz 4.15MHz 7.96MHz

frequency of oscillation

Other elements No No No No One No No (if any) Simulated

Inductor Order of Second Second Second Second Second Second Third Oscillator

Type of active DDCC DDCC DDCC DXCCII DXCCII DVCC DVCC element

All the circuits enjoy the feature of low active and passive sensitivities. Non-ideal

analysis for all the circuits is also given. PSPICE simulations support the validity and practical

utility of all the proposed circuits.

159

CHAPTER 6 INTEGRATION AND TUNING ASPECTS

The integration and tuning aspects of the proposed circuits are next explored. As far as the active

elements are concerned, its implementation in CMOS technology is available. The passive

elements in form of resistors and capacitors should also be made compatible in CMOS

technology [152-156]. The resistors can be replaced by active-MOS resistors with added

advantage of tunability through external voltage [156-157]. Similarly, there are several

techniques for implementing capacitors in MOS technology [115].

This chapter discusses the fabrication possibilities of the passive elements, namely

resistor and capacitor. The filter and oscillator circuits proposed in the preceding Chapters are

not tunable. The proposed circuits can be made tunable by employing tunable passive elements.

This is achieved by using voltage controlled resistors that can be implemented using MOS

transistors. This give rise to which are termed as tunable filter and oscillator circuits. Some case

studies are further presented in this chapter whereas tunability aspects of some of the circuits are

studied.

6.1 Resistors

This section discusses the fabrication possibilities of the resistor [152-155]. By utilizing

the bulk resistivity of one of the transistor region, resistors in monolithic integrated circuits are

obtained. The most common technique in bipolar technology is to use "base diffused" or

"emitter diffused" resistor. The range of value for base diffused resistor is 2052 to 30K2 and for

emitter diffused resistor is 1052 to lks2, which is depend upon the size of the chip area. For

minimum width the ratio tolerance is -2 /o with nominal value as high as Z20 %. Another option

to the designer is the ion implanted resistors whose matching tolerance is improved and value is

almost comparable to base diffused resistor. The sheet resistance of collector epitaxial resistor is

greater than that of base diffusion that's why it gives high valued resistors known as epitaxial

resistors.

As for the resistors compatible with the MOS technology include diffusion, poly-silicon

and n-well (or p-well) resistors. Diffused resistors can be made from various diffusion regions as

shown in Fig. 6.1 (a). Different diffusion regions have different resistivity. An n-well resistor is

160

made up of a strip of n-wells contacted at both ends with n" source/drain diffusion as shown in

Fig. 6.1 (b). This is analogous to the epitaxial resistor in bipolar technology, however the

tolerances are poor. The n-well is usually used for medium-value resistors, while the n+ and p+

diffusions are useful for Iow-value resistors. The actual resistance value can be defined by

changing the length and width of diffused regions. The tolerance of the resistor value is very

poor (20 — 50%), but the matching ratio value of two resistors is quite good (5%).

0

muoon p-substrate

(a)

n-well

p-substrate

(b)

p-substrate

(c)

Figure 6.1 Resistor structures (a) diffusion (b) n-well (c) poly-silicon

161

A poly-silicon resistor can be fabricated by placing the poly-silicon layer on top of thick-

silicon-dioxide as shown in Fig. 6.1 (c). The thin poly-silicon layer provides better surface area

matching and hence more accurate resistor ratios. Furthermore, the poly resistor is physically

separated from the substrate, resulting in much lower parasitic capacitance and voltage

coefficient.

Another type of resistor is the pinched-base resistor that can be used when a large resistor

value is required. The internal structure is shown in Fig. 6.2. In the internal structure, the p-base

region is encroached by the n+ diffusion, restricting the conduction path. It provides resistor

values in excess of 1OKSl with poor tolerance (--50% absolute) and temperature coefficients but

relatively good matching (--10% matching).

Figure 6.2 Pinched base resistor

6.2 Capacitors

Capacitors constitute the most natural element in MOS technology [152, 154, 155]. It is

to be employed in the fabrication of analog circuits in the range of O.lpF to 100pF. The MOS

capacitors may be fabricated through following techniques

(i). Poly-diffusion capacitors,

(ii). Poly-poly capacitors,

(iii). Metal-poly capacitors.

162

Poly

SiO2

p-substrate

(a)

Poly 2

oly 1

SiO2

p-substrate

(b)

Metal 1

"oly I

SiO2

p-substrate

(c)

Figure 6.3 Capacitor structures (a) poly-diffusion (b) poly-poly (c) metal-poly

163

The poly-diffusion capacitor is formed by using one of the interconnect layers (metal or

polysilicon) on top of crystalline silicon separated by a dielectric (silicon dioxide layer). Fig. 6.3

(a) shows a capacitor using polysilicon as the top conducting plate. A low-voltage-coefficient

capacitor can be achieved, if the bottom plate has heavily doped diffusion. To have this heavily

doped diffusion, an extra step is included prior to the deposition of the polysilicon layer. So the

mask defined implanted region becomes the bottom plate of the capacitor. The capacitance

achieved using this method is inversely proportional to gate oxide thickness.

The poly-poly type of capacitor is formed by providing additional polysilicon layer on

top of gate polysilicon (separated by a dielectric) as shown in Fig. 6.3 (b). The dielectric is

formed by a thin silicon dioxide layer, which can be produced by using several steps beyond the

usual single polysilicon process.

A third and less often used capacitor is constructed by putting an n-well underneath an n-

channel transistor as shown in Fig. 6.3 (c). It is similar to the poly-diffusion capacitor except that

its bottom plate (n-well) has a much higher resistivity. Because of this fact it is rarely used in

circuits, where a low voltage coefficient is important. Due to high capacitance per unit area, it

can be matched well and it is available in all CMOS processes since no unique steps or masks are

required. It is used, when one terminal of the capacitor is connected to ground.

The capacitance of MOS or junction capacitors is about 4E-04 pico-farads per square

micrometer. Most of the IC capacitors are typically less than 100 pF values in excess of 500 pF

have been obtained, at the expense of large chip area.

For poly-poly and MOS capacitors, the capacitance values can be controlled to within

1%. Practical capacitance values range from 0.5pF to a few tens of pico-farads. The matching

between similar size capacitors can be within 0.1%. This property is extremely useful for

designing precision analog CMOS circuits.

The parasitic capacitances are unavoidable when fabrication is made, it depends upon the

size and the technology used. The parasitic capacitances can range from 0.01 and 0.001 times the

desired value of the MOS capacitor. The effects may be reduced considerably through a proper

layout of the system.

6.3 Tunable resistors

A number of advantages can be achieved in implementing resistors with MOS transistors.

The techniques are given below

MOS voltage tonfroItedfloatirag resistor

The circuit of voltage controlled floating resistor employing four MOS transistors

is shown in Fig. 6.4 [156].

IT.,.-' VA

VB

Figure 6.4 Voltage controlled floating resistor [156]

The transistor M2 is biased so that it remains on. It is done by biasing M3 such that it operates

only in its ohmic region. The purpose of the diode connected transistor M1 is to drop the supply

voltages to a suitable value such that the condition of non-saturation for M3 is satisfied. To

further ensure that M3 will operate in a non-saturation region, its gate is connected to the gate of

M4 so that its Vos is large. The expression for the floating resistor between terminal voltages VA

and VB is shown in equation (6.1).

165

R— 1

K(Vc —V8 -2V,.)

There is an offset term given by

KxVT2 2

where,

W K= yCoxi

where,

p is the mobility of the carrier

Cox is the gate-oxide capacitance per unit area of the channel capacitor

Vc is the control voltage

VB is the terminal voltage

W is the channel width

L is the channel length

Vr is the threshold voltage for MOS transistor

CMOS trans-conductance based grounded resistor

The four transistors based simple linear, tunable CMOS implementation of a high

frequency trans-conductance element is shown in Fig. 6.5. With its output terminal connected to

the input terminal, it simulates a grounded resistor having value 1/gm [157]. The trans-

conductance value is given as:

gm =2XK ff [2xYG -Vr] (6.4)

where,

VT -. V.2 +V~.3 +IVTn I+IVT41 (6.5)

(6.1)

(6.2)

(6.3)

166

K =( + K

KN xKp (6.6)

where,

1 W KN.r = 2 x Cox x L ] (6.7)

VG3 tMI

M1

VIN vov-r

M2

VG4 O— l L M4

VSs

r Figure 6,5 CMOS trans-conductance based grounded resistor [157]

All the transistors are assumed to be operating in the saturation region. Moreover, the body effect

of all the transistors is assumed to be neglected. The equation (6.4) is valid for equal and

opposite gate voltages (VG) of M, and M2 transistors. Thus the circuit implements an ideal linear

voltage controlled trans-conductance.

> MOS voltage controlled grounded resistor

The MOS voltage controlled grounded resistor can be implemented by using two

MOS devices as shown in Fig. 6.6 [158J.

167

YTN

d}

TOUT

4Z

Vss Figure 6.6 MOS voltage controlled grounded resistor [158]

In the Fig. 6.6, transistors Mj and M2 are assumed to be the matched transistors. The transistors

are assumed to be operating at saturation. The source and bulk of each MOS are connected

together to avoid the body effect. An input current IIN is applied between a source of Ml and a

drain of M2, developing a voltage VOUT. The drain current flowing from M1 and M2 are given by

_K 2 'd i ) = 2 (VDD — VOUT — VT

'd(M,) ^ K

Z (VOUT —Vs YT)2

where,

W K=#Cox L

Using above equations (6.8) and (6.9) and applying KCL at terminal Your, we get

_'a(me) —Id(M1► ; I VOUT 2KVDT 2KVDT

where,

(6.10)

(6.11)

VDT` VDD — VT --(VSS+ VT); VDD^ — VSS (6.12)

(6.8)

(6.9)

168

r A linear current-to-voltage conversion is thus performed, which corresponds to a resistor_

R=Your= I = L 'IN 2KVDT P OXW(VDD -VT)

(6.13)

Here, the resistance R can be tuned electronically by changing Voo. Equation (6.13) is valid

when both M1 and M2 will be in the saturation region, which is true if IYouTI VDT.

6.4 Case studies

6.4. I Case study-I

> Voltage controlled all pass filter'

The circuit of all-pass filter (Fig. 3.1) is made tunable by removing the resistor

(R) and parasitic resistor at X terminal (Rx) is exploited in place of the external resistor (R). The

resulting circuit is shown in Fig. 6.7. Here Rx is controlled by a bias voltage (VBB) and hence the

circuit will be voltage controllable. The pole-frequency can be tuned by varying the bias voltage

of the active element.

Yl VC-DDCC1 X veal

Y2 Y3

Vin L VBB

Y1 VC-DDCC2 X

Y3 Y2 Ic

Figure 6.7 Proposed resistorless voltage controlled all pass filter

The content is based on the author published papers Pg.

169

❖ Circuit analysis

The circuit of Fig. 6.7 is analyzed for its transfer function as given below:

1 Vout — s RxC (6.14) vvn s + 1 KC

Equation (6.14) is the standard voltage transfer function for a first order all-pass filter with unity

gain and frequency dependent phase as L rp = 180 — 2 tan-' coRxC' . Here, Rx is the X terminal

parasitic resistance which depends on the biasing voltage VBe. Note that the proposed circuit

uses a single capacitor in grounded form, which is ideal for integration in MOS technology.

Moreover, no resistor is required, which also favors microminiaturization. The pole frequency of

the all-pass filter (oao 1IRxC) is controllable through bias voltage VBB. This feature is also a

desirable one for the circuit's feasibility in IC form. The circuit possesses low output resistance

as the output is at the X terminal, which shows a low resistance for practical values of VBB, as

will be evident during the simulations. Another feature to be noted is that both VC-DDCCs have

unused Z terminals. Therefore, these stages need not to be implemented when integrating the

circuit.

❖ Non-ideal analysis

The voltage controlled all-pass filter of Fig. 6.7 is reanalyzed using non-idealities

of VC-DDCC, thus transfer function becomes as:

912021 +p23)-p

out = X 11 (6.15) Vin s+ r 1

LRxC

Lrp

=180— tan-' mRYC fl12(pz1 +,23) (6.16)

)612(#21 + P23) -- fi11

170

Here, (3l 1, 1312 are the voltage transfer gains from YI, Y2 terminals respectively to the X terminal

of VC-DDCCI and P21, f are the voltage transfer gains from Y1, Y3 terminals respectively to

the X terminal of VC-DDCC2.

' Design and verification

The proposed voltage-controlled all-pass filter (Fig. 6.7) was designed with

C=lnF and VBB=--1.2V. The gain and phase plots are shown in Fig. 6.8 and Fig. 6.9 respectively,

where a pole frequency of 1.16MHz is obtained. This is close to the theoretical value of

1.17MHz as obtained from the Rx value from Fig. 6.12. Next, Fig. 6.10 shows that at the pole

frequency of 1.17MHz input/output waveforms are 900 phase shifted as expected. The Fourier

spectrum of the output is shown in Fig. 6.11. The poIe frequency control through the bias voltage

(VaH) is shown in Fig. 6.13. The pole frequency is found to vary over a moderate range with

VBB. This further confirms the practical utility of the proposed circuit.

40

G A 20 I N

2 0 N

d -20 B

-401 1.0Hz

n DB(V(4) /V(2)) 100Hz 10KHz 1.0MHz

Frequency

Figure 6.8 Gain plot of the proposed circuit

100MHz

171

1 1 1

~ 1

1 1

1 1 1 1

----------!----------

III"

1 1

1 1 I 1 1 !

1 1

I 1

1

1 1

: 1

1 1 1

1 1 1 .--------.L---------- ----------J.---••--••

•--- --...J------.---- .-- ..--.L.-..----.-

I I I

1 1 1

. 1 .

1

1 1 1 1 . 1 I

1 ,

100Hz 10I z 1.OHHz 100MHz

P 180d-

h a J

e

1

n 90d -

d e 4

Od 1.0Hz

o P(V(4))

21

-2i

Frequency

Figure 6.9 Phase plot of the proposed circuit

,1Ilu r 1

Vin out 1 1 I r ,

1 1 1 1 1

1 1 1

1 1 1 1 1

Ov 1 1 I 1

1 1 1 1 1 1 1 r

1 1 1 I I 1 ! 1 1 1 1 1 Y 1 1 1 1 1 1 1 1 1 1

----+-----r----•- ----r ---- •-•--•--- .r-..-- .r_-r..-- -----r----+ ----T----•----- 1

1 r 1 1 I 1 1 1 1 1 1 1

Os 1.Ous 2.0 us 3.Ous AV(4) v V(2)

Time

Figure 6-10 Input/output waveforms at pole frequency

172

5mV

OV 1

0Hz 10MHz 20MHz u V(4)

Frequency

Figure 6.11 Fourier spectrum of the output at 1.17MHz

4

3.5

3

= 2.5

2

1.5

1

0.5 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

-VBB (11)

Figure 6.12 Pole frequency variations with the bias voltage VBB

6.4.2 Case study-II

}> Proposed tunable all-pass filter

The circuit of first order all-pass filter (Fig. 3.7) is made tunable by replacing the

resistor with MOS equivalent resistor. The proposed tunable all-pass filter is shown in Fig. 6.13.

The floating resistor of Fig. 6.4 is employed in implementing a tunable all-pass filter. Here, R is

controlled by a control voltage. The cut off frequency can be programmed by varying R which in

173

Y

Dxc cu

CL1 X±1 VDD

VO M3 Mi

Lii fl

114 T M2

VC

Figure 6.13 Tunable all-pass filter using MOS resistor

+ Simulation results

The tunable all-pass filter is simulated and designed for C1=1 .5pF. The resistor R

is replaced by its MOS equivalent and controlled by a controlling voltage Vc ranging from 0.25V

to 2V at a fold of 2. The gain and phase plot for all-pass filter is shown in Fig 6.14 and 6.15

respectively. The input/output waveforms at Vc=2V is shown in Fig. 6.16. The Fourier spectrum

is shown in Fig 6.11. 20

G 10 A I

N 0 1 _11'•. ______ I N

d • 10- B

-20- 1.0Hz 100Hz 10KHz 1.0MHz 100MHz

a .. v DB(V(5)/V(1)) Frequency

Figure 6.14 Gain plot

174

-2 OOinV Os o V (1)

200inV-

ov. 2V

Z~~ '12 Z

o V(5) 0. 5us 1.Ous

150

P H 100 A S E

50

C I

• .. .. Wk___

.

.

•

.

~xlxkllkwk m

S . mak .:

mm~Wml

I d. ,Ji.jI. S)I. S Slul. + x A P(V(5))

Frequency

Figure 6.15 Phase plot

Time

Figure 6.16 Input/output waveforms of voltage-controlled all-pass filter at V=2V

175

OV 0Hz 10MHz 20MHz 30MHz 40MEiz

❑ V(1) o V(5) Frequency

Figure 6.17 Fourier spectrum at Vc =2V

6.4.3 Case study-III

> Proposed tunable quadrature oscillator

The circuit of quadrature oscillator (Fig. 5.18) is made tunable by replacing all the

resistors with MOS equivalent resistors. The resulting circuit of tunable oscillator is shown in

Fig. 6.18. Here, the value of resistors is controlled by control voltages. The output voltages are

remaining same as given in section 5.4. Since the resistor is replaced by MOS version therefore

the circuit is completely integrable and tunable.

z+ Y

x+ DXC CII-1 DXCCII-2 z+ w x- x+

IC2

1~1 ~i1 V02 -

ct

10OmV-

50mV-

Figure 6.18 Tunable oscillator

176

-200mV - - - Os ❑ V(6)

200mV-

Ov

o V(7) 0.5us 1.0us 1.5us 2.Ous

❖ Simulation results

The tunable circuit of quadrature oscillator is simulated and designed for C1=C2=

10.5pF. The two resistors are replaced by its MOS equivalent and controlled by controlling

voltages Vi and VCZ.. Fig. 6.19 shows the quadrature voltage outputs at a frequency of 1MHz

controlled by a controlling voltage of 2V. The Fourier spectrum is shown in Fig. 6.20. Table 6.1

shows the variation of frequency with respect to the Vci and Vc2 at constant value of capacitors

(10.5pF each).

Table 6.1: Variation of frequency of oscillation at different values of Vet and Vc2 at constant value of capacitors

Vi (V) Vc2 (V) Frequency of oscillation

0.22 0.25 0.125 0.43 0.5 0.25 0.68 0.75 0.375 0.9 1 0.5 1.86 2 1

Time

Figure 6.19 Quadrature voltage outputs

177

-20 OmV Os D V(6) o V(7)

20 OmV

0v. L 0.5us 1.Ous 1.5us 2.Ous

150mV

lOOmV-

5OutV

Ov. 0Hz

o V(6) * V(7)

------------

4MHz 8MHz 12MHz 16MHz

Time

Figure 6.19 Quadrature voltage outputs

Frequency

Figure 6.20 Fourier spectrum of oscillator outputs

6.4.4 Case study-IV

> Proposed digitally controlled tunable voltage-mode oscillatort

The content is based on the author communicated paper P11.

178

The circuit of voltage-mode oscillator (Fig. 5.21) is made tunable by using DC-

DXCC-I1 with buffered output (Fig. 2.72) as active element. The proposed digitally controlled

oscillator is shown in Fig. 6.21. Digital tunability in the proposed circuit is done with variable

current transfer gain (a.) and is controlled by digital control word. The system loop gain (defined

VoUT / VIN, Fig. 6.21) is given by

V0 (s) (_1) S 2LsmCiR2 —2sLsjm +2R2 (6.17)

V (s) s2Ls,.C31I +2sL + 2R2

If loop gain is set to unity at s = ja, the circuit shown in Fig. 6.21 can be set to provide two


1 2 f = tat L. C

(6.18) Sim 3

The circuit provides two voltage outputs (Vo, and Vat) as depicted in Fig. 6.21.

Vol

Digital Control Word

Figure 6.21 Proposed digitally controlled voltage-mode oscillator

It is now to be emphasized that inductance simulator value is as Lg jm = (C/gmigm2), where gmi &

gm2 are transconductance of transistors used in simulated inductor.

179

By substituting the value of Ls jm in equation (6.17), the system loop gain (defined Vau-r / VIN,

Fig. 6.21) becomes

V(s) =(-1) szCCI R2 —2sC+2R2gm1gm2 (6.19) V,5 ( S) s2CC3R2 + 2sC + 214gm1gm2

If loop gain is set to unity at s = jc~, the circuit shown in Fig. 6.21 can be set to provide two


1 2,r C3C

❖ Non-idea! analysis

(6.20)

Taking the non-idealities into account, the system loop gain (defined VouT / VIN,

Fig. 6.21) is given as:

Vovr(s) = (-1)y pflpsm,2 — sLsimf3 (1+an )+R2 fp(1+ap) (6.21)

s LSrmC3R2 +sLs„.(I+an )+RZ (1+ap )

If loop gain is set to unity at s = jw, the circuit shown in Fig. 6.21 can be set to provide two

voltage outputs with frequency of oscillation as:

I l+ap ~~ - 2n CL 3 Sim

(6.22)

It is now seen from equation (6.22) that the frequency of oscillation of the proposed oscillator is depending on current transfer gain (ar). Therefore, the frequency of oscillation is made

controllable with the variable current transfer gain (av), which depends on the digital control word.

4 Design and simulation The digitally controlled tunable voltage-mode oscillator is simulated and designed

for C1=C3= lOpF, R2=20KSZ and the resistor less floating simulated inductor of lmH. The frequency of oscillation is controlled by the variable current transfer gain (a,). The current

transfer gain (a.) is controlled digitally by the four bit control word [a3 a2 a, a0]. Therefore, the oscillations of the proposed circuit of voltage-mode oscillator are controlled digitally by the four

bit control word [a3 a2 at ao]. Digital control over the frequency of oscillation using the control word of the DC-DXCCII with buffered output (Fig. 2.72) is also explored. Towards this end, the

180

r

digital control parameter (ap) is varied for the DC-DXCCII with buffered output. The values of

frequency of oscillation obtained for various choices of control word are presented in Table 6.2.

Table 6.2: Variation of frequency of oscillation with control word

Control word [a3 a2 al aol Digital control parameter

(aP~

Frequency of oscillation

(Theoretical)

Frequency of oscillation

(Simulated) a3 a2 at

a°

0 0 0 1 1 2.25MHz 2.21MHz

0 0 1 1 2 2.75MHz 2.69MHz

0 1 1 1 3 3.18MHz 3.11MHz

I 1 1 1 4 3.55MHz 3.48MHz


The resistor in the preceding chapter can be implemented by poly-silicon or diffused

fabrication processes but the uncertainty due to fabrication and temperature variation contribute

20% or more. By using the M05 transistors the exact value of resistor can be fabricated and also

the feature of tunability is added to the existing circuits. Some case studies are also illustrated.

PSPICE simulations of the circuits are carried out to verify the theory.

181

CHAPTER 7

CONCLUSION AND FUTURE SCOPE

In the framework of this Thesis, it is clear that the main objectives and intentions set out in the

beginning of this Thesis have been achieved. This Chapter summarizes the work carried out

within this Thesis by providing an overview of the contributions made in each individual

Chapter. Suggestions and possible future aspects of research are pointed out towards the end of

this Chapter.

7.1 Contribution to the Knowledge

The target of this Thesis was to bring the contribution in the field of high performance

universal active elements for the analog signal processing circuits operated in current-mode or

voltage-mode or mixed-mode. In the last decade, current conveyors and its variation got a great

importance for realizing analog signal processing circuits. It is shown that current conveyors

have the potential to satisfy the requirements set out in analog signal processing. The popularity

of current conveyor is attributed to their simple circuitry, wider bandwidth, linearity and high

slew rate. In Chapter 1, brief history of current conveyors along with an introduction to its

variants is presented. Most of the used active elements in Thesis are differential type current

conveyors since the differential circuit improves the performance of analog systems in terms of

noise rejection, dynamic range over one order of magnitude through the cancellation of even

harmonics, as well as it suppresses the effect of coupling between various blocks.

In Chapter 2, the definition and implementation of high performance universal active

elements such as DVCC, DDCC, VC-DDCC, DXCC-II, DXCC-II with buffered output and

digitally controlled DXCC-II in CMOS technology are presented. Thereafter the Thesis has

concentrated on the design and implementation of new analog signal processing circuit

realizations using these active elements with compatibility for IC technologies.

Several first order all-pass sections are proposed in Chapter 3. Many of the proposed

circuits enjoy a minimum component count. All the proposed circuits possess desired

input/output impedance feature, low active and passive sensitivities and low THD. Non-ideality

effects on the circuit performance are found to have negligible effect. The designed and 182

simulated values of the filter parameters using PSPICE simulations are found to be well

matched. Finally, the hardware realization of a first order all-pass filter circuit is also presented.

In Chapter 4, a number of second order filters are proposed_ First, four second order

voltage-mode all-pass filter realizations are based on simulated inductor and frequency

transformation technique. All the four proposed circuits possess high input impedance and low

output impedance. Furthermore, a new second order current-mode biquad filter is presented. It is

very simple and contains a minimum number of components required to achieve a second order

transfer function. Three types of transfer functions are obtained simultaneously, without any

circuit modification. The new circuit is suited for high frequency operation. The last two circuits

of second order voltage-mode band-pass filters are also simple and contain a minimum number

of active components.

Several novel oscillator circuits are proposed in Chapter 5. Some of the proposed circuits

use optimum and minimum component count. Many of them enjoy non-interactive control of

frequency of oscillation and condition of oscillation. The effect of non-idealities on the circuit

performance is found to be negligible. All the circuits were verified using PSPICE simulation

with attractive results.

In Chapter 6, the integration possibility of the circuits is presented. All the circuits

presented in the preceding Chapters uses resistors either in grounded form or in floating form.

These resistors can be replaced by their active equivalents in MOS technology with the added

advantage of tunability through external control voltage. Some case studies are further presented

in this chapter wherein tunability aspects of some of the circuits are studied.

It is to be concluded that the Thesis has enhanced the existing knowledge on the

realization of analog signal processing circuits using universal active elements in form of

DVCC/DDCC, DXCC-II, along with the newly introduced universal active elements namely

buffered output DXCC-II and DC-DXCCII with buffered output. Critical studies of the

proposed active elements and the circuits built around those active elements, as well as the

circuits built around existing active elements is carried out in the work. Exhaustive simulation results using CMOS technology and a sample experimental result is included in support of the

proposed theory.

183

7.2 Suggestions for Future work

As we know, nothing is absolute and nothing ever comes to an end; likewise, the author

feels that there is always room for further work and domains for more explorations. In this

section some suggestions are presented as follows, which may facilitate further work.

❖ The IC implementation of the presented circuits is the most natural future problem.

•3 The new proposed universal active elements can also be employed for realizing several

other functions like a four-quadrant multiplier, equalizer, higher order filters etc.

❖ The devices designed within this Thesis were based on a minimum of 0.18µm CMOS

technology. The devices may further be redesigned using nanometer CMOS technology.

This would make the active elements based on these designs suitable for use in mobile

telephony applications thereby vastly increasing their versatility and acceptance.

❖ Another factor that has a negative effect on the maximum operating frequency is the

presence of active RC components within the design. However, designing of analog

processing circuits with no RC components presents a number of hurdles. An alternate

solution that could be explored is to redesign the proposed circuits in such a way that

only a single resistor (and no capacitor in series with this resistor) is connected to the X-

terminal of the used active elements. In addition, designs could be explored that avoid

connecting resistors to the Y and/or Z terminals of used active elements.

To sum up, there is still a lot of scope in analog signal processing area to exploit the

advantages of high performance universal active elements in the upcoming technologies for

further research.

184

REFERENCES

[1] C. Toumazou, F. J. Lidgey, D. G. Haigh, "Analogue IC Design: The Current-Mode

approach", Peter Peregrinus Limited, London, 1990.

[2] B. Wilson, "Recent developments in current mode circuits," IEE Proceedings Circuits,

Devices and Systems, vol. 137, pp. 63-67, 1990.

[3] M. A. Ibrahim, S. Minaei, H, Kuntman, "A 22.5 MHz current-mode KHN-biquad using

differential voltage current conveyor and grounded passive elements." International

Journal of Electronics and Communications (AEU), vol. 59, pp. 311-318, 2005.

[4] W. G. Jung, "Op-Amp applications", Analog Devices, ISBN 0-916550-26-5, 2002.

[5] L. T. Bruton, "Network transfer function using the concept of frequency dependent

negative resistance", IEEE Transactions on Circuit Theory, vol. CT-16. pp. 406-408,

1969.

[6] A. F. Flores, E. O. Cordero, D. Baez, L. Ramirez, J. M. Ramirez, "Analysis of active

networks containing current feedback operational amplifiers", Communications

Computer & Signal Processing Proceeding IEEE Pacific Conference, pp. 261-263, 1995.

[7] P. A. Martinez, J. Sabadell, C. Aldea, "Grounded resistor controlled sinusoidal oscillator

using CFOAs", Electronics Letters, vol. 33, pp. 346-348, 1997.

[8] A. Sedra, K. C. Smith, "The current conveyor: A new circuit building block", IEEE

Proceedings, vol. 56, pp. 1368-1369, 1968.

[9] A. Toker, S. Ozoguz, C. Oguzhan, C. Acar, "Current-mode all-pass filters using current

differencing buffered amplifier and a new high-Q band-pass filter configuration", IEEE

Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47,

pp. 949-954, 2000.

[10] A. Fabre, "Third-generation current conveyor: A new helpful active element",

Electronics Letters, vol. 31, pp. 338-339, 1995.

[11] I. A. Awad, A. M. Soliman, "Inverting second generation current conveyors: the missing

building blocks, CMOS realizations and applications", International Journal of

Electronics, vol. 86, pp. 413-443, 1999.

185

[12] A. S. Sedra, K. C. Smith, "A second generation current conveyor and its application",

IEEE Transactions on Circuit Theory, vol. CT-17, pp. 132-134, 1970.

[13] H. O. Elwan, A. M. Soliman, "Novel CMOS differential voltage current conveyor and its

applications", IEE Proceedings Circuits Devices Systems, vol. 144, pp. 195-200, 1997.

[14] W. Chin, S. I. Liu, "CMOS differential difference current conveyors and their

applications", IEE Proceedings Circuits Devices Systems, vol. 143, pp. 91-96, 1996.

[15] S. Maheshwari, "A canonical voltage-controlled VM-APS with a grounded capacitor",

Circuits Systems Signal Processing, vol. 27, pp. 123-132, 2008.

[16] A. Zeki, A. Taker, "The dual-X current conveyor (DXCCII): A new active device for

tunable continuous-time filters", International Journal of Electronics, vol. 89, pp. 913-

923, 2002,

[17] S. Maheshwari, M. S. Ansari, "Catalog for realizations of DXCCII using commercially

available ICs and applications", Radioengineering, vol. 21, pp. 281-289, 2012.

[18] I. A. Khan, M. T. Simsim, "A novel impedance multiplier using low voltage digitally

controlled CCII", IEEE GCC Conference and Exhibition (GCC), Dubai, United Arab

Emirates, pp. 19-22, 2011.

[19] S. A. Mahmoud, M. A. Hashiesh, A. M. Soliman, "Low-voltage digitally controlled fully

differential current conveyor", IEEE Transactions on Circuits and Devices-I, vol. 52, pp.

2055-2064, 2005.

[20] A. A. El-adway, A. M. Soliman, H. O. Elwan, "A novel fully differential current

conveyor and its application for analog VLSI", IEEE Transactions on Circuits and

Systems-IL• Analog and Digital Signal Processing, vol. 47, pp. 306-313, 2000.

[21] A. M. Soliman, "Generation of current conveyor based all-pass filters from op-amp based

circuits", IEEE Transactions on Circuits and Systems-IL• Analog and Digital Signal


[22] A. M. Soliman, "Realization of operational-amplifier all-pass network", Electronics

Letters, vol. 9, pp. 67-68, 1973.

[23] A. M. Soliman, "Inductor less realization of an all pass transfer function using current

conveyors", IEEE Transactions on Circuit Theory, vol. CT-20, pp. 80-81, 1973.

186

[24] E. Yuce, K. Pal, S. Minaei, "A high input impedance voltage-mode all-pass/notch filter using a single variable gain current conveyor", Journal of Circuits Systems and Computers, vol. I7, pp. 827-834, 2008.

[25] S. Minaei, 0. Cicekoglu, "A resistor less realization of the first order all-pass filter", International Journal of Electronics, vol. 93, pp. 177-183, 2006.

[26] S. Minaei, E. Yuce, "Novel voltage-mode all-pass filter based on using DVCCs", Circuits Systems and Signal Processing, vol. 29, pp. 391-402, 2010.

[27] D. Biolek, V. Biolkova, "First order voltage-mode all-pass filter employing one active element and one grounded capacitor", Analog Integrated Circuits and Signal Processing, vol. 65, pp. 123-129, 2010.

[28] D. Biolek, V. Biolkova, "All pass filter employing one grounded capacitor and one active

element", Electronics Letters, vol. 45, pp. 807-808, 2009.

[29] M. A. Ibrahim, H. Kuntman, 0. Cicekoglu, "First-order all-pass filter canonical in the

number of resistors and capacitors employing a single DDCC", Circuits Systems and Signal Processing, vol. 22, pp. 525-536, 2003.

[30] M. A. Ibrahim, H. Kuntman, S. Ozcan, 0. Suvak, 0. Cicekoglu, "New first order

inverting type second generation current conveyor based all-pass sections including

canonical forms", Electrical Engineering, vol. 89, pp. 299-301, 2004.

[31] J. W. Homg, C. L. Hou, C. M. Chang, W. Y. Chung, C. T. Lin, 1. C. Shiu, W. Y. Chiu, "First-order all-pass filter and sinusoidal oscillators using DDCCs", International Journal

of Electronics, vol. 93, pp. 457-466, 2006.

[32] I. A. Khan, S. Maheshwari, "Simple first ordcr all-pass section using a single CCII",

International Journal of Electronics, vol. 87, pp. 303-306, 2000.

[33] S. Maheshwari, 1. A. Khan, "Novel first order all- pass sections using a single CCIII",


[34] S. Maheshwari, I. A. Khan, J. Mohan, "Grounded capacitor first-order filters including

canonical forms", Journal of Circuits Systems and Computers, vol. 15, pp. 289-300,

2006.

[35] S. S. Gupta, R. Senani, "Grounded capacitor current mode SRCO: Novel application of

DVCCC", Electronics Letters, vol. 36, pp. 195-196, 2000.

187

[36] K. Pal, "Realization of current conveyor all-pass networks", International Journal of


[37] B. Metin, O. Cicekoglu, "Component reduced all-pass filter with a grounded capacitor

and high impedance input", International Journal of Electronics, vol. 96, pp. 445-455,

2009.

[38] B. Metin, O. Cicekoglu, K. Pal, "DDCC based all-pass filters using minimum number of

passive elements", in 50th Midwest Symposium on Circuits and Systems (MWSCAS

2007), pp. 518-521, 2007.

[39] O. Cicekoglu, H. Kuntman, S. Berk, "All-pass filters using a single current conveyor",


[40] S. J. G. Gift, "The applications of all-pass filters in the design of multiphase sinusoidal

systems", Microelectronics Journal, vol. 31, pp. 9-13, 2000.

[41] S. J. G. Gift, B. Maundy, "A novel circuit element and its application in signal

amplification", International Journal of Circuit Theory and Applications, vol. 36, pp.

219-231, 2008.

[42] S. Maheshwari, "New voltage and current-mode APS using current controlled conveyor",


[43] S. Maheshwari, "High input impedance VM-APSs with grounded passive elements", IET

Circuits Devices and Systems, vol. 1, pp. 72-78, 2007.

[44] S. Maheshwari, "High input impedance voltage-mode first-order all-pass sections",

International Journal of Circuit Theory and Applications, vol. 36, pp. 511-522, 2008.

[45] S. Maheshwari, "Voltage-mode all-pass filters including minimum component count

circuits", Active and Passive Electronic Components, pp.1-5, 2007.

[46] S. Maheshwari, "Analogue signal processing applications using a new circuit topology",

IET Circuits Devices and Systems, vol. 3, pp. 106-115, 2009.

[47] S. Maheshwari, J. Mohan, D. S. Chauhan, "Voltage-mode cascadable all pass sections

with two grounded passive components and one active elements", IET Circuits Devices

and Systems, vol. 4, pp. 113-122, 2010.

[48] A. Toker, S. Ozcan, H. Kuntman, O. Cicekoglu, "Supplementary all-pass sections with

reduced number of passive elements using a single current conveyor", International

Journal of Electronics, vol. 88, pp. 969-976, 2001.

188

[49] T. Tsukutani, H. Tsunetsugu, Y. Sumi, N. Yabuki, "Electronically tunable first-order all-

pass circuit employing DVCC and OTA", International Journal of Electronics, vol. 97, pp. 285-293, 2010.

[50] J. W. Honig, "Current conveyors based all-pass filters and quadrature oscillators

employing grounded capacitors and resistors", Computers and Electrical Engineering,

vol. 31, pp. 81-92, 2005.

[51] H. P. Chen, K. H. Wu, "Grounded-capacitor first-order filter using minimum

components", IEICE Transactions on Fundamentals of Electronics Communications and

Computer Sciences, vol. E89-A, pp. 3730-3731, 2006.

[52] M. Higashimura, Y. Fukui, "Realization of all-pass networks using a current conveyor",


[53] J. Mohan, S. Maheshwari, D. S. Chauhan, "Voltage-mode cascadable all-pass sections

using single active element and grounded passive components", Circuits and Systems,

vol. 1, pp. 5-11, 2010.

[54] J. Mohan, S. Maheshwari, D. S. Chauhan, "Minimum component based first order all-

pass filter with inverting and non-inverting outputs", International Journal of Recent

Trends in Engineering, vol. 3, pp. 61-64, 2010.

[55] D. Biolek, A. U. Keskin, V. Biolkova, "Grounded capacitor current-mode single resistor

controlled oscillator using a single modified current differencing transconductance

amplifier", IET Circuit Devices and Systems, vol. 4, pp. 496-502, 2010.

[56] S. Maheshwari, "Current-mode third order quadrature oscillator", IET Circuits Devices

and Systems, vol. 4, pp. 188-195, 2010.

[57] S. Maheshwari, S. V. Singh, D. S. Chauhan, "Electronically tunable low-voltage mixed-

mode universal biquad filter", JET Circuits Devices and Systems, vol. 5, pp. 149-158,

2011.

[58] R. Trejo-Guerra, E. Tlelo-Cuautle, C. Sanchez-Lopez, J. M. Munoz-Pacheco, C. Cruz-

Hernandez, "Realization of multiscroll chaotic attractors by using current-feedback

operational amplifier", Revista Mexicana de Fisica, vol. 56, pp. 268-274, 2010.

[59] E. Tlelo-Cuautle, M. A. Duarte-Villasenor, I. Guerra-Gomez, "Automatic synthesis of

VFs and VMs by applying genetic algorithms", Circuits Systems and Signal Processing,

vol. 27, pp. 391-403, 2008.

189

[60] C. L. Hou, C. C. Huang, Y. S. Lan, J. J. Shaw, C. M. Chang, "Current-mode and voltage-

mode universal biquads using a single current-feedback amplifier", International Journal of Electronics, vol. 86, pp. 929-932, 1999.

[61] A. U. Keskin, "Multifunction biquad using a single CDBA", Electrical Engineering, vol. 88, pp. 353-356, 2006.

[62] A. U. Keskin, "Voltage mode notch filters using single CDBA", Frequenz, vol. 59, pp. 225-228, 2005.

[63] S. Ozcan, H. Kuntman, 0. Cicekoglu, "Multi-input single-output filter with reduced

number of passive elements using single current conveyor", Computers and Electrical

Engineering, vol. 29, pp. 45-53, 2003.

[64] N. A. Shah, S. Z. Iqbal, "Versatile voltage-mode universal filter biquad filter using the

op-amp pole", International Journal of Electronics, vol. 94, pp. 75-79, 2007.

[65] B. Metin, 0. Cicekoglu, "Novel minimum component second order low Q all-pass and

notch filters with Inverting second generation current conveyor", IJCI Proceedings of

International Conference on Signal Processing, ISSN 1304-2386, pp. 1, 2003.

[66] C. P. Chong, K. C. Smith, "Biquadratic filter sections employing a single current

conveyor", Electronics Letters, vol. 22, pp. 1662-1663, 1986.

[67] V. K. Singh, R. Senani, "New multifunction active filter configuration employing current

conveyors", Electronics Letters, vol. 26, pp. 1814-1815, 1990.

[68] M. Higashimura, "Realisation of voltage-mode biquads using CCIIs", Electronics

Letters, vol. 27, pp. 1345-1346, 1991.

[69] C. M. Chang, M. S. Lee, "Universal voltage-mode filter with three inputs and one output

using three current conveyors and one voltage follower", Electronics Letters, vol. 30, pp.

2112-2113, 1994.

[70] J. W. Horng, J. R. Lay, C. W. Chang, M. H. Lee, "High input impedance voltage-mode

multifunction filters using plus type CCIIs", Electronics Letters, vol. 33, pp. 472-473,

1997.

[71] J. W. Horng, "High input impedance voltage-mode universal biquadratic filter using three

plus type CCIIs", IEEE Transactions on Circuit & Systems, vol. 48, pp. 996-997, 2001.

[72] A. M. Soliman, "Two novel RC canonic band-pass network using current conveyor",

International Journal Electronics, vol. 42, pp. 49-54, 1977.

190

[73] R. Nandi, "Active inductance using current conveyor and their application in a simple

band-pass filter realization", Electronics Letters, vol. 14, pp. 373-375, 1978. [74] S. Maheshwari, "High performance voltage-mode multifunction filter with minimum

component count", WSEAS Transactions on Electronics, vol. 5, pp. 244-249, 2008. [75] A.M. Soliman, "Current-mode universal filter", Electronics Letters, vol. 32, pp. 1420-

1421, 1995.

[76] D. Biolek, V. Biolkova, "Three CDTA current-mode biquad", WSEAS Transactions on

Circuits and Systems, vol. 4, pp. 1227-1232, 2005.

[77] M. T. Abuelma'atti, M. H. Khan, "Low component current-mode universal filter",


[78] O. Cicekoglu, "Current mode biquad with a minimum number of passive elements",

IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing,

vol. 48, pp. 221-222, 2001.

[79] R. K. Sharma, R. Senani, "Universal current mode biquad using a single CFOA",


[80] A.U. Keskin, E. Hancioglu, "Current mode multifunction filter using two CDBAs",

International Journal of Electronics and communication (AEU), vol. 59, pp. 495-498,

2005.

[81] M. A. Ibrahim, S. Minaei, H. Kuntman, "A 22.5MHz current mode KEN biquad using

differential voltage current conveyor", International Journal of Electronics and

Communication (AEU), vol. 59, pp. 311-318, 2005.

[82] S. Minaei, M. A. Ibrahim, "A mixed-mode KHN-biquad using DVCC and grounded

passive elements suitable for direct cascading", International Journal of Circuit Theory

andApplications, vol. 37, pp. 793-810, 2009.

[83] S. Minaei, S. Turkoz, "New current-mode current-controlled universal filter with single

input and three outputs", International Journal of Electronics, vol. 88, pp. 333-337, 2001.

[84] E. Yuce, S. Minaei, "Universal current-mode filters and parasitic impedance effects on

the filter performances", International Journal of Circuit Theory and Applications, vol.

36, pp. 161-171, 2008.

191

[85] S. Minaei, 0, Cicekoglu, H. Kuntman, S. Turkoz, "High output impedance current-mode

low pass, band pass and high pass filters using current controlled conveyors",


[86] S. Minaei, 0. Cicekoglu, H. Kuntman, et'al, "New Realizations of Current-Mode and

Voltage-Mode Multifunction Filters without External Passive Elements", International

Journal of Electronics and Communication (AEU), vol. 57, pp. 63-69, 2003.

[87] E. Yuce, S. Tokat, S. Minaei, O. Cicekoglu, "Stability problems in universal current-

mode filters", International Journal of Electronics and Communication (AEU), vol. 61,

pp. 580-588, 2007.

[88] S. Maheshwari, "Current-mode filters with high output impedance and employing only

grounded components", WSEAS Transactions on Electronics, vol. 5, pp. 238-43, 2008.

[89] T. Tsukutani, Y. Sumi, N. Yabuki, "Novel current mode biquadratic circuits using only

plus type DO-DVCCs and grounded passive components", International Journal of


[901 T. Tsukutani, Y. Sumi, N. Yabuki, "Electronically tunable current-mode universal

biquadratic filter using CCCDBA", ISPACS 2008, vol. 8-11, pp. 1-4, 2009.

[91 ] T. Tsukutani, M. Higashimura, Y. Sumi, Y. Fukui, "Electronically tunable current-mode

active-only biquadratic filter", International Journal of Electronics, vol. 87, pp. 307-

314,2000.

[92] T. Tsukutani, M. Higashimura, Y. Sumi, Y. Fukui, "Current-mode biquad using OTAs

and CF ", Electronics letters, vol. 39, pp. 262-263, 2003.

[93] T. Katoh, T. Tsukutani, Y. Sumi, Y. Fukui, "Electronically Tunable Current-Mode

Universal Filter Employing CCCIIs and Grounded Capacitors", ISPAC-2006, vol. 12-

15, pp. 107-110, 2006.

[94] T. Tsukutani, Y. Sumi, S. Iwanari, Y. Fukui, "Novel current-mode biquad using MO-

CCC1Is and grounded capacitors", ISPAC-2005, vol. 13-16, pp. 433-436, 2005.

[95] Y. Sumi, T. Tsukutani, N. Yabuki, "Novel current-mode biquadratic circuit using only

plus type DO-DVCCCs", ISPACS-2008, vol. 8-11, pp. 1-4, 2009.

[96] H. P. Chen, S. S. Shen, "A versatile universal capacitor-grounded voltage-mode filter

using DVCCs", ETRIJournal, vol. 29, pp. 470-476, 2007.

192

[97] G. W. Roberts, A. S. Sedra, "A general class of current amplifier based biquadratic filter

circuits", IEEE Transactions on Circuits and Systems-I, vol. 39, pp. 257-263, 1992.

[98] A. M. Soliman, "Current conveyor filters: classification and review", Microelectronic

Journal, vol. 29, pp. 133-149, 1998.

[99] H. P. Chen, W. S. Yang, "High-input and low-output impedance voltage-mode universal

DDCC and FDCCII filter", IEICE Transactions on Electronics, vol. E91-C, pp. 666-669,

2008.

[ 100] S. Maheshwari, I. A. Khan, "Novel cascadable current-mode translinear-C universal

filter", Active and Passive Electronic Components, vol. 27, pp. 215-218, 2004.

[101] S. Maheshwari, I. A. Khan, "High performance versatile translinear-C universal filter",

Journal of Active and Passive Electronic Devices, vol. 1, pp. 41-51, 2005.

[102] I. A. Khan, M. H. Zaidi, "Multifunctional translinear-C current mode filter",


[103] M. Sagbas, U. E. Ayten, H. Sedef, "Current and voltage transfer function filters using a

single active device", JET Circuits Devices and Systems, vol. 4, pp. 78-86, 2010.

[104] D. Biolek, J. Bajer, V. Biolkova, Z. Kolka, M. Kubicek, "Z Copy - Controlled Gain -

Current Differencing Buffered Amplifier and its applications", International Journal of

Circuit Theory and Applications, vol. 39, pp. 257-274, 2011.

[105] D. Biolek, V. Biolkova, Z. Kolka, 3. Bajer, "Single-Input Multi-Output Resistor less

Current-Mode Biquad", Proceeding of ECCTD `09, European Conference on Circuit

Theory and Design, pp. 225-228, 2009.

[106] A. U. Keskin, D. Biolek, E. Hancioglu, V. Biolkova, "Current-mode l{_HN filter

employing current differencing transconductance amplifiers", International Journal of

Electronics and Communication (AEU), vol. 60, pp. 443-446, 2006.

[107] I A. Khan, A. M. Nahhas, "Reconfigurable voltage mode first order multifunctional filter

using single low voltage digitally controlled CMOS CCIP', International Journal of

Computer Applications, vol. 45 , pp. 37-40, 201-2.

[108] I. A. Khan, M. T. Simsim, P. Beg, "Reconfigurable continuous time current mode first

order multifunctional filter using low voltage digitally controlled CMOS CCI1",

International Conference on Multimedia, Signal Processing and Communication

Technologies, pp. 5-8, 2011.

193

[109] R. A. Saad, A. M. Soliman, "On the systematic synthesis of CCII-based floating

simulators", International Journal of Circuit Theory and Applications, vol. 38, pp. 935-

967, 2010.

[110] K. Pal, "Novel floating inductance using current conveyors", Electronics Letters, vol. 17, pp. 638, 1981.

[111] 1. A. Khan, M. H. Zaidi, "A novel ideal floating inductor using translinear conveyors,"

Active and Passive Electronic Components, vol. 26, pp. 87-89, 2003.

[112] F. Kacar, A. Yesil, "Novel grounded parallel inductance simulators realization using a

minimum number of active and passive components", Microelectronics Journal, vol. 41,

pp. 632-63 8, 2010.

[113] R. Schaumann, M. E. Valkenburg, "Design of analog filters", Oxford University Press,

New York, 2005.

[114] F. Kacar, B. Metin, H. Kuntman, " A new CMOS dual-X second generation current

conveyor (DXCC-Il) with an FDNR circuit application", International Journal of

Electronics and communication (AEU), vol. 64, pp. 774-778, 2010.

[115] M. Bhusan, R. W. Newcomb, "Grounding of capacitors in integrated circuits",


[116] W. Bolton, "Measurement and instrumentation systems, Newnes", Oxford, 1996.

[117] J. D. Gibson, "The communications handbook", CRC Press, Boca Raton, 1997.

[118] R. Holzel, "A simple wide-band sine wave quadrature oscillator", IEEE Transactions on

Instrumentation and Measurement, vol. 42, pp. 758-760, 1993.

[119] I. A. Khan, S. Khwaja, "An integrable gm-C quadrature oscillator", International Journal

of Electronics, vol. 87, pp. 1353-1357, 2000.

[120] M. T. Ahmed, I. A. Khan, N. Minhaj, "On transconductance-C quadrature oscillators",


[121] A. M. SoIiman, "Simple sinusoidal RC oscillators using current conveyors",


[122] R. Senani, "New canonic single resistor controlled oscillator using a single current

conveyor", Electronics Letters, vol. 15, pp. 568-569, 1979.

194

[123] S. S. Gupta, R. K. Sharma, D. R. Bhaskar, R. Senani, "Sinusoidal oscillators with explicit

current output employing current-feedback op-amps", International Journal of Circuit Theory and Application, vol. 38, pp. 131-147, 2010.

[124] D. Biolek, A. U. Keskin, V. Biolkova, "Quadrature oscillator using CDTA-based integrators", WSEAS Transactions on Electronics, vol. 3, pp. 463-469,2006.

[125] J. W. Horng, "Current-mode quadrature oscillator with grounded capacitors and resistors using two DVCCs", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, pp. 2152-2154, 2003.

[126] S. S. Gupta, R. Senani, "Grounded-capacitor current-mode SRCO: novel application of DVCCC", Electronics Letters, vol. 36, pp. 195-196, 2000.

[127] S. S. Gupta, R. Senani, "Realization of SRCOs using all grounded passive elements", Frequenz, vol. 57, pp. 1-2, 2003.

[128] V. Kumar, A. U. Keskin, K. Pal, "DVCC based single element controlled oscillators

using all grounded components and simultaneous current voltage mode outputs", Frequenz, vol. 59, pp. 7-8, 2005.

[129] S. Maheshwari, B. Chaturvedi, "High output impedance CMQO using DVCCs and

grounded components", International Journal of Circuit Theory and Application, vol. 39, pp. 427-435, 2011.

[130] M. S. Ansari, S. Maheshwari, "Electronically tunable MOSFET-C mixed-mode quadrature oscillator", International Conference on Multimedia Signal Processing and

Communication Techniques-2009, pp. 158-160, IEEE:doi 10.11 09/mspct.2009.5 164199,

2009. [131] M. S. Ansari, S. Sharma, "DXCC-Ii based mixed mode electronically tunable quadrature

oscillator with grounded capacitors", Advances in Computing, Communication and

Control Communications in Computer and Information Science, vol. 125, pp. 515-521,

2011.

[1321

S. Maheshwari, I. A. Khan, "Mixed mode quadrature oscillator using translinear conveyors and grounded components", International Conference on Multimedia Signal Processing and Communication Techniques-2011, pp. 153-55, IEEE:doi 10.11091mspct.2011.6150462, 2011.

195

[133] 3. Mohan, S. Maheshwari, I. A. Khan, "Mixed-mode quadrature oscillators using single

FDCCII", Journal ofActive and Passive Electronic Devices, vol. 2, pp. 227-234, 2007.

[ 134] P. Lamun, P. Phasukkit, M. Kumngern, K. Dejhan, "A new mixed-mode quadrature

oscillator using a single CCCDTA", International Conference on Electrical

Engineering/Electronics, Computer, Telecommunications and Information Technology

(ECTI-CON)-2011, pp. 141-144, IEEE:doi 10.1109/ECTICON.2011.5947791, 2011.

[135] P. Beg, M. S. Ansari, M. A. Siddiqi, "DXCC-II based mixed-mode three phase

oscillator", International Conference on Multimedia Signal Processing and

Communication Technologies-2011, pp. 9-11, IEEE:doi 10.1 109/MSPCT.201 1.6150507,

2011.

[136] M. T. Abuelma'atti, M. A. Al-qahtani, "A new current controlled multiphase sinusoidal

oscillator using translinear conveyors", IEEE Transactions on Circuits and Systems-IL•

Analog and Digital Signal Processing, vol. 45, pp. 881-885, 1998.

[137] L A. Khan, P. Beg, M. T. Ahmad, "First order current-mode filters and multiphase

oscillators using CMOS MOCCIIs", Arabian Journal for Science and Engineering, vol.

32, pp. 117-126, 2007.

[138] D. R. Bhaskar, S. S. Gupta, R. Senani, A. K. Singh, "New CFOA-based Sinusoidal

Oscillators retaining independent control of oscillation frequency even under the

influence of parasitic impedances", Analog Integrated Circuits and Signal Processing,

vo]. 73, no. 1, pp. 427-437, 2012.

[139] S. Maheshwari, "Voltage-mode four-phase sinusoidal generator and its useful

extensions", Active and Passive Electronic Components, vol. 2013, pp. 8, 2013.

doi :10.1155120131685939

[140] A. M. Soliman, "Two integrator loop quadrature oscillators: A review", Journal of

Advance Research, vol. 4, pp. 1-11, 2013.

[141] G. Souliotis, C. Psychalinos, "Harmonic oscillators realized using current amplifiers and

grounded capacitors", International Journal of Circuit Theory and Application, vol. 35,

pp. 93-104, 2007.

[ 142]

A. U. Keskin, D. Biolek, "Current mode quadrature oscillator using current differencing

transconductance amplifier", IEE Proceeding on Circuits Devices and Systems, vol. 153,

pp. 214-218, 2006.

196

THESIS

[143] J. W. Horng, H. Lee, J. Y. Wu, "Electronically tunable third-order quadrature oscillator

using CDTAs", Radioengineering, vol. 19, pp. 326-330, 2010.

[144] S. Maheshwari, 1. A. Khan, "Current controlled third order quadrature oscillator", IRS

Proceeding on Circuits Devices and Systems, vol. 152, pp. 605-607, 2005.

[145] J. W. Horng, "Current/voltage-mode third-order quadrature oscillator employing two

multiple outputs CCIIs and grounded capacitors", Indian Journal of Pure and Applied Physics, vol. 49, pp. 494-498, 2011.

[146] M. Kumngern, S. Junnapiya, "Current-mode third-order quadrature oscillator using

minimum elements", International Conference on Electrical Engineering and

Informatics, pp. 1-4, 2011.

[147] M. Kumngern, P. Lamun, K. Dejhan, "Current- mode quadrature oscillator using current

differencing transconductance amplifiers", International Journal of Electronics, vol. 99,

pp. 971-986, 2012.

[148] V. Biolkova, J. Bajer, D. Biolek, "Four-phase oscillators employing two active

elements", Radioengineering, vol. 20, pp. 334-339, 2011.

[149] T. Tsukutani, Y. Sumi, Y. Fukui, "Electronically controlled current mode oscillators

using MO-OTAs and grounded capacitors", Frequenz, vol. 60, pp. 220-223, 2006.

[150] P. Prommee, K. Dejhan, "An integrable electronic controlled sinusoidal oscillator using

CMOS operational transconductance amplifier", International Journal of Electronics,

vol. 89, pp. 365-379, 2002.

[151] G. Souliotis, C. Psychalinos, "Electronically controlled multiphase sinusoidal oscillators

using current amplifiers", International Journal of Circuit Theory and Application, vol.

37, pp. 43-52, 2009.

[152] A. S. Sedra, K. C. Smith, "Microelectronic Circuits", 4th edition, Oxford University

Press, New York, 1998.

[153] R. L. Geiger, P. E. Allen, N. R. Strader, "VLSI design techniques for analog and digital

circuits", McGraw-Hill Publishing Company, New York, 1990.

[154] B. Razavi, "Design of analog CMOS integrated circuits", Tata McGraw Hill Edition,

2004.

[1551 P. E. Allen, D. R. Holberg, "CMOS analog circuit design", Second edition, Oxford

University Press, 2007,

197

[156] K. M. Al-Ruwaihi, "A floating voltage-controlled linear resistor and its application to

active RC filters", International Journal of Elkctronics, vol. 92, pp. 483-498, 1997.

[157] C. S. Park, R. Schaumann, "A high-frequency CMOS linear transconductance element",

IEEE Transactions on Circuits and Systems, vol. 33, pp. 1132-1137, 1986.

[158] Z. Wang, "2-MOSFET trans-resistor with extremely low distortion for output reaching

supply voltages", Electronics Letters, vol. 26, pp. 951-952, 1990.

198

Date post:	21-Feb-2021
Category:	Documents
Upload:	others
View:	1 times
Download:	0 times

't'rte :° - / I r e otter,=~. , aka AD / r? r f BHARTEND-...

Documents